CN109669887A - 高带宽存储器、高带宽存储器系统及其命令处理方法 - Google Patents

高带宽存储器、高带宽存储器系统及其命令处理方法 Download PDF

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Publication number
CN109669887A
CN109669887A CN201810980551.7A CN201810980551A CN109669887A CN 109669887 A CN109669887 A CN 109669887A CN 201810980551 A CN201810980551 A CN 201810980551A CN 109669887 A CN109669887 A CN 109669887A
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China
Prior art keywords
function
high bandwidth
memory
bandwidth memory
controller
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Pending
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CN201810980551.7A
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English (en)
Chinese (zh)
Inventor
张牧天
克里希纳·特佳·马拉迪
牛迪民
郑宏忠
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN109669887A publication Critical patent/CN109669887A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Software Systems (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
CN201810980551.7A 2017-10-17 2018-08-27 高带宽存储器、高带宽存储器系统及其命令处理方法 Pending CN109669887A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762573390P 2017-10-17 2017-10-17
US62/573,390 2017-10-17
US15/854,557 US10866900B2 (en) 2017-10-17 2017-12-26 ISA extension for high-bandwidth memory
US15/854,557 2017-12-26

Publications (1)

Publication Number Publication Date
CN109669887A true CN109669887A (zh) 2019-04-23

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CN201810980551.7A Pending CN109669887A (zh) 2017-10-17 2018-08-27 高带宽存储器、高带宽存储器系统及其命令处理方法

Country Status (5)

Country Link
US (3) US10866900B2 (enExample)
JP (1) JP2019075101A (enExample)
KR (1) KR102289095B1 (enExample)
CN (1) CN109669887A (enExample)
TW (1) TWI750406B (enExample)

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Also Published As

Publication number Publication date
US20210096999A1 (en) 2021-04-01
US11940922B2 (en) 2024-03-26
JP2019075101A (ja) 2019-05-16
KR20190043072A (ko) 2019-04-25
US20190114265A1 (en) 2019-04-18
KR102289095B1 (ko) 2021-08-12
TW201917567A (zh) 2019-05-01
US20230119291A1 (en) 2023-04-20
US11556476B2 (en) 2023-01-17
TWI750406B (zh) 2021-12-21
US10866900B2 (en) 2020-12-15

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