KR102289095B1 - 인-메모리 명령 처리 방법, 이를 적용하는 고대역폭 메모리 및 시스템 - Google Patents
인-메모리 명령 처리 방법, 이를 적용하는 고대역폭 메모리 및 시스템 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/45—Caching of specific data in cache memory
- G06F2212/452—Instruction code
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Software Systems (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762573390P | 2017-10-17 | 2017-10-17 | |
| US62/573,390 | 2017-10-17 | ||
| US15/854,557 US10866900B2 (en) | 2017-10-17 | 2017-12-26 | ISA extension for high-bandwidth memory |
| US15/854,557 | 2017-12-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20190043072A KR20190043072A (ko) | 2019-04-25 |
| KR102289095B1 true KR102289095B1 (ko) | 2021-08-12 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020180080925A Active KR102289095B1 (ko) | 2017-10-17 | 2018-07-12 | 인-메모리 명령 처리 방법, 이를 적용하는 고대역폭 메모리 및 시스템 |
Country Status (5)
| Country | Link |
|---|---|
| US (3) | US10866900B2 (enExample) |
| JP (1) | JP2019075101A (enExample) |
| KR (1) | KR102289095B1 (enExample) |
| CN (1) | CN109669887A (enExample) |
| TW (1) | TWI750406B (enExample) |
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| US11127442B2 (en) * | 2019-12-06 | 2021-09-21 | Xilinx, Inc. | Data transfers between a memory and a distributed compute array |
| CN115427925A (zh) | 2019-12-26 | 2022-12-02 | 美光科技公司 | 用于堆叠存储器系统的主机技术 |
| EP4553663A3 (en) | 2019-12-26 | 2025-07-30 | Micron Technology, Inc. | Truth table extension for stacked memory systems |
| US12386777B2 (en) | 2020-01-07 | 2025-08-12 | SK Hynix Inc. | Processing-in-memory (PIM) device to perform a memory access operation and an arithmetic operation in response to a command from a PIM controller and a high speed interface, respectively |
| US12136470B2 (en) | 2020-01-07 | 2024-11-05 | SK Hynix Inc. | Processing-in-memory (PIM) system that changes between multiplication/accumulation (MAC) and memory modes and operating methods of the PIM system |
| US11829760B2 (en) * | 2020-01-07 | 2023-11-28 | SK Hynix Inc. | Processing-in-memory device and processing-in-memory system including the same |
| TWI868210B (zh) * | 2020-01-07 | 2025-01-01 | 韓商愛思開海力士有限公司 | 記憶體中處理(pim)系統 |
| US11635911B2 (en) * | 2020-01-07 | 2023-04-25 | SK Hynix Inc. | Processing-in-memory (PIM) system and operating methods of the PIM system |
| US11983508B2 (en) | 2020-01-07 | 2024-05-14 | SK Hynix Inc. | Processing-in-memory (PIM) system and operating methods of the PIM system |
| KR102831057B1 (ko) | 2020-01-20 | 2025-07-07 | 삼성전자주식회사 | 고대역폭 메모리 및 이를 포함하는 시스템 |
| US11226816B2 (en) | 2020-02-12 | 2022-01-18 | Samsung Electronics Co., Ltd. | Systems and methods for data placement for in-memory-compute |
| US11281554B2 (en) * | 2020-03-17 | 2022-03-22 | Samsung Electronics Co., Ltd. | System and method for in-memory computation |
| KR102786984B1 (ko) | 2020-09-03 | 2025-03-27 | 삼성전자주식회사 | 메모리 장치, 그것을 포함하는 메모리 시스템, 그것을 제어하는 제어기 및 그것의 동작 방법 |
| US11868777B2 (en) * | 2020-12-16 | 2024-01-09 | Advanced Micro Devices, Inc. | Processor-guided execution of offloaded instructions using fixed function operations |
| EP4024222A1 (en) * | 2021-01-04 | 2022-07-06 | Imec VZW | An integrated circuit with 3d partitioning |
| CN115469800A (zh) | 2021-06-10 | 2022-12-13 | 三星电子株式会社 | 数据处理系统以及用于访问异构存储器系统的方法 |
| CN113643739B (zh) * | 2021-09-02 | 2025-02-07 | 西安紫光国芯半导体股份有限公司 | 一种llc芯片及缓存系统 |
| CN117350911A (zh) * | 2022-06-28 | 2024-01-05 | 华为技术有限公司 | 一种着色器输入数据的处理方法和图形处理装置 |
| KR20250019482A (ko) * | 2023-08-01 | 2025-02-10 | 삼성전자주식회사 | 가속기, 이를 포함하는 전자 장치 및 그 동작 방법 |
| US12052116B1 (en) * | 2024-03-28 | 2024-07-30 | Persimmons, Inc. | Methods for arbitrating the role of bus master among a plurality of host devices |
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| WO2017172258A1 (en) | 2016-03-30 | 2017-10-05 | Qualcomm Incorporated | Providing space-efficient storage for dynamic random access memory (dram) cache tags |
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2017
- 2017-12-26 US US15/854,557 patent/US10866900B2/en active Active
-
2018
- 2018-07-12 KR KR1020180080925A patent/KR102289095B1/ko active Active
- 2018-08-27 CN CN201810980551.7A patent/CN109669887A/zh active Pending
- 2018-08-27 TW TW107129831A patent/TWI750406B/zh active
- 2018-09-18 JP JP2018173507A patent/JP2019075101A/ja active Pending
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2020
- 2020-12-14 US US17/121,488 patent/US11556476B2/en active Active
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2022
- 2022-12-14 US US18/081,488 patent/US11940922B2/en active Active
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Also Published As
| Publication number | Publication date |
|---|---|
| US10866900B2 (en) | 2020-12-15 |
| US20190114265A1 (en) | 2019-04-18 |
| US20230119291A1 (en) | 2023-04-20 |
| US11940922B2 (en) | 2024-03-26 |
| JP2019075101A (ja) | 2019-05-16 |
| US20210096999A1 (en) | 2021-04-01 |
| KR20190043072A (ko) | 2019-04-25 |
| CN109669887A (zh) | 2019-04-23 |
| US11556476B2 (en) | 2023-01-17 |
| TWI750406B (zh) | 2021-12-21 |
| TW201917567A (zh) | 2019-05-01 |
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