CN109656870A - A kind of in-orbit dynamic restructuring management system of SRAM type FPGA and method - Google Patents
A kind of in-orbit dynamic restructuring management system of SRAM type FPGA and method Download PDFInfo
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- CN109656870A CN109656870A CN201811378251.8A CN201811378251A CN109656870A CN 109656870 A CN109656870 A CN 109656870A CN 201811378251 A CN201811378251 A CN 201811378251A CN 109656870 A CN109656870 A CN 109656870A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
A kind of system and method for the in-orbit dynamic restructuring management of SRAM type FPGA, support most four-ways, six kinds of model SRAM type FPGA, have power on configuration, dynamic configuration, periodic refreshing, readback refreshing, timing readback, dynamic restructuring, poll verification ability, multinomial task switches under the United Dispatching of dynamic restructuring managing chip, operating mode adjustment is carried out by controlling signal or serial ports control instruction firmly, and inner workings information can be obtained by serial ports control instruction.
Description
Technical field
The present invention relates to a kind of in-orbit dynamic restructuring management system of SRAM type FPGA and methods, and it is reliable to belong to space flight component
Property field and technical field of integrated circuits.
Background technique
It when SRAM type FPGA works in space radiation environment, is influenced by single particle effect, the event of Yi Fasheng single-particle inversion
Barrier and single event function interrupt failure lead to circuit operation error.The common method for repairing such failure is to utilize SRAM type
The characteristic that FPGA can dynamically be reconfigured is timed refreshing (blind brush) to its configured memory array or readback refreshes.
103840822 B of China Patent Publication No. CN, publication date is on June 4th, 2014, entitled " to be based on
A kind of general brush suitable for aerospace FPGA is disclosed in the implementation method of the general refresh circuit of aerospace FPGA of SELECTMAP "
Novel circuit, the circuit execute refreshing, but this electricity to FPGA in the case where reading back check incorrect situation by the way of readback refreshing
Road has the following disadvantages:
(1) configuration and refreshing of single channel SRAM type FPGA are only supported；
(2) it is single to refresh mode, only readback is supported to refresh mode, and the refresh cycle is uncontrollable；
(3) it not can be carried out dynamic configuration；
(4) do not have the ability of in-orbit dynamic restructuring；
(5) do not have the ability for receiving external control instruction adjustment operating mode or switch operating task；
104484214 A of China Patent Publication No. CN, application publication date is on April 1st, 2015, a kind of entitled " SRAM
Integral system is infused in the configuration of type FPGA, refreshing and program ", it discloses and a kind of is realized using integrated management FPGA to SRAM type
The integral system of FPGA configuration, refreshing and in-orbit function switch, but this patent has the following disadvantages:
(1) it is single to refresh mode, only supports periodic refreshing mode；
(2) configuration, refreshing and the in-orbit function switch of single channel SRAM type FPGA are only supported；
(3) configuration, refreshing and the in-orbit function switch to single model XQR2V3000 type FPGA are only supported.
Summary of the invention
The technical problem to be solved by the present invention is it is in-orbit to have overcome the deficiencies of the prior art and provide a kind of SRAM type FPGA
The system and method for dynamic restructuring management supports most four-ways, six kinds of model SRAM type FPGA, has power on configuration, dynamic
The ability that configuration, periodic refreshing, readback refreshing, timing readback, dynamic restructuring, poll verify, multinomial task is in dynamic weight
It is switched under the United Dispatching of structure managing chip, carries out operating mode adjustment by controlling signal or serial ports control instruction firmly,
And inner workings information can be obtained by serial ports control instruction.
The object of the invention is achieved by the following technical programs:
A kind of in-orbit dynamic restructuring management system of SRAM type FPGA, including SRAM type FPGA, dynamic restructuring managing chip, match
Set stream storage chip, dynamic restructuring bit stream storage chip, serial port chip；
The configuration bit stream of overall format is stored on the configuration bit stream storage chip；The dynamic restructuring bit stream storage chip
Upper storage dynamic restructuring bit stream；Then the serial port chip is sent for receiving external control instruction and external dynamic reconstruct bit stream
To the dynamic restructuring managing chip；
The dynamic restructuring managing chip is used to read the configuration bit stream stored in the configuration bit stream memory to SRAM
Type FPGA is configured and is refreshed；The dynamic restructuring managing chip is deposited for reading in the dynamic restructuring bit stream storage chip
The configuration bit stream of storage configures SRAM type FPGA, refreshed and is reconstructed；The dynamic restructuring managing chip is to the SRAM type
The bit stream of FPGA carries out CRC check, judges whether to execute refreshing according to CRC check result；The dynamic restructuring managing chip will
Work state information is sent to the serial port chip；The dynamic restructuring managing chip is written after receiving external dynamic reconstruct bit stream
In the dynamic restructuring bit stream storage chip.
The above-mentioned in-orbit dynamic restructuring management system of SRAM type FPGA, the dynamic restructuring managing chip can be to the dynamic
The Bose-Chaudhuri-Hocquenghem Code bit stream saved in reconstruct bit stream storage chip is polled verification, the fan when verifying error where misregistration
Regional address.
The above-mentioned in-orbit dynamic restructuring management system of SRAM type FPGA, the dynamic restructuring managing chip can read described
Device ID in the configuration register of SRAM type FPGA, then recognition means model.
The above-mentioned in-orbit dynamic restructuring management system of SRAM type FPGA, the in-orbit dynamic restructuring management system of SRAM type FPGA
Using from and mode the SRAM type FPGA configured, refreshed and readback.
The above-mentioned in-orbit dynamic restructuring management system of SRAM type FPGA, the in-orbit dynamic restructuring management system of SRAM type FPGA
The SRAM type FPGA in most four channels can be configured, be refreshed, in-orbit reconstruct.
The above-mentioned in-orbit dynamic restructuring management system of SRAM type FPGA, the in-orbit dynamic restructuring management system of SRAM type FPGA
It can be to six kinds of models of XQVR300, XQR2V3000, XQR4VSX55, XQR5VSX95T, XQR5VLX155T, XQR5VFX130T
SRAM type fpga chip configured, refreshed, in-orbit reconstruct.
The above-mentioned in-orbit dynamic restructuring management system of SRAM type FPGA, the dynamic restructuring managing chip include master control and scheduling
Module, configuration module, refresh module, readback module, UART module, poll correction verification module, in which:
The master control and scheduler module are for all device works in the in-orbit dynamic restructuring management system of the SRAM type FPGA
The control of operation mode and the scheduling of task；
The configuration module from the configuration bit stream memory or the dynamic restructuring bit stream storage chip for reading
Bit stream is configured, the SRAM type FPGA is then written；
The refresh module from the configuration bit stream memory or the dynamic restructuring bit stream storage chip for reading
Bit stream is configured, then configuration bit stream is pre-processed, is ultimately written the SRAM type FPGA；
The readback module from the configured memory array of the SRAM type FPGA for reading the state of configuration register
Value and configuration bit stream, realize the device recognition to the SRAM type FPGA and CRC check；
The UART module reconstructs bit stream for receiving external control instruction and external dynamic, and according to read states register
Instruction returns to corresponding internal register value；
The poll correction verification module is used to carry out the Bose-Chaudhuri-Hocquenghem Code bit stream saved in the dynamic restructuring bit stream storage chip
Decoding, verification, when verifying error, the poll correction verification module is to the BCH saved in the dynamic restructuring bit stream storage chip
Coding stream is repaired or is recorded.
The above-mentioned in-orbit dynamic restructuring management system of SRAM type FPGA, when verifying error, if the Bose-Chaudhuri-Hocquenghem Code of verification error
When bit stream is less than or equal to 2bit, the poll correction verification module repairs the Bose-Chaudhuri-Hocquenghem Code bit stream of the error, if verification
When the Bose-Chaudhuri-Hocquenghem Code bit stream of error is more than or equal to 3bit, institute of the poll correction verification module to the Bose-Chaudhuri-Hocquenghem Code bit stream of the error
It is recorded in sevtor address.
A kind of in-orbit dynamic reconfiguration method of SRAM type FPGA, using above-mentioned SRAM type FPGA in-orbit dynamic restructuring management system
System, includes the following steps:
Step (1): dynamic restructuring managing chip determines destination channel according to the CON_EN pin status in four channels；
Step (2): dynamic restructuring managing chip carries out power on configuration to the SRAM type FPGA of one of destination channel；
Step (3): dynamic restructuring managing chip carries out device recognition by the device ID of readback destination channel；
Step (4): then dynamic restructuring managing chip passes through the Bose-Chaudhuri-Hocquenghem Code bit stream of the SRAM type FPGA of readback destination channel
Calculate GoldenCRC；
Step (5): repeating step (1)~step (4), completes initialization to the SRAM type FPGA of other destination channels；
Step (6): configuration of the control instruction to configuration bit stream storage chip according to hard control signal and/or from serial ports
The dynamic restructuring bit stream of bit stream and/or dynamic restructuring bit stream storage chip is updated, then according to configuration bit stream storage chip and
Or the operating mode of dynamic restructuring bit stream storage chip is scheduled destination channel task；When task is triggered
Execute dynamic configuration or periodic refreshing or readback refreshing or timing readback, dynamic restructuring or poll verification.
The above-mentioned in-orbit dynamic reconfiguration method of SRAM type FPGA, the poll verification include the following steps:
Step (11): BCH decoding is carried out to the current sector FLASH；
Step (12): if decoding discovery mistake, current sector is recompiled, the progress error correction of data retrography, is entered step
(13), if decoding is directly entered step (13) without discovery mistake；
Step (13): CRC check is carried out to current sector, if verification is correct, is directly entered step (14)；If verifying out
Mistake records the address of faulty sector and updates respective inner register, subsequently into step (14)；
Step (14): circulation executes step (11)~step (13) until being used for the sector of storage configuration bit stream in FLASH
Complete verification finishes.
The present invention has the following beneficial effects: compared with the prior art
(1) present invention supports most four-way SRAM type FPGA to work at the same time, and improves efficiency；
(2) present invention supports six kinds of model SRAM type FPGA, has power on configuration, dynamic configuration, periodic refreshing, readback brush
Newly, the function of timing readback, dynamic restructuring, poll verification, use scope are wide；
(3) present invention adjusts operating mode and switch operating times by controlling signal and serial ports control instruction two ways firmly
Business, controllability is strong, using flexible；
(4) present invention sends instruction by serial ports and obtains internal register value, can real-time monitoring circuit working condition；
(5) present invention is to the data polling verification of FLASH chip storage configuration bit stream using BCH decoding superposition CRC check
Mode, ensure that the reliability of data.
Detailed description of the invention
Fig. 1 is system composition schematic diagram of the invention；
Fig. 2 is flow chart of the method for the present invention；
Fig. 3 is timing refresh flow figure of the invention；
Fig. 4 is readback refresh flow figure of the invention；
Fig. 5 is timing readback flow chart of the invention；
Fig. 6 is poll checking process figure of the invention；
Fig. 7 is the embodiment of the present invention application schematic diagram.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to implementation of the invention
Mode is described in further detail.
A kind of in-orbit dynamic restructuring management system of SRAM type FPGA, including SRAM type FPGA, dynamic restructuring managing chip, match
Set stream storage chip, dynamic restructuring bit stream storage chip, serial port chip；
The configuration bit stream of overall format is stored on the configuration bit stream storage chip；The dynamic restructuring bit stream storage chip
Upper storage dynamic restructuring bit stream；Then the serial port chip is sent for receiving external control instruction and external dynamic reconstruct bit stream
To the dynamic restructuring managing chip；
The dynamic restructuring managing chip is used to read the configuration bit stream stored in the configuration bit stream memory to SRAM
Type FPGA is configured and is refreshed；The dynamic restructuring managing chip is deposited for reading in the dynamic restructuring bit stream storage chip
The configuration bit stream of storage configures SRAM type FPGA, refreshed and is reconstructed；The dynamic restructuring managing chip is to the SRAM type
The bit stream of FPGA carries out CRC check, judges whether to execute refreshing according to CRC check result；The dynamic restructuring managing chip will
Work state information is sent to the serial port chip；The dynamic restructuring managing chip is written after receiving external dynamic reconstruct bit stream
In the dynamic restructuring bit stream storage chip.The dynamic restructuring managing chip can be to the dynamic restructuring bit stream storage chip
The Bose-Chaudhuri-Hocquenghem Code bit stream of middle preservation is polled verification, the sevtor address when verifying error where misregistration.The dynamic weight
Structure managing chip can read the device ID in the configuration register of the SRAM type FPGA, then recognition means model.
The dynamic restructuring managing chip include master control and scheduler module, configuration module, refresh module, readback module,
UART module, poll correction verification module, in which:
The master control and scheduler module are for all device works in the in-orbit dynamic restructuring management system of the SRAM type FPGA
The control of operation mode and the scheduling of task；
The configuration module from the configuration bit stream memory or the dynamic restructuring bit stream storage chip for reading
Bit stream is configured, the SRAM type FPGA is then written；
The refresh module from the configuration bit stream memory or the dynamic restructuring bit stream storage chip for reading
Bit stream is configured, then configuration bit stream is pre-processed, is ultimately written the SRAM type FPGA；
The readback module from the configured memory array of the SRAM type FPGA for reading the state of configuration register
Value and configuration bit stream, realize the device recognition to the SRAM type FPGA and CRC check；
The UART module reconstructs bit stream for receiving external control instruction and external dynamic, and according to read states register
Instruction returns to corresponding internal register value；
The poll correction verification module is used to carry out the Bose-Chaudhuri-Hocquenghem Code bit stream saved in the dynamic restructuring bit stream storage chip
Decoding, verification, when verifying error, the poll correction verification module is to the BCH saved in the dynamic restructuring bit stream storage chip
Coding stream is repaired or is recorded.Specifically, when verifying error, if the Bose-Chaudhuri-Hocquenghem Code bit stream of verification error is less than or equal to
When 2bit, the poll correction verification module repairs the Bose-Chaudhuri-Hocquenghem Code bit stream of the error, if the BCH of verification error is compiled
When code bit stream is more than or equal to 3bit, place sevtor address of the poll correction verification module to the Bose-Chaudhuri-Hocquenghem Code bit stream of the error
It is recorded.
The in-orbit dynamic restructuring management system of SRAM type FPGA, which is used, matches the SRAM type FPGA from simultaneously mode
It sets, refresh and readback.The in-orbit dynamic restructuring management system of SRAM type FPGA can be to the SRAM type in most four channels
FPGA configured, refreshed, in-orbit reconstruct.The in-orbit dynamic restructuring management system of SRAM type FPGA can to XQVR300,
The SRAM type FPGA core of six kinds of models of XQR2V3000, XQR4VSX55, XQR5VSX95T, XQR5VLX155T, XQR5VFX130T
Piece configured, refreshed, in-orbit reconstruct.
A kind of in-orbit dynamic reconfiguration method of SRAM type FPGA, using the in-orbit dynamic restructuring management system of SRAM type FPGA, packet
Include following steps:
Step (1): dynamic restructuring managing chip determines destination channel according to the CON_EN pin status in four channels；
Step (2): dynamic restructuring managing chip carries out power on configuration to the SRAM type FPGA of one of destination channel；
Step (3): dynamic restructuring managing chip carries out device recognition by the device ID of readback destination channel；
Step (4): then dynamic restructuring managing chip passes through the Bose-Chaudhuri-Hocquenghem Code bit stream of the SRAM type FPGA of readback destination channel
Calculate GoldenCRC；
Step (5): repeating step (1)~step (4), completes initialization to the SRAM type FPGA of other destination channels；
Step (6): configuration of the control instruction to configuration bit stream storage chip according to hard control signal and/or from serial ports
The dynamic restructuring bit stream of bit stream and/or dynamic restructuring bit stream storage chip is updated, then according to configuration bit stream storage chip and
Or the operating mode of dynamic restructuring bit stream storage chip is scheduled destination channel task；When task is triggered
Execute dynamic configuration or periodic refreshing or readback refreshing or timing readback, dynamic restructuring or poll verification.
Embodiment:
A kind of in-orbit dynamic restructuring management system of multichannel SRAM type FPGA, comprising: SRAM type FPGA, dynamic restructuring management
Chip, configuration bit stream storage chip PROM, dynamic restructuring bit stream storage chip FLASH, RS485 serial port chip, as shown in Figure 1,
Wherein:
The SRAM type FPGA use from and mode configured, refreshed and readback；
The configuration bit stream of the configuration bit stream storage chip PROM storage overall format, powers on for the SRAM type FPGA
It automatically configures afterwards and the dynamic configuration and refreshing in the course of work；
The dynamic restructuring bit stream storage chip FLASH stores the dynamic restructuring bit stream after Bose-Chaudhuri-Hocquenghem Code, for described
SRAM type FPGA automatically configures after powering on, the dynamic configuration in the course of work, refreshing and in-orbit function switch；
The RS485 serial port chip is to receive external control instruction, return to work state information, infuse dynamic restructuring in reception
The channel of bit stream；
The dynamic restructuring managing chip has following functions:
(1) it reads the configuration bit stream stored in the configuration bit stream memory PROM SRAM type FPGA is configured and brushed
Newly；
(2) the configuration bit stream stored in the dynamic restructuring bit stream storage chip FLASH is read, through decoding to SRAM type
FPGA is configured, refreshed and is reconstructed；
(3) the configuration register acquisition device ID of SRAM type FPGA described in readback, the device type of automatic identification destination channel
Number；
(4) bit stream of SRAM type FPGA described in readback carries out CRC check, is made whether to execute the decision refreshed；
(5) instruction transmitted through the RS485 serial port chip is received, inner workings information or adjustment Working mould are returned
Formula；
(6) the dynamic restructuring bit stream transmitted through the RS485 serial port chip is received, is written after resolve packet and verification
In the dynamic restructuring bit stream storage chip FLASH；
(7) verification is polled to the Bose-Chaudhuri-Hocquenghem Code bit stream saved in the dynamic restructuring bit stream storage chip FLASH, and
FLASH sevtor address when verifying error where misregistration.
The system supports the configuration, refreshing, in-orbit reconstruct of most four channels SRAM type fpga chip, each channel pair
A CON_EN pin is answered, the switch state of the pin decides whether to control the channel, and destination channel need to be by CON_EN
Pin connects high level, and corresponding CON_EN pin need to be grounded by idle channel.
Configuration, refreshing, the in-orbit reconstruct of the SRAM type fpga chip of six kinds of models of the system support, including XQVR300,
XQR2V3000、XQR4VSX55、XQR5VSX95T、XQR5VLX155T、XQR5VFX130T。
The system includes power on configuration, dynamic configuration, periodic refreshing, readback refreshing, timing readback, dynamic restructuring, wheel
Ask the task and operating mode of verification.
The dynamic restructuring managing chip include master control and scheduler module, configuration module, refresh module, readback module,
UART module and poll correction verification module, in which:
The master control and scheduler module for realizing to device operating modes all in system control and task
Scheduling；
The configuration module is from the configuration bit stream memory PROM or the dynamic restructuring bit stream storage chip FLASH
Configuration bit stream is read, is written in the configured memory array of the SRAM type FPGA, is realized to the SRAM type using from simultaneously mode
The power on configuration and the dynamic configuration in the course of work, dynamic restructuring of FPGA；
The refresh module is from the configuration bit stream memory PROM or the dynamic restructuring bit stream storage chip FLASH
Configuration bit stream is read, and configuration bit stream is pre-processed, is stored using the configuration that the SRAM type FPGA is written from simultaneously mode
In array, the refresh operation to the SRAM type FPGA is realized；
The readback module uses from simultaneously mode and reads configuration deposit from the configured memory array of the SRAM type FPGA
The state value and configuration bit stream of device, realize the device recognition to the SRAM type FPGA and CRC check；
The UART module from host computer or other controllers includes dynamic configuration instruction, dynamic weight for receiving
Control instruction and upper note including structure instruction, data polling instruction, operating mode setting instruction and read states register instruction
Dynamic restructuring bit stream, and corresponding internal register value is returned to according to read states register instruction；
The poll correction verification module, for when receiving command adapted thereto, to the dynamic restructuring bit stream storage chip
The Bose-Chaudhuri-Hocquenghem Code bit stream saved in FLASH is decoded, is verified, and is automatically repaired when verifying error to 2bit following error, right
3bit or more wrong place sevtor address is recorded.
A kind of in-orbit dynamic restructuring management method of multichannel SRAM type FPGA includes overall workflow, periodic refreshing stream
Journey, readback refresh flow, timing readback process and poll checking process, specific workflow are as follows:
The overall workflow includes the following steps, as shown in Figure 2:
Step (1): destination channel is determined according to the corresponding CON_EN pin status in four channels；
Step (2): power on configuration is carried out to the SRAM type FPGA in current goal channel；
Step (3): device recognition is carried out by readback device ID；
Step (4): GoldenCRC is calculated by readback bit stream；
Step (5): repeating step (1)~step (4), completes to initialize to all destination channels；
Step (6): being updated internal register according to hard control signal and the control instruction from serial ports, and according to
The operating mode of internal register setting carries out the scheduling of current goal channels operation task, the execution when task is triggered
Corresponding dynamic configuration, periodic refreshing, readback refreshing, timing readback, dynamic restructuring, poll verification；
Step (7): current channel task is arranged corresponding working condition in internal register after the completion of executing and selects
Select next destination channel circulating repetition step (6)~step (7).
The timing refresh flow includes the following steps, as shown in Figure 3:
Step (1): according to pre-set periodic refreshing period timing, when timing then carries out single event function interrupt
Detection；
Step (2): if single event function interrupt failure occurs, entering step (3), if without single event function interrupt event
Barrier, enters step (4)；
Step (3): enabling if dynamic is reconfigured, and matches from reading in the configuration bit stream memory (PROM/FLASH) currently selected
Set stream reconfigures FPGA using from simultaneously mode, if dynamic reconfiguration is forbidden, this operation terminates, and starts again at timing；
Step (4): configuring bit stream from reading in the configuration bit stream memory (PROM/FLASH) currently selected, pre- through code stream
FPGA portion configured memory array is reconfigured using from simultaneously mode after processing, single is executed and refreshes；
Step (5): refresh and complete, start again at timing.
The readback refresh flow includes the following steps, as shown in Figure 4:
Step (1): according to pre-set readback refresh cycle timing, when timing then carries out single event function interrupt
Detection；
Step (2): if single event function interrupt failure occurs, entering step (3), if without single event function interrupt event
Barrier, enters step (4)；
Step (3): enabling if dynamic is reconfigured, and matches from reading in the configuration bit stream memory (PROM/FLASH) currently selected
Set stream reconfigures FPGA, if dynamic reconfiguration is forbidden, this operation terminates, and starts again at timing；
Step (4): using readback bit stream carries out CRC check from FPGA from simultaneously mode, by the school CurrentCRC of generation
It tests code and GoldenCRC is compared, this operation terminates if check results are identical, restarts timing；If check results are different
It causes, then reads configuration bit stream from the configuration bit stream memory (PROM/FLASH) currently selected, it is right after code stream pre-processes
FPGA portion configured memory array is reconfigured, and is executed single and is refreshed；
Step (5): refresh and complete, start again at timing.
The timing readback process includes the following steps, as shown in Figure 5:
Step (1): according to pre-set timing readback period timing, when timing then carries out single event function interrupt
Detection；
Step (2): if single event function interrupt failure occurs, entering step (3), if without single event function interrupt event
Barrier, enters step (4)；
Step (3): enabling if dynamic is reconfigured, and matches from reading in the configuration bit stream memory (PROM/FLASH) currently selected
Set stream reconfigures FPGA, if dynamic reconfiguration is forbidden, this operation terminates, and starts again at timing；
Step (4): using readback bit stream carries out CRC check from FPGA from simultaneously mode, by the school CurrentCRC of generation
Code is tested to save to corresponding internal register；
Step (5): this operation terminates, and starts again at timing.
The poll checking process includes the following steps, as shown in Figure 6:
Step (1): BCH decoding is carried out to the current sector FLASH；
Step (2): if decoding discovery mistake, current sector is recompiled, the progress error correction of data retrography, is entered step
(3), if decoding is directly entered step (3) without discovery mistake；
Step (3): carrying out CRC check to current sector, if verification is correct, illustrates happens is that 2bit and following error,
Error correction is completed in step (2)；If verification error, illustrate happens is that 3bit and the above mistake, is not correctable error, records out
The address of wrong sector simultaneously updates respective inner register；
Step (4): circulation executes step (1)~step (4) until whole for the sector of storage configuration bit stream in FLASH
Verification finishes.
Fig. 7 is the system connection schematic diagram that four-way SRAM type FPGA is worked at the same time, and 7-1~7-4 is to be refreshed/reconstruct
SRAM type FPGA, shared data line, clock line and configuration mode line, 7-5~7-8 are configuration bit stream storage chip PROM, are shared
Clock line and data line respectively correspond 7-1~7- wherein the data saved are the configuration bit streams being cured before the in-orbit application of system
4,7-9 be dynamic restructuring bit stream storage chip FLASH, using 256Mb massive store chip, for receiving matching of infusing on ground
Set stream, subregion 0, subregion 1, subregion 2, the subregion 3 of the chip respectively correspond 7-1~7-4, and 7-10 is using RS485 agreement
UART interface, 7-11 are dynamic restructuring managing chips, and 7-12 is typical hard control signal, including dynamic configuration enable signal
DYNA_PROG7-12-1, refresh enable signal EN_SCRUB7-12-2, self-refresh mode signal MODE_SCRUB7-12-3, refresh
Periodic signal INTERVEL [2:0] 7-12-4 and data source selection signal SEL_BIT7-12-5,7-13 are the switches in four channels
Pin CON_EN_0, CON_EN_1, CON_EN_2, CON_EN_3.
The following are default settings: hard control signal 7-12-1,7-12-2,7-12-3 are high level, and 7-12-5 is low level,
7-12-4 is zero, respectively represents that dynamic configuration is enabled, refresh enabled, readback refresh mode, data source PROM, the refresh cycle is
Optional minimum interval；CON_EN_0, CON_EN_1, CON_EN_2, CON_EN_3 are high level, represent four destination channels
It is in opening state.
After powering on, 7-11 executes initialization operation first since first aim channel, comprising: according to hard control signal
The default setting of decision is updated the corresponding internal register in the channel, and configuration bit stream is then read from 7-5 and is matched automatically
7-1 is set, device ID identification is realized by the IDCODE register of readback 7-1 and configuration bit stream again after configuration successful and is generated
GoldenCRC will execute the above operation to next destination channel after work state information updates at this time, until four targets are logical
All initialization is completed in road.Progress task then is recycled to each destination channel to share out the work, and specifically, selects one
Destination channel is updated internal register according to the pin level state of 7-12 or the external control instruction from 7-10,
And the scheduling of work at present task is carried out according to the operating mode of internal register setting, execute corresponding dynamic configuration, timing
The task of refreshing, readback refreshing, timing readback, dynamic restructuring or poll verification operation, current channel executes after the completion more
New corresponding work state information simultaneously selects next channel to carry out the above operation.
By taking first channel as an example, task scheduling and the concrete mode executed are as follows:
Internal register value is read, if receiving dynamic configuration instruction, stops the refreshing being carrying out or read back operation, root
Configuration bit stream is read from the subregion 0 of data source 7-5 or 7-9 according to current setting selection, and 7-1 is matched using from simultaneously mode
It sets, wherein the data read from 7-9 need that 7-1 is first written again through BCH decoding；
If receiving dynamic restructuring instruction, stop the refresh operation being carrying out, erasing behaviour first is executed to the subregion of 7-9 0
Make, then the dynamic restructuring bit stream from ground received from 7-10 is written to the subregion 0 of 7-9；Match executing dynamic next time
7-1 is written in the dynamic restructuring bit stream that can update this when setting, and realizes in-orbit function switch；
If receiving data polling instruction, stop the refresh operation being carrying out, the configuration to saving in the subregion 0 of 7-9
Bit stream is verified, and check results are saved to respective inner register；
If operating mode is periodic refreshing, do not arrived in timing and in the case where without other live task instructions to current channel
Do-nothing operation is executed, channel selecting state is jumped to, operating mode acquisition and task-scheduling operation are carried out to next destination channel；
Come then in timing, SEFI detection is carried out to FPGA first, if detection is selected according to current setting from data source without SEFI failure
Read configuration bit stream in the subregion 0 of 7-5 or 7-9, it is preprocessed obtain after valid data frame using from and mode 7-1 is brushed
Newly, this restarts timing after the completion of refreshing；If it is detected that SEFI failure, according to current setting, when dynamic configuration enables
Dynamic configuration is executed to FPGA, restarts timing after the completion, directly stops this operation when dynamic configuration is forbidden, open again
Beginning timing；
If operating mode is that readback refreshes, do not arrived in timing and in the case where without other live task instructions to current channel
Do-nothing operation is executed, channel selecting state is jumped to, operating mode acquisition and task-scheduling operation are carried out to next destination channel；
Come then in timing, SEFI detection carried out to FPGA first, if detection without SEFI failure, using from and mode readback 7-1 position
CurrentCRC is flowed and calculated, it is compared with the GoldenCRC saved in initialization operation, is not necessarily to when two values are identical
Refresh, when two value differences, configuration bit stream is read from the subregion 0 of data source 7-5 or 7-9 according to current setting selection, through pre-
Processing obtain after valid data frame using from and mode 7-1 is refreshed, this restarts timing after the completion of refreshing；If inspection
SEFI failure is measured, according to current setting, dynamic configuration is executed to FPGA when dynamic configuration enables, restarts to count after the completion
When, directly stop this operation when dynamic configuration is forbidden, restarts timing；
If operating mode is timing readback, do not arrived in timing and in the case where without other live task instructions to current channel
Do-nothing operation is executed, channel selecting state is jumped to, operating mode acquisition and task-scheduling operation are carried out to next destination channel；
Come then in timing, SEFI detection carried out to FPGA first, if detection without SEFI failure, using from and mode readback 7-1 position
Flow and calculate CurrentCRC, by preservation restart timing into respective inner register, after the completion of this readback；If inspection
SEFI failure is measured, according to current setting, dynamic configuration is executed to FPGA when dynamic configuration enables, restarts to count after the completion
When, directly stop this operation when dynamic configuration is forbidden, restarts timing.
The content that description in the present invention is not described in detail belongs to the well-known technique of those skilled in the art.
Claims (10)
1. a kind of in-orbit dynamic restructuring management system of SRAM type FPGA, it is characterised in that: including SRAM type FPGA, dynamic restructuring pipe
Manage chip, configuration bit stream storage chip, dynamic restructuring bit stream storage chip, serial port chip；
The configuration bit stream of overall format is stored on the configuration bit stream storage chip；It is deposited on the dynamic restructuring bit stream storage chip
Store up dynamic restructuring bit stream；The serial port chip is then sent to institute for receiving external control instruction and external dynamic reconstruct bit stream
State dynamic restructuring managing chip；
The dynamic restructuring managing chip is used to read the configuration bit stream stored in the configuration bit stream memory to SRAM type
FPGA is configured and is refreshed；The dynamic restructuring managing chip is stored for reading in the dynamic restructuring bit stream storage chip
Configuration bit stream SRAM type FPGA is configured, refreshed and is reconstructed；The dynamic restructuring managing chip is to the SRAM type
The bit stream of FPGA carries out CRC check, judges whether to execute refreshing according to CRC check result；The dynamic restructuring managing chip will
Work state information is sent to the serial port chip；The dynamic restructuring managing chip is written after receiving external dynamic reconstruct bit stream
In the dynamic restructuring bit stream storage chip.
2. the in-orbit dynamic restructuring management system of a kind of SRAM type FPGA according to claim 1, it is characterised in that: described dynamic
State reconfiguration management chip can be polled verification to the Bose-Chaudhuri-Hocquenghem Code bit stream saved in the dynamic restructuring bit stream storage chip,
Sevtor address when verifying error where misregistration.
3. the in-orbit dynamic restructuring management system of a kind of SRAM type FPGA according to claim 1, it is characterised in that: described dynamic
State reconfiguration management chip can read the device ID in the configuration register of the SRAM type FPGA, then recognition means model.
4. the in-orbit dynamic restructuring management system of a kind of SRAM type FPGA according to claim 1, it is characterised in that: described
The in-orbit dynamic restructuring management system of SRAM type FPGA, which is used, to be configured, refreshed and is returned to the SRAM type FPGA from simultaneously mode
It reads.
5. the in-orbit dynamic restructuring management system of a kind of SRAM type FPGA according to claim 1, it is characterised in that: described
The in-orbit dynamic restructuring management system of SRAM type FPGA can configure the SRAM type FPGA in most four channels, be refreshed,
Rail reconstruct.
6. the in-orbit dynamic restructuring management system of a kind of SRAM type FPGA according to claim 1, it is characterised in that: described
The in-orbit dynamic restructuring management system of SRAM type FPGA can to XQVR300, XQR2V3000, XQR4VSX55, XQR5VSX95T,
The SRAM type fpga chip of six kinds of models of XQR5VLX155T, XQR5VFX130T configured, refreshed, in-orbit reconstruct.
7. the in-orbit dynamic restructuring management system of a kind of SRAM type FPGA according to claim 1, it is characterised in that: described dynamic
State reconfiguration management chip includes that master control and scheduler module, configuration module, refresh module, readback module, UART module, poll verify
Module, in which:
The master control and scheduler module are for all device Working moulds in the in-orbit dynamic restructuring management system of the SRAM type FPGA
The control of formula and the scheduling of task；
The configuration module is used to read configuration from the configuration bit stream memory or the dynamic restructuring bit stream storage chip
Then the SRAM type FPGA is written in bit stream；
The refresh module is used to read configuration from the configuration bit stream memory or the dynamic restructuring bit stream storage chip
Then bit stream pre-processes configuration bit stream, be ultimately written the SRAM type FPGA；
The readback module for from the configured memory array of the SRAM type FPGA read configuration register state value and
Bit stream is configured, realizes the device recognition to the SRAM type FPGA and CRC check；
The UART module reconstructs bit stream for receiving external control instruction and external dynamic, and according to read states register instruction
Return to corresponding internal register value；
The poll correction verification module is for translating the Bose-Chaudhuri-Hocquenghem Code bit stream saved in the dynamic restructuring bit stream storage chip
Code, verification, when verifying error, the poll correction verification module compiles the BCH saved in the dynamic restructuring bit stream storage chip
Code bit stream is repaired or is recorded.
8. the in-orbit dynamic restructuring management system of a kind of SRAM type FPGA according to claim 7, it is characterised in that: work as verification
When error, if the Bose-Chaudhuri-Hocquenghem Code bit stream of verification error is less than or equal to 2bit, the poll correction verification module is to the error
Bose-Chaudhuri-Hocquenghem Code bit stream is repaired, if the Bose-Chaudhuri-Hocquenghem Code bit stream of verification error is more than or equal to 3bit, the poll correction verification module
The place sevtor address of the Bose-Chaudhuri-Hocquenghem Code bit stream of the error is recorded.
9. a kind of in-orbit dynamic reconfiguration method of SRAM type FPGA, it is characterised in that: use SRAM type FPGA described in claim 1
In-orbit dynamic restructuring management system, includes the following steps:
Step (1): dynamic restructuring managing chip determines destination channel according to the CON_EN pin status in four channels；
Step (2): dynamic restructuring managing chip carries out power on configuration to the SRAM type FPGA of one of destination channel；
Step (3): dynamic restructuring managing chip carries out device recognition by the device ID of readback destination channel；
Step (4): then dynamic restructuring managing chip is calculated by the Bose-Chaudhuri-Hocquenghem Code bit stream of the SRAM type FPGA of readback destination channel
GoldenCRC；
Step (5): repeating step (1)~step (4), completes initialization to the SRAM type FPGA of other destination channels；
Step (6): according to hard control signal and/or the control instruction from serial ports to the configuration bit stream for configuring bit stream storage chip
And/or the dynamic restructuring bit stream of dynamic restructuring bit stream storage chip is updated, then according to configuration bit stream storage chip and/or dynamic
The operating mode of state reconstruct bit stream storage chip is scheduled destination channel task；The execution when task is triggered
Dynamic configuration or periodic refreshing or readback refreshing or timing readback, dynamic restructuring or poll verification.
10. a kind of in-orbit dynamic reconfiguration method of SRAM type FPGA according to claim 9, it is characterised in that: the poll
Verification includes the following steps:
Step (11): BCH decoding is carried out to the current sector FLASH；
Step (12): if decoding discovery mistake, recompiling current sector, the progress error correction of data retrography, enter step (13),
If decoding is directly entered step (13) without discovery mistake；
Step (13): CRC check is carried out to current sector, if verification is correct, is directly entered step (14)；If verification error, note
It records the address of faulty sector and updates respective inner register, subsequently into step (14)；
Step (14): circulation executes step (11)~step (13) until whole for the sector of storage configuration bit stream in FLASH
Verification finishes.
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