CN113312305A - FPGA-based aerospace electronic system on-orbit reconstruction method and system - Google Patents
FPGA-based aerospace electronic system on-orbit reconstruction method and system Download PDFInfo
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Abstract
The invention discloses an on-orbit reconstruction method and an on-orbit reconstruction system of an aerospace electronic system based on an FPGA (field programmable gate array). The method plays a key role in repairing the on-orbit fault of an aerospace electronic system, relieving the influence of the Single Event Effect (SEE) of the aerospace space on aerospace electronic equipment such as a satellite and the like. The autonomous health management and on-orbit maintenance capability of the aerospace electronic system are fundamentally improved. And on-orbit autonomous configuration, self-test, autonomous repair and maintenance can be realized. Thereby greatly improving the system performance and reliability.
Description
Technical Field
The invention belongs to the field of on-orbit upgrade maintenance and control, and particularly relates to an on-orbit reconstruction method and system of an aerospace electronic system based on an FPGA.
Background
With the increasing complexity of the functions of the aerospace system, more and more functions are realized by the FPGA, which puts higher requirements on the on-orbit reconstruction, on-orbit maintenance, task upgrade and health management of the system. With the continuous deepening and upgrading of the in-orbit application of the aerospace system, a technology capable of realizing in-orbit systematization and comprehensive upgrading of software and reconstructing an FPGA is urgently needed to realize iterative upgrading of the application.
The functions of the traditional satellite, airship and other systems are highly customized, and the on-orbit maintenance is generally realized by means of the application software. Hardware functionality cannot be changed. This makes the electronic system and the whole star function solidified and single. The hardware design is highly customized, the universality cannot be realized, and the production cost of a single machine and the execution cost of a single task are very high.
Disclosure of Invention
The invention aims to overcome the defects and provides an on-orbit reconstruction method and an on-orbit reconstruction system of an aerospace electronic system based on an FPGA (field programmable gate array), which can flexibly define the functions and the performances of a satellite or an electronic component.
In order to achieve the aim, the on-orbit reconstruction method of the aerospace electronic system based on the FPGA comprises the following steps:
s1, compatible with CPU software, FPGA configuration stream file and operating system reconstruction command and configuration file protocol in the system;
s2, analyzing and judging the CPU software, the FPGA configuration stream file and the system reconstruction command according to a set protocol, and identifying the type of the upper annotation data stream and the upper annotation target;
if the type of the upper note data is CPU software or an operating system file, executing S3;
if the type of the upper note data is identified to be the FPGA configuration stream file, S4 is executed;
s3, extracting effective bit stream from CPU software or operation system file, writing the effective bit stream into corresponding FLASH memory area, and making reset or interrupt request to processor to execute newly configured program;
s4, extracting effective bit stream in FPGA configuration stream file, re-framing according to configuration refresh chip programming command format, then forwarding to refresh chip, generating upper note sequence by refresh chip to program corresponding FLASH, after programming, performing data read-back and data CRC check, if no error, issuing command, and reloading FPGA.
When the route calculation unit software is reconstructed, the following steps are carried out:
s401, erasing the corresponding FLASH whole chip, and returning to the telemetry frame;
s402; programming on a corresponding FLASH and returning a telemetering frame;
s403, detecting corresponding FLASH read-back bit streams;
s404, checking the CRC, and if the CRC is correct, executing S405; if not, then 407 is performed
S405, starting the FPGA to reload, and executing S406; if the production is interrupted, ending;
s406, if the overloading is successful, starting timing refreshing, and if the overloading is failed, returning a telemetering frame;
s407, returning the telemetry frame, uploading data, and reading back CRC check failure.
When the route switching unit FPGA is reconstructed, the following steps are carried out:
s411, closing the timing refreshing;
s412, periodically returning telemetry frames;
s413, judging whether the refreshing is successful, if so, executing S401; if not, S411 is executed.
In S401, after returning to the telemetry frame, judging whether the whole slice is successfully erased, if so, executing S402; if not, the corresponding FLASH is erased again in a whole piece.
In S402, after the telemetry frame is returned, whether the programming is successful is judged, and if so, S4021 is carried out; if not, programming on the corresponding FLASH again;
s4021, determines whether or not the programming is completed, if so, proceeds to S403, and if not, proceeds to S402.
An aerospace electronic system on-orbit reconstruction system based on an FPGA (field programmable gate array) comprises a main control unit, a main control communication and protocol analysis module based on an antifuse FPGA, a refreshing chip protocol conversion and control module, CPU (central processing unit) routing software and loading control module, a telemetering acquisition and framing module, a CPU software operation monitoring module, a communication module, an SRAM (static random access memory) type FPGA refreshing chip outside the FPGA and a FLASH memory;
the main control communication and protocol analysis module is used for receiving target FPGA starting, stopping, refreshing and programming commands from the main control unit, is compatible with the erasing, programming and readback verification commands of CPU software and FPGA configuration file FLASH and commands of FPGA overloading, software resetting and system remote information requiring, and sends internal instructions and upper injection data to the refreshing chip and the CPU route loading control module after analyzing the commands;
the refreshing chip protocol conversion and control module is used for completing protocol and logic control functions of communication protocol conversion, code rate conversion, communication priority arbitration and the like between the main control unit and the refreshing chip;
the telemetering acquisition and framing module is used for returning telemetering and timing telemetering according to a system command, and periodically returning current CPU routing software, an SRAM type FPGA and current working state and register configuration information of a refreshing chip to the main control unit;
the CPU software operation monitoring module is used for monitoring and acquiring the operation condition of the CPU software in real time, refreshing the working state and configuration condition of a chip, resetting the system, a CPU heartbeat signal, the loading state of an SRAM type FPGA, three-mode voting of an important register of a functional FPGA and the operation condition of a watchdog circuit;
the CPU routing software and loading control module are connected with a FLASH storage chip for storing the CPU software and the operating system, are used for carrying out erasing, programming and readback verification on NORFLASH of a storage program according to a main control command, are used as an interface for the CPU to access NOR FLASH, and when the CPU enters a bootstrap program, the operating system or an application program which is newly added is reloaded through the interface.
The refreshing chip is connected with a refreshing chip protocol conversion and control unit through a refreshing communication interface, and the refreshing chip protocol conversion and control unit is connected with a telemetering acquisition and framing unit and a main control communication protocol analysis unit.
The main control communication protocol analysis unit and the telemetering acquisition and framing unit are connected with a CPU routing software loading control unit, and the CPU routing software loading control unit is connected with a CPU and a software FLASH memory.
Compared with the prior art, the method is based on the FPGA technology, and can realize the software of an aerospace electronic system and the on-orbit reconstruction function of the FPGA. The method plays a key role in repairing the on-orbit fault of an aerospace electronic system, relieving the influence of the Single Event Effect (SEE) of the aerospace space on aerospace electronic equipment such as a satellite and the like. The autonomous health management and on-orbit maintenance capability of the aerospace electronic system are fundamentally improved. And on-orbit autonomous configuration, self-test, autonomous repair and maintenance can be realized. Thereby greatly improving the system performance and reliability.
The space navigation computer architecture capable of being reconstructed by the system improves the dimensionality of the computer system in a time level, is a technology which can be used for fault repair and on-track upgrade, and can be researched as a new Time Division Multiplexing (TDMA) computer architecture. And a method and a technical approach are provided for realizing software-defined satellite and aerospace artificial intelligence.
Drawings
FIG. 1 is a block diagram of the system of the present invention;
FIG. 2 is a flow chart of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Referring to fig. 1, the aerospace electronic system on-orbit reconstruction system based on the FPGA is characterized by comprising a master control communication protocol analysis module based on the antifuse FPGA, a chip refreshing protocol conversion and control module, a CPU routing software and loading control module, a telemetering acquisition and framing module, a CPU software operation monitoring module, a communication module and the like. And an SRAM type FPGA refreshing chip, a FLASH memory and the like outside the FPGA.
The main control communication and protocol analysis module is realized by FPGA, mainly interfaces with the main control unit, receives the following information from the main control unit: the target FPGA starts, stops, refreshes and programs commands, and is compatible with CPU software, commands of erasing, programming and readback verification of an FPGA configuration file FLASH, commands of FPGA overloading, software resetting, system request telemetering information and the like. And after the command is analyzed, sending an internal instruction and upper note data to other internal function modules such as a refresh chip, a CPU route loading control module and the like.
The protocol conversion and control module of the refresh chip is realized by FPGA, and is positioned between the main control unit and the refresh chip in the system, and the main functions are to complete the communication protocol conversion, code rate conversion, communication priority arbitration, and other protocol and logic control functions between the main control unit and the refresh chip.
The telemetry acquisition and framing module has the main functions of: the 'return telemetry according to system command' and 'timing return telemetry' are the main modes for the reconstruction control system to feed back the current working information to the main control unit. And periodically (every 12ms), returning current CPU routing software, an SRAM type FPGA, a current working state of a refreshing chip and register configuration information to the main control unit.
The system health monitoring module is used for real-time monitoring and acquisition: the CPU software running condition, the working state and the configuration condition of a refreshing chip, the system reset state, the CPU heartbeat signal, the loading state of the SRAM type FPGA, the triple modular voting (TMR Vote) of the important register of the functional FPGA, the running condition of a watchdog circuit and other key parameters which are related to the running safety of a target system. The real-time monitoring of the health state of the target system by the reconstruction control system is realized, and safe application software and a target FPGA configuration program are started and reloaded under the condition of system failure.
The CPU routing software loading control module is connected with a FLASH memory chip for storing CPU software and an operating system, and can perform operations such as erasing, programming, readback verification and the like on NORFLASH of a stored program according to a main control command. And simultaneously as an interface for the CPU to access the NOR FLASH. When the processor (CPU) enters the boot program, the newly injected operating system or application program will be reloaded through the interface.
Referring to fig. 2, an aerospace electronic system on-orbit reconstruction method based on an FPGA includes the following steps:
s1, compatible with CPU software, FPGA configuration stream file and operating system reconstruction command and configuration file protocol in the system;
s2, analyzing and judging the CPU software, the FPGA configuration stream file and the system reconstruction command according to a set protocol, and identifying the type of the upper annotation data stream and the upper annotation target;
if the type of the upper note data is CPU software or an operating system file, executing S3;
if the type of the upper note data is identified to be the FPGA configuration stream file, S4 is executed;
s3, extracting effective bit stream from CPU software or operation system file, writing the effective bit stream into corresponding FLASH memory area, and making reset or interrupt request to processor to execute newly configured program;
s4, extracting effective bit stream in FPGA configuration stream file, re-framing according to configuration refresh chip programming command format, then forwarding to refresh chip, generating upper note timing sequence by refresh chip, programming corresponding FLASH, performing data read-back and data CRC check after programming, if no error is checked, issuing command, and reloading FPGA.
When the route calculation unit software is reconstructed, the following steps are carried out:
s401, erasing the corresponding FLASH whole chip, and returning to the telemetry frame;
s402; programming on a corresponding FLASH and returning a telemetering frame;
s403, detecting corresponding FLASH read-back bit streams;
s404, checking the CRC, and if the CRC is correct, executing S405; if not, then 407 is performed
S405, starting the FPGA to reload, and executing S406; if the production is interrupted, ending;
s406, if the overloading is successful, starting timing refreshing, and if the overloading is failed, returning a telemetering frame;
s407, returning the telemetry frame, uploading data, and reading back CRC check failure.
When the route switching unit FPGA is reconstructed, the following steps are carried out:
s411, closing the timing refreshing;
s412, periodically returning telemetry frames;
s413, judging whether the refreshing is successful, if so, executing S401; if not, S411 is executed.
In S401, after returning to the telemetry frame, judging whether the whole slice is successfully erased, if so, executing S402; if not, the corresponding FLASH is erased again in a whole piece.
In S402, after the telemetry frame is returned, whether the programming is successful is judged, and if so, S4021 is carried out; if not, programming on the corresponding FLASH again;
s4021, determines whether or not the programming is completed, if so, proceeds to S403, and if not, proceeds to S402.
The invention can synchronously reconstruct software and FPGA, thereby flexibly defining the functions and performances of the satellite or the electronic component. The reconstructed FPGA chip is hardware with a specific function, the FPGA can mine a potential parallel relation in a task, parallel computation is realized by utilizing the resource advantage of the high-performance FPGA, and flexibly configurable FPGA resources are used for replacing on-track performance. The method has the advantages that the task is expanded in time and space, high flexibility and high performance are realized, in-orbit maintainability is realized, and the method is very suitable for application in aerospace projects. Compared with a hardware solidification system, the system has more flexible functions and more excellent performance.
The invention carries out operations such as erasing, programming, data readback, CRC check and the like on the FLASH memory storing the CPU software and the FPGA configuration file. And collecting information of modules such as a refreshing chip, software loading control, CPU state monitoring, FPGA key registers and the like to form a telemetering frame format, and automatically sending the telemetering frame format to a system main control unit.
The functions, the communication protocol, the verification, the programming, the erasing, the verification and other operations are all realized by one anti-fuse FPGA in an actual system. The method has the characteristics of high reliability, radiation resistance, independence, simple hardware structure and the like.
The method and the related technology provided by the invention can be widely applied to space navigation electronic systems such as satellites, airships, space stations and the like, and for on-orbit faults or hidden dangers, the method and the technology can eliminate the defects or hidden dangers in the original design and improve the reliability of the system; or provide remedy for system and hardware failure. Iterative upgrade of system application can also be realized by the method.
The method and the technology improve the dimensionality of the satellite-borne computer system in the time level, can be used as a new time division multiplexing computer system structure except for on-orbit fault repair and application upgrading, and provide technical support for realizing software defined satellites and aerospace artificial intelligence.
The invention is successfully applied to the project of a mobile internet constellation networking satellite inter-satellite router. The on-orbit maintenance of the on-satellite application software and the route calculation FPGA is realized.
Claims (8)
1. An aerospace electronic system on-orbit reconstruction method based on FPGA is characterized by comprising the following steps:
s1, compatible with CPU software, FPGA configuration stream file and operating system reconstruction command and configuration file protocol in the system;
s2, analyzing and judging the CPU software, the FPGA configuration stream file and the system reconstruction command according to a set protocol, and identifying the type of the upper annotation data stream and the upper annotation target;
if the type of the upper note data is CPU software or an operating system file, executing S3;
if the type of the upper note data is identified to be the FPGA configuration stream file, S4 is executed;
s3, extracting effective bit stream from CPU software or operation system file, writing the effective bit stream into corresponding FLASH memory area, and making reset or interrupt request to processor to execute newly configured program;
s4, extracting effective bit stream in FPGA configuration stream file, re-framing according to configuration refresh chip programming command format, then forwarding to refresh chip, generating upper note timing sequence by refresh chip, programming corresponding FLASH, performing data read-back and data CRC check after programming, if no error is checked, issuing command, and reloading FPGA.
2. The on-orbit reconstruction method for the aerospace electronic system based on the FPGA as recited in claim 1, wherein when the software is reconstructed, the following steps are performed:
s401, erasing the corresponding FLASH whole chip, and returning to the telemetry frame;
s402; programming on a corresponding FLASH and returning a telemetering frame;
s403, detecting corresponding FLASH read-back bit streams;
s404, checking the CRC, and if the CRC is correct, executing S405; if not, then 407 is performed
S405, starting the FPGA to reload, and executing S406; if the production is interrupted, ending;
s406, if the overloading is successful, starting timing refreshing, and if the overloading is failed, returning a telemetering frame;
s407, returning the telemetry frame, uploading data, and reading back CRC check failure.
3. The on-orbit reconstruction method for the aerospace electronic system based on the FPGA as recited in claim 2, wherein when the FPGA is reconstructed by the routing switching unit, the following steps are performed:
s411, closing the timing refreshing;
s412, periodically returning telemetry frames;
s413, judging whether the refreshing is successful, if so, executing S401; if not, S411 is executed.
4. The on-track reconfiguration method of an aerospace electronic system based on FPGA of claim 2, wherein in S401, after returning the telemetry frame, it is determined whether the whole piece is successfully erased, if yes, S402 is executed; if not, the corresponding FLASH is erased again in a whole piece.
5. The method for reconstructing the on-orbit of the aerospace electronic system based on the FPGA as recited in claim 2, wherein in S402, after returning the telemetry frame, whether the programming is successful is judged, if so, S4021 is performed; if not, programming on the corresponding FLASH again;
s4021, determines whether or not the programming is completed, if so, proceeds to S403, and if not, proceeds to S402.
6. An aerospace electronic system on-orbit reconstruction system based on an FPGA (field programmable gate array) is characterized by comprising a main control unit, a main control communication and protocol analysis module based on an antifuse FPGA, a refreshing chip protocol conversion and control module, CPU (central processing unit) routing software and loading control module, a telemetering acquisition and framing module, a CPU software operation monitoring module, a communication module, an SRAM (static random access memory) type FPGA refreshing chip outside the FPGA and a FLASH memory;
the main control communication and protocol analysis module is used for receiving target FPGA starting, stopping, refreshing and programming commands from the main control unit, is compatible with the erasing, programming and readback verification commands of CPU software and FPGA configuration file FLASH and commands of FPGA overloading, software resetting and system remote information requiring, and sends internal instructions and upper injection data to the refreshing chip and the CPU route loading control module after analyzing the commands;
the refreshing chip protocol conversion and control module is used for completing protocol and logic control functions of communication protocol conversion, code rate conversion, communication priority arbitration and the like between the main control unit and the refreshing chip;
the telemetering acquisition and framing module is used for returning telemetering and timing telemetering according to a system command, and periodically returning current CPU routing software, an SRAM type FPGA and current working state and register configuration information of a refreshing chip to the main control unit;
the CPU software operation monitoring module is used for monitoring and acquiring the operation condition of the CPU software in real time, refreshing the working state and configuration condition of a chip, resetting the system, a CPU heartbeat signal, the loading state of an SRAM type FPGA, three-mode voting of an important register of a functional FPGA and the operation condition of a watchdog circuit;
the CPU routing software and loading control module are connected with a FLASH storage chip for storing the CPU software and the operating system, are used for carrying out erasing, programming and readback verification on NORFLASH of a storage program according to a main control command, are used as an interface for the CPU to access NOR FLASH, and when the CPU enters a bootstrap program, the operating system or an application program which is newly added is reloaded through the interface.
7. The FPGA-based aerospace electronic system on-track reconfiguration system of claim 6, wherein the refresh chip is connected to the refresh chip protocol conversion and control unit through the refresh communication interface, and the refresh chip protocol conversion and control unit is connected to the telemetry acquisition and framing unit and the master communication protocol parsing unit.
8. The FPGA-based aerospace electronic system on-orbit reconstruction system of claim 6, wherein the master control communication protocol parsing unit and the telemetry acquisition and framing unit are connected with the CPU routing software loading control unit, and the CPU routing software loading control unit is connected with the CPU and the software FLASH memory.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114564422A (en) * | 2022-01-26 | 2022-05-31 | 中国人民解放军国防科技大学 | Dynamic synchronous refresh controller and dynamic synchronous refresh control method for multi-channel DRAM |
| CN114661531A (en) * | 2022-02-28 | 2022-06-24 | 成都市硅海武林科技有限公司 | Fine-grained self-repairing circuit and method for FPGA |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106843191A (en) * | 2016-12-18 | 2017-06-13 | 航天恒星科技有限公司 | The in-orbit maintaining methods of FPGA and device |
| CN109656870A (en) * | 2018-11-19 | 2019-04-19 | 北京时代民芯科技有限公司 | A kind of in-orbit dynamic restructuring management system of SRAM type FPGA and method |
| CN109783434A (en) * | 2018-10-25 | 2019-05-21 | 西安空间无线电技术研究所 | The highly reliable in-orbit reconfiguration system of spaceborne single machine multi-disc SRAM type FPGA of low-cost and method |
| CN109799515A (en) * | 2018-12-17 | 2019-05-24 | 上海航天电子有限公司 | Remote terminal and its in-orbit reconstructing method |
| CN110333881A (en) * | 2019-03-22 | 2019-10-15 | 中国电子科技集团公司第五十四研究所 | A kind of in-orbit reconstructing method of load class device software based on spaceborne FPGA processing |
| CN111611201A (en) * | 2020-06-24 | 2020-09-01 | 中国人民解放军国防科技大学 | Refresh self-adaptive continuous high-leanable-rail FPGA reconstruction system and method |
| CN111800345A (en) * | 2020-06-30 | 2020-10-20 | 西安微电子技术研究所 | High-reliability constellation networking space router circuit |
-
2021
- 2021-06-15 CN CN202110662031.3A patent/CN113312305B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106843191A (en) * | 2016-12-18 | 2017-06-13 | 航天恒星科技有限公司 | The in-orbit maintaining methods of FPGA and device |
| CN109783434A (en) * | 2018-10-25 | 2019-05-21 | 西安空间无线电技术研究所 | The highly reliable in-orbit reconfiguration system of spaceborne single machine multi-disc SRAM type FPGA of low-cost and method |
| CN109656870A (en) * | 2018-11-19 | 2019-04-19 | 北京时代民芯科技有限公司 | A kind of in-orbit dynamic restructuring management system of SRAM type FPGA and method |
| CN109799515A (en) * | 2018-12-17 | 2019-05-24 | 上海航天电子有限公司 | Remote terminal and its in-orbit reconstructing method |
| CN110333881A (en) * | 2019-03-22 | 2019-10-15 | 中国电子科技集团公司第五十四研究所 | A kind of in-orbit reconstructing method of load class device software based on spaceborne FPGA processing |
| CN111611201A (en) * | 2020-06-24 | 2020-09-01 | 中国人民解放军国防科技大学 | Refresh self-adaptive continuous high-leanable-rail FPGA reconstruction system and method |
| CN111800345A (en) * | 2020-06-30 | 2020-10-20 | 西安微电子技术研究所 | High-reliability constellation networking space router circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114564422A (en) * | 2022-01-26 | 2022-05-31 | 中国人民解放军国防科技大学 | Dynamic synchronous refresh controller and dynamic synchronous refresh control method for multi-channel DRAM |
| CN114564422B (en) * | 2022-01-26 | 2023-11-21 | 中国人民解放军国防科技大学 | Dynamic synchronous refresh controller and dynamic synchronous refresh control method for multi-channel DRAM |
| CN114661531A (en) * | 2022-02-28 | 2022-06-24 | 成都市硅海武林科技有限公司 | Fine-grained self-repairing circuit and method for FPGA |
| CN114661531B (en) * | 2022-02-28 | 2023-08-29 | 成都市硅海武林科技有限公司 | Fine-granularity self-repairing circuit and method for FPGA |
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|---|---|
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