CN110555237B - FPGA on-orbit dynamic reconfigurable method - Google Patents
FPGA on-orbit dynamic reconfigurable method Download PDFInfo
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Abstract
The invention discloses an FPGA on-orbit dynamic reconfigurable method. And the reliability of the configuration of the FPGA for processing the satellite-borne signal is improved through hardware triple-modular redundancy and software triple-modular comparison. And the ground transmits erasing, writing and reading instructions to the satellite configuration FPGA to realize the operations of erasing, writing and reading the satellite configuration data storage FLASH chip, thereby realizing the dynamic reconstruction of the satellite signal processing FPGA. The dynamic reconfiguration of the satellite-borne signal processing FPGA can realize on-orbit update or upgrade of the effective load function, reduce repeated development of hardware and save manpower, material resources and financial resources.
Description
Technical Field
The invention relates to an FPGA on-orbit dynamic reconfigurable method, and belongs to the field of design of effective loads of space aircrafts.
Background
The configuration file of the traditional satellite-borne signal processing FPGA is stored in an anti-fuse PROM, and the configuration file has the characteristic of one-time programming, namely the function of the satellite-borne equipment cannot be updated after the satellite-borne equipment runs on the track, and the function of the signal processing FPGA cannot be recovered when the PROM fails. With the increase of the number of on-orbit running spacecrafts, the space environment is increasingly complex, and higher requirements are put on the reliability of the on-board equipment. Based on the above considerations, the requirement for on-orbit dynamic reconfiguration of FPGAs is urgent and has important national strategic significance.
In order to save hardware costs, it is desirable to implement satellite in-orbit functionality maintenance, extension or updating through software updates. The existing functions are perfected or the performance is improved and the faults are repaired by upgrading the software. Satellite payloads work in complex and changeable space environments with severe environments, and satellite-borne electronic equipment is easily influenced by space environments such as single-event upset, single-event function interruption and the like to cause functional failure. The on-orbit dynamic reconfigurable technology can realize the recovery or update of the functions of the satellite-borne electronic equipment by reconfiguring the signal processing FPGA, and improves the reliability of the satellite-borne electronic equipment. There is no currently on-orbit dynamic reconfigurable application of FPGAs.
Disclosure of Invention
The technical solution of the invention is as follows: overcomes the defects of the prior art and provides an FPGA on-orbit dynamic reconfigurable method.
The technical scheme of the invention is as follows:
an FPGA on-orbit dynamic reconfigurable method comprises the following steps:
(1) The ground transmits a power-on instruction to the satellite-borne equipment, wherein the satellite-borne equipment comprises a signal processing FPGA, a configuration FPGA and three parallel FLASH chips;
(2) During function switching, the ground transmits a configuration instruction to the configuration FPGA, the configuration instruction indicates what number of configuration files to configure the static storage area, and the step (8) is performed; when the function is updated, the ground transmits an erasing instruction to the configuration FPGA to indicate the number of the erasing dynamic storage areas, and the step (3) is entered;
(3) After the erasure is completed, the ground transmits a writing instruction to the configuration FPGA;
(4) After the configuration FPGA receives the writing instruction, returning a writing instruction to the ground to finish handshake;
(5) After receiving the handshake information, the ground sends a configuration file to the configuration FPGA;
(6) After the writing of the configuration file is completed, the configuration FPGA returns a writing completion message to the ground;
(7) After receiving the writing completion message, the ground sends a reading instruction to the configuration FPGA;
(8) After receiving the reading instruction, the configuration FPGA starts to configure the signal processing FPGA according to the configuration file;
(9) After configuration is completed, judging whether the signal processing FPGA works normally, and if so, starting a timing monitoring and SEFI detection flow; if the work is abnormal, the step (10) is carried out;
(10) Judging whether the reconfiguration times reach a threshold value, and if so, judging that the satellite-borne equipment works abnormally; if the threshold is not reached, reconfiguration is performed.
Each parallel FLASH chip can store a plurality of configuration files, and the three parallel FLASH chips realize the function of hardware triple-modular redundancy.
Each FLASH chip storage area is divided into two parts, wherein one part stores a configuration file before satellite transmission, which is called a static storage area, and the other part annotates the configuration file on the ground after satellite transmission, which is called a dynamic storage area; both the static storage area and the dynamic storage area may store several configuration files.
In the step (5), after the ground transmits the configuration file to the configuration FPGA, the configuration FPGA writes the configuration file into three parallel FLASH chips.
The configuration FPGA comprises a workflow control module, a FLASH control module, a signal processing FPGA configuration module and a reset module;
and a reset module: generating reset signals required by each module of the configuration FPGA, and ensuring that signals and variables defined by the configuration FPGA during power-up operation have fixed initial values;
the workflow control module: according to the received remote control instruction, an erasing, writing or reading instruction and a corresponding starting address are sent to the FLASH control module; the workflow control module monitors DONE signals of the signal processing FPGA at regular time, and if abnormal, the signal processing FPGA is reconfigured; the workflow control module reads back a state signal register of the signal processing FPGA at regular time, and reconfigures the signal processing FPGA if the verification error reaches 3 times continuously;
FLASH control module: controlling the erasing, writing or reading operation of the parallel FLASH chips, and outputting the read configuration data to a signal processing FPGA configuration module;
a signal processing FPGA configuration module: and configuring the signal processing FPGA.
In the step (8), when the FPGA is configured to configure the signal processing FPGA, the FPGA is configured to read data in three FLASH at the same time, three-mode comparison is performed, and if the three FLASH data are consistent, the data in the first FLASH are selected to be output to the signal processing FPGA; if the two pieces of FLASH data are consistent, outputting the data of any one of the two pieces of FLASH to a signal processing FPGA; if all the three FLASH data are inconsistent, selecting the data in the first FLASH and outputting the data to the signal processing FPGA.
The timing monitoring flow is as follows:
(d1) Step (d 2) is carried out when the timing detection signal processing FPGA works normally and works abnormally;
(d2) If the work is abnormal, judging whether the reconfiguration times reach a threshold value, and if the reconfiguration times do not reach the threshold value, reconfiguring the signal processing FPGA; and if the threshold value is reached, judging that the satellite-borne equipment works abnormally.
The SEFI detection flow is as follows:
(s 1) configuring the FPGA to read the values of a frame address register and a status register of the signal processing FPGA at regular time;
(s 2) configuring the FPGA to compare the read-back value with the check value;
(s 3) if the read-back value is inconsistent with the check value, judging whether the continuous inconsistent times reach a threshold value, if so, judging that the single-particle function is interrupted, and configuring the FPGA to reconfigure the signal processing FPGA; if the threshold is not reached, the process returns to the step (s 1) and the detection is continued.
The SEFI phenomenon of the signal processing FPGA is represented by a configuration control register and a part of configuration state signals in the signal processing FPGA, and the SEFI can be detected by detecting the configuration control register and the configuration state signals.
Compared with the prior art, the invention has the following beneficial effects:
(1) The invention realizes the on-orbit switching and on-orbit function updating of satellite functions, so that one hardware platform can realize multiple functions, the repeated development of hardware is avoided, the manpower, material resources and financial resources are saved, in addition, when the satellite-borne electronic equipment is subjected to space environment irradiation or the influence of single event upset and fails to work normally, the ground can send a reconfiguration instruction to the configuration FPGA, the function of signal processing FPGA is recovered, and the service life of the satellite-borne electronic equipment is prolonged.
(2) When the signal processing FPGA is configured, the data in the three FLASH are read by the configuration FPGA at the same time, and are output to the signal processing FPGA after three-mode comparison, so that the configuration success rate is improved.
Drawings
FIG. 1 is a flow chart of an on-orbit dynamic reconfigurable method of an FPGA;
FIG. 2 is a timing monitoring flow;
FIG. 3 is a SEFI detection flow;
FIG. 4 is a block diagram of an on-orbit dynamically reconfigurable hardware design for an FPGA;
fig. 5 is a block diagram of the functional modules of the configuration FPGA software.
Detailed Description
The on-orbit dynamic reconfigurable hardware design block diagram of the FPGA is shown in figure 4. The on-board equipment comprises a configuration FPGA, a signal processing FPGA and three parallel FLASH chips. The configuration files are stored in the parallel FLASH chips, each parallel FLASH chip can store a plurality of configuration files, and the three parallel FLASH chips realize the function of hardware triple-modular redundancy. The FLASH chip storage area is divided into two parts, one part stores configuration files before satellite transmission, which are called static storage areas, and the other part annotates configuration files by the ground after satellite transmission, which are called dynamic storage areas. Both the static storage area and the dynamic storage area may store several configuration files. The reconfigurable instruction sent by the ground is received by the configuration FPGA (anti-fuse FPGA) to execute the corresponding function. There are two types of reconfigurable instructions: (1) And indicating the serial number of the configuration file, reading the corresponding configuration file from the FLASH chip by the anti-fuse FPGA, and configuring the configuration file to the signal processing FPGA. (2) Firstly, an erasing instruction is sent, a corresponding dynamic storage area is erased, secondly, a writing instruction is sent, a configuration file is uploaded, finally, a reading instruction is sent, and the configuration file uploaded on the ground is configured to a signal processing FPGA. And configuring the working state of the FPGA for timing monitoring signal processing, and if the working state is abnormal, reconfiguring.
The FPGA is configured to serve as a control unit for protecting the single event effect, the reliability requirement is high, and the reliability requirement can be met by selecting an FPGA device insensitive to the single event effect. The SEFI (Single Event Function Interrupt, single event interrupt) phenomenon of the signal processing FPGA can be represented by its internal configuration control registers and a portion of the configuration status signals. The detection of SEFI can be achieved by detecting the configuration control register and the configuration status signal. When the SEFI is detected, the signal processing FPGA needs to be subjected to global reconfiguration for repair.
The configuration FPGA adopts a structural program design method, program modules are divided according to functions, and when the requirements change, the corresponding program modules can be changed. The software functional module block diagram is shown in fig. 5, and mainly comprises a workflow control module, a FLASH control module, a signal processing FPGA configuration module and a reset module. The functions of each module are as follows:
(1) Reset module
And generating reset signals required by all modules, and ensuring fixed initial values of signals and variables defined by the configuration FPGA during power-up operation. The input signals of the reset module comprise: (1) a clock signal, (2) a watchdog reset signal. The output signal includes: (1) reset signals to each module, (2) a watchdog signal.
(2) Workflow control module
And the workflow control module sends an erasing, writing or reading instruction and a corresponding starting address to the FLASH control module according to the received remote control instruction. The workflow control module monitors the DONE signal of the signal processing FPGA at regular time, and if the DONE signal is abnormal, the signal processing FPGA is reconfigured. The workflow control module reads back the state signal register of the signal processing FPGA at regular time, and reconfigures the signal processing FPGA if the verification error continuously reaches 3 times. The input signals of the workflow control module include: (1) a clock signal, (2) a remote control command signal, (3) a signal processing FPGA operation abnormality indication signal (DONE signal), (4) a signal processing FPGA initialization completion signal (init_b signal). And (3) outputting a signal: (1) an erase, write or read command to the FLASH control module, (2) an erase, write or read start address, (3) telemetry information (whether the signal processing FPGA is configured successfully or not).
(3) FLASH control module
The FLASH control module controls the erasing, writing or reading operation of the parallel FLASH chip and outputs the read configuration data to the signal processing FPGA configuration module. The input signal includes: (1) a clock, (2) an erase, write or read instruction output by the workflow control module, (3) a start address of an erase, write or read operation, and (4) read configuration data. The output signal includes: (1) a chip select signal (CE) of the parallel FLASH chip, (2) a write enable signal (WE) of the parallel FLASH chip, (3) a read enable signal (OE) of the parallel FLASH chip, (4) an address signal of an erase, write or read operation, (5) configuration data (ground-on-the-air) of the write operation (6) is output to configuration data of the signal processing FPGA configuration module.
(4) Signal processing FPGA configuration module
The signal processing FPGA configuration module mainly completes the configuration function of the signal processing FPGA. The input signal includes: (1) the clock, (2) whether the signal processing FPGA works abnormal signals (DONE signals), (3) whether the signal processing FPGA is initialized to finish signals (INIT_B signals), (4) configuration data information output by the FLASH control module, and (5) a configuration control register returned by the signal processing FPGA and a configuration state signal. The output signal includes: (1) a configuration clock signal (CCLK signal) output to the signal processing FPGA, (2) a PROG pin signal (PROG_B signal) of the pull-down signal processing FPGA, (3) a read-write enable signal (RDWR_B signal) output to the signal processing FPGA, (4) a chip select signal (CS_B signal) output to the signal processing FPGA, and (5) configuration data information output to the signal processing FPGA.
On the basis of the above, as shown in fig. 1, the method for dynamically reconstructing the FPGA on-orbit provided by the present invention comprises the following steps:
(1) The ground transmits a power-up instruction to the satellite-borne equipment;
(2) During function switching, the ground transmits a configuration instruction to the configuration FPGA, the configuration instruction indicates what number of configuration files to configure the static storage area, and the step (8) is performed; when the function is updated, the ground transmits an erasing instruction to the configuration FPGA to indicate the number of the erasing dynamic storage areas, and the step (3) is entered;
(3) After the erasure is completed, the ground transmits a writing instruction to the configuration FPGA;
(4) After the configuration FPGA receives the writing instruction, returning a writing instruction to the ground to finish handshake;
(5) After receiving the handshake information, the ground sends a configuration file to the configuration FPGA;
(6) After the writing of the configuration file is completed, the configuration FPGA returns a writing completion message to the ground;
(7) After receiving the writing completion message, the ground sends a reading instruction to the configuration FPGA;
(8) After receiving the reading instruction, the configuration FPGA starts to configure the signal processing FPGA according to the configuration file;
(9) After configuration is completed, judging whether the signal processing FPGA works normally, and if so, starting a timing monitoring and SEFI detection flow; if the work is abnormal, the step (10) is carried out;
(10) Judging whether the reconfiguration times reach a threshold value, and if so, judging that the satellite-borne equipment works abnormally; if the threshold is not reached, the process goes to the step (8) to reconfigure.
The timing monitoring flow is shown in fig. 2.
(1) And detecting whether the signal processing FPGA works normally or not at regular time.
(2) If the work is abnormal, judging whether the reconfiguration times reach a threshold value.
(3) And if the threshold value is not reached, reconfiguring the signal processing FPGA.
(4) And if the threshold value is reached, judging that the satellite-borne equipment works abnormally.
The SEFI detection flow is shown in fig. 3.
(1) The FPGA is configured to read the values of a FAR (Frame Address) register and a Status (Status) register of the signal processing FPGA at regular time.
(2) The configuration FPGA compares the read-back value with the check value.
(3) If the read-back value is inconsistent with the check value, judging whether the continuous inconsistent times reach the threshold value or not.
(4) If the threshold is reached, judging that the single-particle function is interrupted, configuring the FPGA to reconfigure the signal processing FPGA.
The on-orbit dynamic reconfigurable method of the FPGA can realize the following functions: (1) Realizing satellite on-orbit function switching through ground on-injection instructions; (2) The on-orbit function updating of the satellite is realized through the ground on-stream instruction and the configuration data; (3) Detecting a satellite-borne signal processing FPGA at regular time, and if the work is abnormal, reconfiguring the signal processing FPGA; (4) And (3) regularly reading back the values of the FAR register and the STAT register, comparing the values with the check value, judging that the single-event function is interrupted if the continuous inconsistent times reach the threshold value, and configuring the FPGA to reconfigure the signal processing FPGA.
The invention provides an FPGA on-orbit dynamic reconfiguration method, which realizes on-orbit switching and on-orbit reconfiguration of satellite functions, so that one hardware platform can realize multiple functions, repeated development of hardware is avoided, manpower, material resources and financial resources are saved, the research and development period is shortened, and in addition, when the satellite-borne electronic equipment is subjected to space environment irradiation or single event upset and fails to work normally, the ground can send reconfiguration instructions to the configuration FPGA, the function of signal processing FPGA is recovered, the service life of the satellite-borne electronic equipment is prolonged, and the reliability of the satellite-borne equipment is improved. When the signal processing FPGA is configured, the data in the three FLASH are read by the configuration FPGA at the same time, and are output to the signal processing FPGA after three-mode comparison, so that the configuration success rate is improved.
What is not described in detail in the present specification belongs to the known technology of those skilled in the art.
Claims (7)
1. The FPGA on-orbit dynamic reconfigurable method is characterized by comprising the following steps of:
(1) The ground transmits a power-on instruction to the satellite-borne equipment, wherein the satellite-borne equipment comprises a signal processing FPGA, a configuration FPGA and three parallel FLASH chips; each FLASH chip storage area is divided into two parts, wherein one part stores a configuration file before satellite transmission, which is called a static storage area, and the other part annotates the configuration file on the ground after satellite transmission, which is called a dynamic storage area; the static storage area and the dynamic storage area can store a plurality of configuration files;
(2) During function switching, the ground transmits a configuration instruction to the configuration FPGA, the configuration instruction indicates what number of configuration files to configure the static storage area, and the step (8) is performed; when the function is updated, the ground transmits an erasing instruction to the configuration FPGA to indicate the number of the erasing dynamic storage areas, and the step (3) is entered;
(3) After the erasure is completed, the ground transmits a writing instruction to the configuration FPGA;
(4) After the configuration FPGA receives the writing instruction, returning a writing instruction to the ground to finish handshake;
(5) After receiving the handshake information, the ground sends a configuration file to the configuration FPGA;
(6) After the writing of the configuration file is completed, the configuration FPGA returns a writing completion message to the ground;
(7) After receiving the writing completion message, the ground sends a reading instruction to the configuration FPGA;
(8) After receiving the reading instruction, the configuration FPGA starts to configure the signal processing FPGA according to the configuration file;
(9) After configuration is completed, judging whether the signal processing FPGA works normally, and if so, starting a timing monitoring and SEFI detection flow; if the work is abnormal, the step (10) is carried out;
(10) Judging whether the reconfiguration times reach a threshold value, and if so, judging that the satellite-borne equipment works abnormally; if the threshold value is not reached, reconfiguration is carried out;
the configuration FPGA comprises a workflow control module, a FLASH control module, a signal processing FPGA configuration module and a reset module;
and a reset module: generating reset signals required by each module of the configuration FPGA, and ensuring that signals and variables defined by the configuration FPGA during power-up operation have fixed initial values; the input signals of the reset module comprise: (1) a clock signal, (2) a watchdog reset signal; the output signal includes: (1) reset signals to each module, (2) feeding dog signals;
the workflow control module: according to the received remote control instruction, an erasing, writing or reading instruction and a corresponding starting address are sent to the FLASH control module; the workflow control module monitors DONE signals of the signal processing FPGA at regular time, and if abnormal, the signal processing FPGA is reconfigured; the workflow control module reads back a state signal register of the signal processing FPGA at regular time, and reconfigures the signal processing FPGA if the verification error reaches 3 times continuously; the input signals of the workflow control module include: (1) the method comprises the steps of (1) a clock signal, (2) a remote control instruction signal, (3) a signal processing FPGA working abnormality indication signal, and (4) a signal processing FPGA initialization completion signal; and (3) outputting a signal: (1) an erasing, writing or reading instruction to the FLASH control module, (2) an erasing, writing or reading starting address, (3) telemetry information, and whether the signal processing FPGA is configured successfully;
FLASH control module: controlling the erasing, writing or reading operation of the parallel FLASH chips, and outputting the read configuration data to a signal processing FPGA configuration module; the input signal includes: (1) a clock, (2) an erase, write or read instruction output by the workflow control module, (3) a start address of an erase, write or read operation, (4) read configuration data; the output signal includes: (1) the method comprises the steps of (1) selecting a chip of a parallel FLASH chip, (2) writing enabling signals of the parallel FLASH chip, (3) reading enabling signals of the parallel FLASH chip, (4) address signals of erasing, writing or reading operation, and (5) outputting configuration data (6) of writing operation to configuration data of a signal processing FPGA configuration module;
a signal processing FPGA configuration module: configuring a signal processing FPGA; the input signal includes: (1) the clock, (2) whether the signal processing FPGA works abnormally or not, (3) whether the signal processing FPGA is initialized or not is finished, and (4) the configuration data information output by the FLASH control module, (5) the configuration control register returned by the signal processing FPGA and the configuration state signal; the output signal includes: (1) the method comprises the steps of (1) outputting a configuration clock signal to a signal processing FPGA, (2) pulling down a PROG pin signal of the signal processing FPGA, (3) outputting a read-write enabling signal to the signal processing FPGA, (4) outputting a chip selection signal to the signal processing FPGA, and (5) outputting configuration data information to the signal processing FPGA;
the configuration FPGA adopts a structural program design method, program modules are divided according to functions, and when the requirements change, the corresponding program modules are changed.
2. The method for dynamically reconstructing an FPGA on-orbit according to claim 1, wherein: each parallel FLASH chip can store a plurality of configuration files, and the three parallel FLASH chips realize the function of hardware triple-modular redundancy.
3. The method for dynamically reconstructing an FPGA on-orbit according to claim 1, wherein: in the step (5), after the ground transmits the configuration file to the configuration FPGA, the configuration FPGA writes the configuration file into three parallel FLASH chips.
4. An FPGA on-orbit dynamic reconfiguration method according to claim 3, wherein: in the step (8), when the FPGA is configured to configure the signal processing FPGA, the FPGA is configured to read data in three FLASH at the same time, three-mode comparison is performed, and if the three FLASH data are consistent, the data in the first FLASH are selected to be output to the signal processing FPGA; if the two pieces of FLASH data are consistent, outputting the data of any one of the two pieces of FLASH to a signal processing FPGA; if all the three FLASH data are inconsistent, selecting the data in the first FLASH and outputting the data to the signal processing FPGA.
5. The method for dynamically reconstructing an FPGA on-orbit according to claim 1, wherein: the timing monitoring flow is as follows:
(d1) Step (d 2) is carried out when the timing detection signal processing FPGA works normally and works abnormally;
(d2) If the work is abnormal, judging whether the reconfiguration times reach a threshold value, and if the reconfiguration times do not reach the threshold value, reconfiguring the signal processing FPGA; and if the threshold value is reached, judging that the satellite-borne equipment works abnormally.
6. The method for dynamically reconstructing an FPGA on-orbit according to claim 1, wherein: the SEFI detection flow is as follows:
(s 1) configuring the FPGA to read the values of a frame address register and a status register of the signal processing FPGA at regular time;
(s 2) configuring the FPGA to compare the read-back value with the check value;
(s 3) if the read-back value is inconsistent with the check value, judging whether the continuous inconsistent times reach a threshold value, if so, judging that the single-particle function is interrupted, and configuring the FPGA to reconfigure the signal processing FPGA; if the threshold is not reached, the process returns to the step (s 1) and the detection is continued.
7. The method for dynamically reconstructing an FPGA on-orbit according to claim 1, wherein: the SEFI phenomenon of the signal processing FPGA is represented by a configuration control register and a part of configuration state signals in the signal processing FPGA, and the SEFI can be detected by detecting the configuration control register and the configuration state signals.
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| CN111552500B (en) * | 2020-03-26 | 2023-06-06 | 北京遥测技术研究所 | Refreshing method suitable for spaceborne FPGA |
| CN111800345B (en) * | 2020-06-30 | 2022-04-26 | 西安微电子技术研究所 | High-reliability constellation networking space router circuit |
| CN112230970A (en) * | 2020-09-16 | 2021-01-15 | 北京遥测技术研究所 | FPGA refreshing method suitable for satellite-borne XILINX V2 |
| CN113447891A (en) * | 2021-04-28 | 2021-09-28 | 中国电子科技集团公司第十四研究所 | Satellite-borne radar exchange interface module |
| CN113433858A (en) * | 2021-06-24 | 2021-09-24 | 上海航天电子通讯设备研究所 | Automatic monitoring system for satellite-borne FPGA chip |
| CN115347938B (en) * | 2022-08-10 | 2024-05-31 | 山东航天电子技术研究所 | Satellite communication system based on RFSoC software radio architecture |
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