CN113312305B - On-orbit reconstruction method and system of aerospace electronic system based on FPGA - Google Patents
On-orbit reconstruction method and system of aerospace electronic system based on FPGA Download PDFInfo
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Abstract
The invention discloses an on-orbit reconstruction method and system of an aerospace electronic system based on an FPGA. The method plays a key role in repairing on-orbit faults of an aerospace electronic system, relieving the influence of a Single Event Effect (SEE) of a space on aerospace electronic equipment such as satellites and the like. The autonomous health management and on-orbit maintenance capability of the aerospace electronic system are fundamentally improved. The on-orbit autonomous configuration, the self-test, the autonomous repair and the maintenance can be realized. Thereby greatly improving the system performance and reliability.
Description
Technical Field
The invention belongs to the field of on-orbit upgrade maintenance and control, and particularly relates to an on-orbit reconstruction method and system of an aerospace electronic system based on an FPGA.
Background
With the increasing complexity of the functions of the aerospace system, more and more functions are realized by the FPGA, which puts higher demands on the on-orbit reconstruction, on-orbit maintenance, task upgrading and health management of the system. With the continuous deepening and upgrading of on-orbit application of an aerospace system, a technology capable of on-orbit systemizing and comprehensively upgrading software and reconstructing an FPGA is urgently needed to realize iterative upgrading of the application.
The functions of the conventional satellite, airship and other systems are highly customized, and in-orbit maintenance is generally realized by means of uploading application software. The hardware functions cannot be changed. This allows the electronic system and the whole star function to be cured and singular. The hardware design is highly customized, the universality cannot be realized, and the single-machine production cost and the single task execution cost are high.
Disclosure of Invention
The invention aims to overcome the defects and provide an on-orbit reconstruction method and system of an aerospace electronic system based on an FPGA, which can flexibly define functions and performances of satellites or electronic components.
In order to achieve the above purpose, an on-orbit reconstruction method of an aerospace electronic system based on an FPGA comprises the following steps:
s1, CPU software, FPGA configuration stream files, operating system reconfiguration commands and configuration file protocols in a compatible system;
s2, analyzing and judging CPU software, FPGA configuration stream files and system reconfiguration commands according to a set protocol, and identifying the type of the uploading data stream and the uploading target;
if the type of the uploading data is CPU software or an operating system file, executing S3;
if the type of the uploading data is identified as the FPGA configuration stream file, executing S4;
s3, extracting effective bit streams in CPU software or an operating system file, writing the effective bit streams into a corresponding FLASH storage area, and providing a reset or interrupt request for a processor to enable the processor to execute a newly configured program;
s4, extracting effective bit streams in the FPGA configuration stream file, re-framing according to a configuration refreshing chip programming command format, forwarding to the refreshing chip, generating an uploading time sequence by the refreshing chip to carry out programming operation on the corresponding FLASH, and carrying out data read-back and data CRC check after programming is finished, if the check is correct, sending out a command, and reloading the FPGA.
When the route calculation unit software is reconstructed, the following steps are performed:
s401, erasing the whole corresponding FLASH, and returning to a telemetry frame;
s402; programming is carried out on the corresponding FLASH, and a telemetry frame is returned;
s403, detecting a corresponding FLASH read-back bit stream;
s404, checking CRC, if the CRC is correct, executing S405; if not, then execution 407;
s405, starting FPGA reload, and executing S406; if the production is interrupted, ending;
s406, if the reloading is successful, starting timing refreshing, and if the reloading is failed, returning to the telemetry frame;
s407, returning the telemetry frame, uploading data, and returning the read CRC to fail.
When the route switching unit FPGA is reconstructed, the following steps are carried out:
s411, closing timing refresh;
s412, periodically returning a telemetry frame;
s413, judging whether the refreshing is successful, if so, executing S401; if not, S411 is performed.
In S401, after a telemetry frame is returned, judging whether the whole slice is successfully erased, if so, executing S402; if not, erasing the whole corresponding FLASH.
In S402, after the telemetry frame is returned, whether programming is successful is determined, if yes, S4021 is performed; if not, programming is carried out on the corresponding FLASH again;
s4021, judging whether programming is finished, if yes, executing S403, and if not, executing S402.
An on-orbit reconstruction system of an aerospace electronic system based on an FPGA comprises a main control unit, a main control communication and protocol analysis module based on an anti-fuse FPGA, a refreshing chip protocol conversion and control module, a CPU routing software and loading control module, a telemetering acquisition and framing module, a CPU software operation monitoring module, a communication module, an SRAM type FPGA refreshing chip outside the FPGA and a FLASH memory;
the main control communication and protocol analysis module is used for receiving starting, stopping, refreshing and programming commands of a target FPGA from the main control unit, and is compatible with erasing, programming and read-back checking commands of CPU software and an FPGA configuration file FLASH, and commands of FPGA reloading, software resetting and system requiring telemetry information, analyzing the commands and then sending internal instructions and uploading data to the refreshing chip and the CPU route loading control module;
the refreshing chip protocol conversion and control module is used for completing the communication protocol conversion, code rate conversion, communication priority arbitration, and other protocol and logic control functions between the main control unit and the refreshing chip;
the telemetry acquisition and framing module is used for returning telemetry and timing return telemetry according to system commands, and periodically returning current CPU routing software, SRAM type FPGA and refreshing current working state of the chip and register configuration information to the main control unit;
the CPU software operation monitoring module is used for monitoring and collecting the CPU software operation condition, refreshing the working state and the configuration condition of a chip, resetting the system, a CPU heartbeat signal, an SRAM type FPGA loading state, three-mode voting of a functional FPGA important register and the watchdog circuit operation condition in real time;
the CPU routing software and the loading control module are connected with a FLASH memory chip for storing the CPU software and the operating system, and are used for erasing, programming and read-back checking the NORFLASH of the stored program according to the main control command, and are used as an interface for accessing the NOR FLASH by the CPU, and when the CPU enters the guide program, the newly-loaded operating system or application program is reloaded through the interface.
The refreshing chip is connected with the refreshing chip protocol conversion and control unit through the refreshing communication interface, and the refreshing chip protocol conversion and control unit is connected with the telemetry acquisition and framing unit and the main control communication protocol analysis unit.
The main control communication protocol analysis unit and the telemetry acquisition and framing unit are connected with the CPU routing software loading control unit, and the CPU routing software loading control unit is connected with the CPU and the software FLASH memory.
Compared with the prior art, the method is based on the FPGA technology, and can realize the software of an aerospace electronic system and the on-rail reconstruction function of the FPGA. The method plays a key role in repairing on-orbit faults of an aerospace electronic system, relieving the influence of a Single Event Effect (SEE) of a space on aerospace electronic equipment such as satellites and the like. The autonomous health management and on-orbit maintenance capability of the aerospace electronic system are fundamentally improved. The on-orbit autonomous configuration, the self-test, the autonomous repair and the maintenance can be realized. Thereby greatly improving the system performance and reliability.
The system of the invention can reconstruct an aerospace computer architecture, improves the dimension of the computer system at the time level, is a technology which can be used for fault repair and on-orbit upgrading, and can be researched as a new Time Division Multiplexing (TDMA) computer architecture. Methods and technical approaches are also provided for implementation of software-defined satellites and aerospace artificial intelligence.
Drawings
FIG. 1 is a system block diagram of the present invention;
fig. 2 is a flow chart of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Referring to fig. 1, an on-orbit reconstruction system of an aerospace electronic system based on an FPGA is characterized by comprising a main control communication protocol analysis module based on an antifuse FPGA, a refresh chip protocol conversion and control module, a CPU routing software and loading control module, a telemetry acquisition and framing module, a CPU software operation monitoring module, a communication module and the like. And SRAM type FPGA refresh chips, FLASH memories and the like outside the FPGA.
The main control communication and protocol analysis module is realized by an FPGA and is mainly connected with the main control unit to receive signals from the main control unit: the target FPGA starts, stops, refreshes and programs commands, is compatible with CPU software, the commands of erasing, programming and read-back verification of an FPGA configuration file FLASH, and commands of FPGA reloading, software resetting, system demand telemetry information and the like. After analyzing the command, internal instructions and uploading data are sent to other internal functional modules such as a refreshing chip, a CPU route loading control module and the like.
The refreshing chip protocol conversion and control module is realized by an FPGA, and is positioned between the main control unit and the refreshing chip in the system, and the main functions are to complete the communication protocol conversion, code rate conversion, communication priority arbitration, and other protocol and logic control functions between the main control unit and the refreshing chip.
The telemetry acquisition and framing module has the main functions of: the "return telemetry according to the system command" and the "timing return telemetry" are the main modes of the reconstruction control system for feeding back the current working information to the main control unit. And (3) periodically (every 12 ms) returning the current CPU routing software, the SRAM type FPGA and the current working state and register configuration information of the refreshing chip to the main control unit.
The system health monitoring module is used for monitoring and collecting in real time: the method comprises the following steps of CPU software running condition, refreshing chip working state and configuration condition, system reset state, CPU heartbeat signal, SRAM type FPGA loading state, function FPGA important register triple-mode voting (TMR Vote), watchdog circuit running condition and other key parameters related to the running safety of a target system. The method realizes the real-time monitoring of the health state of the target system by the reconfiguration control system, and starts to reload the safe application software and the target FPGA configuration program under the condition of system failure.
The CPU routing software loading control module is connected with the FLASH memory chip interface for storing the CPU software and the operating system, and can erase, program, read back and check the NORFLASH of the stored program according to the main control command. And simultaneously, the interface of the NOR FLASH is accessed as a CPU. When the processor (CPU) enters the boot program, the newly loaded operating system or application will be reloaded through the interface.
Referring to fig. 2, an on-orbit reconstruction method of an aerospace electronic system based on an FPGA comprises the following steps:
s1, CPU software, FPGA configuration stream files, operating system reconfiguration commands and configuration file protocols in a compatible system;
s2, analyzing and judging CPU software, FPGA configuration stream files and system reconfiguration commands according to a set protocol, and identifying the type of the uploading data stream and the uploading target;
if the type of the uploading data is CPU software or an operating system file, executing S3;
if the type of the uploading data is identified as the FPGA configuration stream file, executing S4;
s3, extracting effective bit streams in CPU software or an operating system file, writing the effective bit streams into a corresponding FLASH storage area, and providing a reset or interrupt request for a processor to enable the processor to execute a newly configured program;
s4, extracting effective bit streams in the FPGA configuration stream file, re-framing according to a configuration refreshing chip programming command format, forwarding to the refreshing chip, generating an uploading time sequence by the refreshing chip, performing programming operation on corresponding FLASH, performing data read-back and data CRC check after programming, and if the check is correct, sending out a command, and reloading the FPGA.
When the route calculation unit software is reconstructed, the following steps are performed:
s401, erasing the whole corresponding FLASH, and returning to a telemetry frame;
s402; programming is carried out on the corresponding FLASH, and a telemetry frame is returned;
s403, detecting a corresponding FLASH read-back bit stream;
s404, checking CRC, if the CRC is correct, executing S405; if not, then execution 407;
s405, starting FPGA reload, and executing S406; if the production is interrupted, ending;
s406, if the reloading is successful, starting timing refreshing, and if the reloading is failed, returning to the telemetry frame;
s407, returning the telemetry frame, uploading data, and returning the read CRC to fail.
When the route switching unit FPGA is reconstructed, the following steps are carried out:
s411, closing timing refresh;
s412, periodically returning a telemetry frame;
s413, judging whether the refreshing is successful, if so, executing S401; if not, S411 is performed.
In S401, after a telemetry frame is returned, judging whether the whole slice is successfully erased, if so, executing S402; if not, erasing the whole corresponding FLASH.
In S402, after the telemetry frame is returned, whether programming is successful is determined, if yes, S4021 is performed; if not, programming is carried out on the corresponding FLASH again;
s4021, judging whether programming is finished, if yes, executing S403, and if not, executing S402.
The invention can reconstruct the software and the FPGA synchronously, thereby flexibly defining the functions and performances of the satellite or the electronic component. The reconstructed FPGA chip is hardware with a specific function, the FPGA can mine potential parallel relation in tasks, the resource advantage of the high-performance FPGA is utilized to realize parallel calculation, and the flexibly configured FPGA resource is used for exchanging on-orbit performance. The method has the advantages of expanding the task in time and space, having high flexibility and high performance, being maintainable in orbit and being very suitable for being applied to aerospace projects. This is more flexible and better performing than hardware cured systems.
The invention erases, programs, data read-back, CRC and other operations on the FLASH memory storing CPU software and FPGA configuration files. And information of modules such as a refreshing chip, software loading control, CPU state monitoring, FPGA key registers and the like is collected to form a telemetry frame format, and the telemetry frame format is automatically sent to a system main control unit.
The above functions and communication protocols, verification, programming, erasing, verification, etc. are all implemented in a real system by a piece of antifuse FPGA. The method has the characteristics of high reliability, radiation resistance, independence, simple hardware structure and the like.
The method and the related technology provided by the invention can be widely applied to aerospace electronic systems such as satellites, airships, space stations and the like, and for faults or hidden dangers occurring in orbit, the defects or hidden dangers in the original design can be eliminated by the method and the technology, and the reliability of the system is improved; or provide a remedy for system and hardware faults. The iterative upgrade of the system application can also be realized by the method.
The method and the technology improve the dimension of the spaceborne computer system in a time level, can be used as a new time division multiplexing computer system structure except for on-orbit fault repair and application upgrading, and provide technical support for the realization of software defined satellites and aerospace artificial intelligence.
The invention is successfully applied to the 'inter-satellite router' project of the constellation networking satellite of the mobile internet. On-orbit maintenance of on-board application software and routing computation FPGA is realized.
Claims (8)
1. An on-orbit reconstruction method of an aerospace electronic system based on an FPGA is characterized by comprising the following steps:
s1, CPU software, FPGA configuration stream files, operating system reconfiguration commands and configuration file protocols in a compatible system;
s2, analyzing and judging CPU software, FPGA configuration stream files and system reconfiguration commands according to a set protocol, and identifying the type of the uploading data stream and the uploading target;
if the type of the uploading data is CPU software or an operating system file, executing S3;
if the type of the uploading data is identified as the FPGA configuration stream file, executing S4;
s3, extracting effective bit streams in CPU software or an operating system file, writing the effective bit streams into a corresponding FLASH storage area, and providing a reset or interrupt request for a processor to enable the processor to execute a newly configured program;
s4, extracting effective bit streams in the FPGA configuration stream file, re-framing according to a configuration refreshing chip programming command format, forwarding to the refreshing chip, generating an uploading time sequence by the refreshing chip, performing programming operation on corresponding FLASH, performing data read-back and data CRC check after programming, and if the check is correct, sending out a command and reloading the FPGA.
2. The method for on-rail reconstruction of an FPGA-based aerospace electronic system according to claim 1, wherein when the software is reconstructed, the following steps are performed:
s401, erasing the whole corresponding FLASH, and returning to a telemetry frame;
s402; programming is carried out on the corresponding FLASH, and a telemetry frame is returned;
s403, detecting a corresponding FLASH read-back bit stream;
s404, checking CRC, if the CRC is correct, executing S405; if not, then execution 407;
s405, starting FPGA reload, and executing S406; if the production is interrupted, ending;
s406, if the reloading is successful, starting timing refreshing, and if the reloading is failed, returning to the telemetry frame;
s407, returning the telemetry frame, uploading data, and returning the read CRC to fail.
3. The method for on-orbit reconstruction of an FPGA-based avionic system according to claim 2, wherein when the routing switch unit FPGA is reconstructed, the following steps are performed:
s411, closing timing refresh;
s412, periodically returning a telemetry frame;
s413, judging whether the refreshing is successful, if so, executing S401; if not, S411 is performed.
4. The method for on-orbit reconstruction of an FPGA-based avionic system according to claim 2, wherein in S401, after the telemetry frame is returned, it is determined whether the whole slice is successfully erased, if so, S402 is executed; if not, erasing the whole corresponding FLASH.
5. The method for on-orbit reconstruction of an FPGA-based avionic system according to claim 2, wherein in S402, after the telemetry frame is returned, it is determined whether the programming is successful, if yes, S4021 is performed; if not, programming is carried out on the corresponding FLASH again;
s4021, judging whether programming is finished, if yes, executing S403, and if not, executing S402.
6. The on-orbit reconstruction system of the aerospace electronic system based on the FPGA is characterized by comprising a main control unit, a main control communication and protocol analysis module based on an anti-fuse FPGA, a refreshing chip protocol conversion and control module, a CPU routing software loading control module, a telemetering acquisition and framing module, a CPU software operation monitoring module, a communication module, an SRAM type FPGA outside the FPGA, a refreshing chip and a FLASH memory;
the main control communication and protocol analysis module is used for receiving starting, stopping, refreshing and programming commands of a target FPGA from the main control unit, and is compatible with erasing, programming and read-back checking commands of CPU software and an FPGA configuration file FLASH, and commands of FPGA reloading, software resetting and system requiring telemetry information, analyzing the commands and then sending internal instructions and uploading data to the refreshing chip and the CPU routing software loading control module;
the refreshing chip protocol conversion and control module is used for completing the communication protocol conversion, code rate conversion, communication priority arbitration, protocol and logic control functions between the main control unit and the refreshing chip;
the telemetry acquisition and framing module is used for returning telemetry and timing return telemetry according to system commands, and periodically returning current CPU routing software, SRAM type FPGA and refreshing current working state of the chip and register configuration information to the main control unit;
the CPU software operation monitoring module is used for monitoring and collecting the CPU software operation condition, refreshing the working state and the configuration condition of a chip, resetting the system, a CPU heartbeat signal, an SRAM type FPGA loading state, three-mode voting of a functional FPGA important register and the watchdog circuit operation condition in real time;
the CPU route software loading control module is connected with the FLASH memory chip for storing CPU software and an operating system, and is used for erasing, programming and read-back checking the NORFLASH of the stored program according to the main control command, and is used as an interface for accessing the NOR FLASH by the CPU, and when the CPU enters the guide program, the newly uploaded operating system or application program is reloaded through the interface.
7. The on-orbit reconstruction system of the aerospace electronic system based on the FPGA as claimed in claim 6, wherein the refreshing chip is connected with the refreshing chip protocol conversion and control unit through the refreshing communication interface, and the refreshing chip protocol conversion and control unit is connected with the telemetry acquisition and framing unit and the main control communication protocol analysis unit.
8. The on-orbit reconstruction system for an aerospace electronic system based on an FPGA as claimed in claim 6, wherein the main control communication protocol analysis unit and the telemetry acquisition and framing unit are connected with the CPU routing software loading control unit, and the CPU routing software loading control unit is connected with the CPU and the software FLASH memory.
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| CN114661531B (en) * | 2022-02-28 | 2023-08-29 | 成都市硅海武林科技有限公司 | Fine-granularity self-repairing circuit and method for FPGA |
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