CN108268381B - Method for safely realizing fast addressing of data - Google Patents
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- CN108268381B CN108268381B CN201711371592.8A CN201711371592A CN108268381B CN 108268381 B CN108268381 B CN 108268381B CN 201711371592 A CN201711371592 A CN 201711371592A CN 108268381 B CN108268381 B CN 108268381B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
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Abstract
The invention discloses a method for safely realizing quick addressing of data, and belongs to the technical field of computers. In a computer system, some data need to be read quickly, and quick access can be realized by inputting data and searching corresponding addresses; in a network transmission system, a router determines from a received MAC address which port data is transmitted from, where the data is identified and classified by inputting MAC address information. With the development of the times, the system gives more stringent requirements on the address searching time, but no effective measure can quantitatively and safely finish the rapid addressing of data. In order to solve the above problems in the fast addressing of data, the present invention provides a technique for safely implementing fast addressing of data. And configuring a data storage area and a data address according to the requirements of data length and data addressing time in a programming mode, and realizing quick data addressing by matching a data recombination technology and an address recombination technology in a working mode.
Description
Technical Field
The invention discloses a method for safely realizing quick addressing of data, and belongs to the technical field of computers.
Background
In a computer system, some data need to be read quickly, and quick access can be realized by inputting data and searching corresponding addresses; in a network transmission system, a router determines from a received MAC address which port data is transmitted from, where the data is identified and classified by inputting MAC address information. With the development of the times, the system gives more stringent requirements on the address searching time, but no effective measure can quantitatively and safely finish the rapid addressing of data.
In order to solve the above problems in the fast addressing of data, the present invention provides a technique for safely implementing fast addressing of data. And configuring a data storage area and a data address according to the requirements of data length and data addressing time in a programming mode, and realizing quick data addressing by matching a data recombination technology and an address recombination technology in a working mode. The self-checking technology, the data reorganization technology and the address reorganization technology provided by the invention are matched to ensure the correctness of the data in the storage area and the quick addressing of the data.
Disclosure of Invention
The invention aims to provide a technology for safely realizing quick data addressing so as to solve the problem of data addressing caused by large data volume and large address space.
The technical scheme of the invention is as follows: a method for safely realizing fast addressing of data, which comprises the following steps:
the method comprises the following steps: initializing data addressing;
planning a data storage area according to the preset data volume, data address and data addressing time of the system, and specifically operating as follows: calculating the number N of comparison data needed to be performed in a single clock cycle according to the data addressing time to obtain a new data width value (W2) of N data width (W1), and establishing the data (B1), the data address (A1), the new data (B2) and the new data address (A2)
B1＝B2[(W1+1)*mod(A1，N)-1：W1*mod(A1，N)]
Step two: a programming mode;
in the programming mode, the upper computer sends a programming mode command to the data storage area, after the data storage area is prepared, the data storage area judges whether the data storage area is in the programming mode, if the data storage area is in the programming mode, the data storage area starts a data writing mode, the upper computer performs writing operation on the data storage area, and the writing operation of the upper computer automatically translates an operated data address into a new data address;
step three: a working mode;
in the working mode, the data storage area automatically carries out data addressing work, the data storage area automatically carries out polling comparison with data to be compared, if the comparison is correct, decoding is carried out according to the data width and the data address in the step 1) and the operation relation between the new data width and the new data address, the data storage area outputs the data address to the upper computer, and a comparison completion signal is output to the upper computer; if the comparison consistency result is not generated in the whole data space after polling, the data needing to be compared is not matched with the data in the data storage area, and the data storage area feeds the unmatched result back to the upper computer.
The number of comparison data required to be carried out in a single clock cycle in the method is N, N is more than or equal to 2, and N is 2mWherein m is a positive integer.
The specific operational relationship of the operational relationship formula (1) among the data (B1), the data address (A1) and the new data (B2) and the new data address (A2) in the method is shown as the following table:
| upper computer | Addressing data |
| Address/data n1 'b 0/n 2'd (1) | 1’b0/{n2*(2n-1)’hx,n2’d(1)} |
| Address/data n1 'b 1/n 2'd (2) | 1’b0/{n2*(2n-2)’hx,n2’d(2),n2’hx} |
| Address/data n1 'b 10/n 2'd (3) | 1’b0/{n2*(2n-3)’hx,n2’d(3),2*n2’hx} |
| …… | … |
| Address/data n1 'b 11 … 1/n 2'd (2)n) | 1’b0/{n2’d(1),n2*(2n-1)’hx} |
Where n1 is the data address (A1) width, n2 is the data (B1) width, and hx represents the don't care item.
The method further comprises the steps of: and (3) checking mode: and reading back the written data immediately after writing the data, comparing, and if the comparison is consistent, performing a writing command given by the next upper computer, and closing to avoid rewriting the data storage area in other states after finishing the programming mode.
The invention has the advantages and beneficial effects that:
1) the invention can evaluate addressing space, time and resources according to system requirements and hardware resource amount;
2) the amount of addressing data in a single clock cycle can be dynamically configured;
3) the read-back comparison mechanism ensures the safety of the written data;
4) the addressing time is reduced by at least fifty percent or more compared to conventional data addressing techniques.
Drawings
FIG. 1 is a system level schematic of the design of the present invention.
FIG. 2 is a state jump diagram for a particular programming mode.
Fig. 3 is a detailed operating mode state transition diagram.
Detailed Description
A method for safely realizing fast addressing of data, which comprises the following steps:
the method comprises the following steps: initializing data addressing;
planning a data storage area according to the preset data volume, data address and data addressing time of the system, and specifically operating as follows: calculating the number N of comparison data required to be performed in a single clock cycle according to the data addressing time, obtaining a new data width numerical value (W2) as N data width (W1), and simultaneously establishing an operational relation among the data (B1), the data address (A1), the new data (B2) and the new data address (A2), wherein the operational relation refers to formula (1) so as to perform data addressing;
B1＝B2[(W1+1)*mod(A1，N)-1：W1*mod(A1，N)]
step two: a programming mode;
in the programming mode, the upper computer sends a programming mode command to the data storage area, after the data storage area is prepared, the data storage area judges whether the data storage area is in the programming mode, if the data storage area is in the programming mode, the data storage area starts a data writing mode, the upper computer performs writing operation on the data storage area, and the writing operation of the upper computer automatically translates an operated data address into a new data address;
step three: a working mode;
in the working mode, the data storage area automatically carries out data addressing work, the data storage area automatically carries out polling comparison with data to be compared, if the comparison is correct, decoding is carried out according to the data width and the data address in the step 1) and the operation relation between the new data width and the new data address, the data storage area outputs the data address to the upper computer, and a comparison completion signal is output to the upper computer; if the comparison consistency result is not generated in the whole data space after polling, the data needing to be compared is not matched with the data in the data storage area, and the data storage area feeds the unmatched result back to the upper computer.
The number of comparison data required to be carried out in a single clock cycle in the method is N, N is more than or equal to 2, and N is 2mWherein m is a positive integer.
The specific operational relationship of the operational relationship formula (1) among the data (B1), the data address (A1) and the new data (B2) and the new data address (A2) in the method is shown as the following table:
| upper computer | Addressing data | |
| Address/data | n1’b0/n2’d(1) | 1’b0/{n2*(2n-1)’hx,n2’d(1)} |
| Address/data | n1’b1/n2’d(2) | 1’b0/{n2*(2n-2)’hx,n2’d(2),n2’hx} |
| Address/data | n1’b10/n2’d(3) | 1’b0/{n2*(2n-3)’hx,n2’d(3),2*n2’hx} |
| … | … | … |
| Address/data | n1’b11…1/n2’d(2n) | 1’b0/{n2’d(1),n2*(2n-1)’hx} |
Where n1 is the data address (A1) width, n2 is the data (B1) width, and hx represents the don't care item.
The method further comprises the steps of: and (3) checking mode: and reading back the written data immediately after writing the data, comparing, and if the comparison is consistent, performing a writing command given by the next upper computer, and closing to avoid rewriting the data storage area in other states after finishing the programming mode.
The present invention will be described in detail with reference to the accompanying drawings.
The principle of the invention is as follows: the data is converted into a new data form, the operational relation between the data and the data address and between the new data and the new data address is established, and the data volume for comparison in a single clock period is increased, so that the whole data addressing time is reduced.
A method for safely realizing fast addressing of data, which comprises the following steps:
1) initializing data addressing;
planning a data storage area according to the preset data volume, data address and data addressing time of the system, and specifically operating as follows: calculating the number (N) of comparison data required to be performed in a single clock cycle (T) according to the data addressing time (T), wherein N is T/T, obtaining a new data width numerical value (W2) of N data width (W1), and simultaneously establishing an operational relation among the data (B1), the data address (A1), the new data (B2) and the new data address (A2), wherein the operational relation is shown in formula (1) so as to perform data addressing;
B1＝B2[(W1+1)*mod(A1，N)-1：W1*mod(A1，N)]
2) a programming mode;
the programming mode is described in detail below with reference to FIG. 2: the upper computer sends a programming mode command to the data storage area and closes the write enable, the data storage area carries out preparation and initial state judgment, and if the data storage area finishes the preparation work, whether the data storage area enters a programming mode is judged; if the program is not entered into the programming mode, feeding back information which is not entered into the programming mode to the upper computer; after the write enable is started, the upper computer can directly write the data (B1) and the data address (A1) into the data storage area, and the data storage area can automatically decode according to the formula (1) to form new data (B2) and a new data address (A2); the data storage area immediately reads back the written data after each data writing operation, if the comparison is the same, the next data writing operation is carried out, if the comparison is different, the incorrect information is compared and uploaded to the upper computer, all data are written, and the data are compared and correctly uploaded to the upper computer; and the upper computer receives the data initialization completion identifier of the data storage area or gives a command to the data storage area when the data storage area is not in the programming mode, so that the data storage area is prepared and the write enable is closed.
3) A working mode;
the following detailed description of the operation mode is made with reference to fig. 3: the upper computer sends a working mode starting command to the data storage area, the data storage area carries out preparation and initialization state judgment, and if the data storage area finishes the preparation work, whether the data storage area enters a working mode is judged; if the working mode is not entered, feeding back information that the working mode is not entered to the upper computer; after entering a working mode, the data storage area provides normal working information for the upper computer, at the moment, the upper computer outputs data needing addressing to the data storage area, meanwhile, new address information (A2) is reset to zero, new data (B2) is read out from the data storage area and is compared with the data needing addressing according to a formula (1), and if the comparison meets the formula (1), the data storage area outputs a data address (A1) and comparison correct information to the upper computer; if the corresponding new data (B2) in the new data address (A2) is not matched with the data needing addressing, adding 1 to the new data address (A2), reading the corresponding new data (B2), continuing to match with the data needing addressing until the data are matched, and outputting the data address (A1) and correct comparison information to the upper computer by the data storage area according to a formula (1) after the data are matched; and if the polling of the whole data storage area space does not produce a result of consistent comparison, which indicates that the data needing addressing is not matched with the data in the data storage area, the data storage area feeds back the result of unmatched data to the upper computer.
The number N of the comparison data required by the single clock period is more than or equal to 2, and N is 2mWhere m is a positive integer, since dyadic is commonly used in the computer artsProcessing data; if the number of comparison data is m powers of 2 in the address decoding, the conversion between the data address (A1) and the new data address (A2) can be simplified to the new data address (A2) being equal to the data address (A1) minus the lowest m bits.
The operational relationship between the data address and the new data address is shown in the following table:
| upper computer | Addressing data | |
| Address/data | n1’b0/n2’d(1) | 1’b0/{n2*(2n-1)’hx,n2’d(1)} |
| Address/data | n1’b1/n2’d(2) | 1’b0/{n2*(2n-2)’hx,n2’d(2),n2’hx} |
| Address/data | n1’b10/n2’d(3) | 1’b0/{n2*(2n-3)’hx,n2’d(3),2*n2’hx} |
| … | … | … |
| Address/data | n1’b11…1/n2’d(2n) | 1’b0/{n2’d(1),n2*(2n-1)’hx} |
Where n1 is the data address (A1) width, n2 is the data (B1) width, and hx represents the don't care item.
The method further comprises the steps of:
and (3) checking mode: and reading back the written data immediately after writing the data, comparing, and if the comparison is consistent, performing a writing command given by the next upper computer, and closing to avoid rewriting the data storage area in other states after finishing the programming mode.
Example one
A simple example is given here to illustrate the relationship between the data address (A1), data (B1) and the new data address (A2), new data (B2) and the decoding process in the actual engineering process.
In this example, the number N of comparison data is 8, and the data addresses (a1) are 3 'b 000, 3' b001, 3 'b 010, 3' b011, 3 'b 100, 3' b101, 3 'b 110, and 3' b111, respectively, where the width N1 of the data address (a1) is 3; according to the system plan, the number N of the compared data needed in a single clock cycle is 4, a new data address (A2) is obtained, and the lowest m of the data address (A1) is removed to be 2 bits. The new data addresses (a2) are thus 1 'b 0 and 1' b1, where the data address (a2) width n2 equals 1; the following table can be established according to equation (1):
| upper computer | Addressing data | |
| Address/data | 3’b000/8’h1 | 1’b0/{24’hx,8’h1} |
| Address/data | 3’b001/8’h2 | 1’b0/{16’hx,8’h2,8’hx} |
| Address/data | 3’b010/8’h3 | 1’b0/{8’hx,8’h3,16’hx} |
| Address/data | 3’b011/8’h4 | 1’b0/{8’h4,24’hx} |
| Address/data | 3’b100/8’h5 | 1’b1/{24’hx,8’h5} |
| Address/data | 3’b101/8’h6 | 1’b1/{16’hx,8’h6,8’hx} |
| Address/data | 3’b110/8’h7 | 1’b1/{8’hx,8’h7,16’hx} |
| Address/data | 3’b111/8’h8 | 1’b1/{8’h8,24’hx} |
In the programming mode, the upper computer writes addresses and data listed in the upper computer in the table according to requirements, the data storage area can be decoded into data and addresses in the addressing data according to the setting and written into the data storage area for standby, and in the process, the data storage area can complete the corresponding verification mode and upload the written data information to the upper computer after the verification mode is passed.
In the working mode, the upper computer inputs data 8 ' h8 needing comparison into a data storage area and requests comparison, the data storage area compares 8 ' h8 according to formula (1), a new data address (A2 is 1 ' b1) is obtained, the data address (A1 is 3 ' b111), and the data storage area uploads correct data comparison information to the upper computer and gives the data address (A1 is 3 ' b 111). If the method of the invention is not used, the comparison process needs 8 clock cycles, and when the method of the invention is used, the comparison process is changed into 2 clock cycles, and the comparison time is reduced to 25 percent of the original process, thereby greatly improving the efficiency of data addressing.
Example two
A simple example is given here to illustrate the relationship between the data address (A1), data (B1) and the new data address (A2), new data (B2) under the fastest data addressing and the decoding process in the actual engineering process.
In this example, the number N of comparison data is 8, and the data addresses (a1) are 3 'b 000, 3' b001, 3 'b 010, 3' b011, 3 'b 100, 3' b101, 3 'b 110, and 3' b111, respectively, where the width N1 of the data address (a1) is 3; according to the system plan, the number N of the compared data needed in a single clock cycle is 8, a new data address (A2) is obtained, and the lowest m of the data address (A1) is removed to be 3 bits. The new data address (a2 ═ 0), where the new data address (a2) width n2 ═ 0, i.e., without regard to the new data address; the following table can be established according to equation (1):
| upper computer | Addressing data | |
| Address/data | 3’b000/8’h1 | {56’hx,8’h1} |
| Address/data | 3’b001/8’h2 | {48’hx,8’h2,8’hx} |
| Address/data | 3’b010/8’h3 | {40’hx,8’h3,16’hx} |
| Address/data | 3’b011/8’h4 | {32’hx,8’h4,24’hx} |
| Address/data | 3’b100/8’h5 | {24’hx,8’h5,32’hx} |
| Address/data | 3’b101/8’h6 | {16’hx,8’h6,40’hx} |
| Address/data | 3’b110/8’h7 | {8’hx,8’h7,48’hx} |
| Address/data | 3’b111/8’h8 | {8’h8,56’hx} |
In the programming mode, the upper computer writes addresses and data listed in the upper computer in the table according to requirements, the data storage area can be decoded into data and addresses in the addressing data according to the setting and written into the data storage area for standby, and in the process, the data storage area can complete the corresponding verification mode and upload the written data information to the upper computer after the verification mode is passed.
In the working mode, the upper computer inputs data 8 'h 8 needing comparison into a data storage area and requests comparison, the data storage area compares 8' h8 according to formula (1), a new data address (A2 is 0) and a data address (A1 is 3 'b 111) are obtained, and at the moment, the data storage area uploads correct data comparison information to the upper computer and gives the data address (A1 is 3' b 111). If the method of the invention is not used, the comparison process needs 8 clock cycles, and when the method of the invention is used, the comparison process is changed into 1 clock cycle, and the comparison time is reduced to 12.5 percent of the original process, thereby greatly improving the efficiency of data addressing.
Claims (4)
1. A method for safely realizing fast addressing of data, which comprises the following steps:
the method comprises the following steps: initializing data addressing;
planning a data storage area according to the preset data volume, data address and data addressing time of the system, and specifically operating as follows: calculating the number N of comparison data required to be performed in a single clock cycle according to the data addressing time, obtaining a new data width value W2 as N x the data width W1, and simultaneously establishing an operational relation among the data B1, the data address A1, the new data B2 and the new data address A2, wherein the operational relation refers to formula (1) so as to perform data addressing;
step two: a programming mode;
in the programming mode, the upper computer sends a programming mode command to the data storage area, after the data storage area is prepared, the data storage area judges whether the data storage area is in the programming mode, if the data storage area is in the programming mode, the data storage area starts a data writing mode, the upper computer performs writing operation on the data storage area, and the writing operation of the upper computer automatically translates an operated data address into a new data address;
step three: a working mode;
in the working mode, the data storage area automatically carries out data addressing work, the data storage area automatically carries out polling comparison with data to be compared, if the comparison is correct, decoding is carried out according to the data width and the data address in the step one and the operation relation between the new data width and the new data address, the data storage area outputs the data address to the upper computer, and a comparison completion signal is output to the upper computer; if the comparison consistency result is not generated in the whole data space after polling, the data needing to be compared is not matched with the data in the data storage area, and the data storage area feeds the unmatched result back to the upper computer.
2. The method as claimed in claim 1, wherein the number of comparison data required in a single clock cycle in the method is N, N ≧ 2, and N ═ 2mWherein m is a positive integer.
3. The method for safely realizing the fast addressing of the data as claimed in claim 1, wherein the specific operational relationship of the operational relationship formula (1) between the data B1 and the data address A1 and the new data B2 and the new data address A2 is as shown in the following table:
Where n1 is the data address A1 width, n2 is the data B1 width, hx denotes don't care.
4. A method for securely implementing fast addressing of data as claimed in claim 1, wherein said method further comprises the steps of: and (3) checking mode: and reading back the written data immediately after writing the data, comparing, and if the comparison is consistent, performing a writing command given by the next upper computer, and closing to avoid rewriting the data storage area in other states after finishing the programming mode.
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