CN100390556C - Device and method for application specific integrated circuit verification utilizing simulated source data - Google Patents
Device and method for application specific integrated circuit verification utilizing simulated source data Download PDFInfo
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Abstract
The present invention discloses a device for verifying an application-specific integrated circuit (ASIC) by simulation source data, which comprises a comparison module, an ASIC data processing component and an interface module, wherein the comparison module is used for storing simulation source data and expected data consistent with the 3GPP protocol and outputting the simulation source data to the interface module, algorism information is configured, a control instruction is sent to the ASIC data processing component, result data is read and stored at the interface module, and the result data and the expected data are used for comparison verification according to the BIT; the ASIC data processing component is used for carrying out algorithmic manipulation of a band spread system on the simulation source data and outputting the result data; the interface module is used for controlling the data transmission between the comparison module and the ASIC data processing component. The present invention also discloses a method for verifying the ASIC by the simulation source data and has the advantages that the algorithm of the band spread system adopted by an ASIC chip can be verified, the result data and the expected data can be compared according to the BIT, and the arithmetic functions of the ASIC chip is precisely verified by the simple and feasible method.
Description
Technical field
The present invention relates to a kind of special IC (ASIC) functional verification technology, particularly a kind of apparatus and method of utilizing the emulation source data to carry out the ASIC functional verification.
Background technology
At present, in Wideband Code Division Multiple Access (WCDMA) (WCDMA) spread spectrum communication system, asic chip is as the implementation of spread spectrum system core algorithm technology, not only there is big difficulty in its design, itself more complicated of asic chip implementation algorithm, actual application environment is more various, and the asic chip in the WCDMA system in the industry cycle belongs to great technological difficulties.Thereby the related data information of its verification method and thinking is difficult to obtain.How to construct a kind of efficient feasible demo plant and method the spread spectrum system algorithm function of asic chip realization is verified to have suitable difficulty and originality.
Usually, industry can adopt the WCDMA signal generating Instrument as signal source, and the algorithm that the asic chip in the WCDMA system is realized is verified.Fig. 1 is that the ASIC demo plant of prior art is formed structural representation.As shown in Figure 1, adopt the WCDMA signal generating Instrument need in the hardware environment of reality, carry out as the verification method of signal source.Its concrete grammar is exactly: WCDMA signal generating Instrument 101 is received on the base band/intermediate frequency/radio-frequency channel 102 that need carry out the asic chip proof of algorithm; Then the data input ASIC data processor 103 of path 10 2 outputs is handled; At last, the result who directly ASIC data processor 103 is exported analyzes.Wherein, ASIC data processor 103 comprises two major parts: asic chip 104 and digital signal processor (DSP) 105.Asic chip 104 is mainly finished the spread spectrum system algorithm process; DSP105 mainly finishes in the processing procedure various resource distributions and the control to asic chip 104.
But owing to be many bits (BIT) and line output under a lot of situations of data of ASIC data processor output.If directly the output result is compared, can only get its sign bit and compare or be provided with decoding module by comparer and carry out Block Error Rate (BLER) and judge.This analysis is just to the result data of reality and the general comparison of expected data.Thereby the maximum drawback of this verification method is that the utilization instrument can only be verified the general function of institute's placement algorithm in the asic chip.This kind method can't accomplish the result data of ASIC data processor output and the expected data of simulated environment output are carried out comparatively validate by BIT, therefore can't make exact evaluation to the spread spectrum system algorithm function of asic chip realization.Like this, may cause the significant problem of chip to be hidden.In addition, though this kind method can be simulated actual environment as far as possible, structure actual channel environment also needs the instrument of purchasing price costliness, and the checking cost is too high.And, increase decoding module and carry out BLER and judge, the complexity of the interpretation of result that has also increased greatly.Therefore, existing proof scheme is not a kind of way of simple possible.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of device that utilizes the emulation source data to carry out the ASIC checking, the result data of ASIC data processor output and the expected data of simulated environment output can be pressed BIT relatively, and can reduce the checking cost greatly, and then the spread spectrum system algorithm function that can adopt simple demo plant that asic chip is realized is accurately verified.
Another object of the present invention is to provide a kind of method of utilizing the emulation source data to carry out the ASIC checking, can under simple verification environment, carry out input and output control by the result data to the output of ASIC data processor, the expected data of result data and simulated environment output is compared by BIT, thereby the spread spectrum system algorithm function that the method for the enough simple possible of energy realizes asic chip is accurately verified.
The invention discloses a kind of device that utilizes the emulation source data to carry out the ASIC checking, comprising:
Emulation tool, the one section emulation source data that meets the 3GPP agreement that is used for self is generated is carried out the spread spectrum system algorithm process that the ASIC data processor is realized, obtains corresponding expected data, and judges whether to obtain whole expected datas;
Comparison module, be used to receive and store one section emulation source data and expected data from emulation tool, output emulation source data is to interface module, placement algorithm information and sending controling instruction are to the ASIC data processor, read and the event memory data from interface module, and be judged as at emulation tool and obtain whole expected datas and interface module and be judged as when obtaining the partial results data, the current emulation source data that obtains the partial results data is carried out the current resulting part expected data of algorithm process that obtains the partial results data, with the current partial results data that obtain by the BIT comparatively validate, be judged as until interface module and obtain whole result datas;
The ASIC data processor is used to receive steering order, and the emulation source data of input is carried out the spread spectrum system algorithm process and exported result data;
Interface module is used to receive one section emulation source data and exports the ASIC data processor to, receives and the output result data from the ASIC data processor, and judges whether the ASIC data processor has obtained whole result datas.
Described comparison module further comprises, be judged as at emulation tool and obtain part expected data and interface module and be judged as when obtaining whole result data, the current emulation source data that obtains the part expected data is carried out the current resulting partial results data of algorithm process that obtain the part expected data, compare by BIT with the current part expected data that obtains, be judged as until emulation tool and obtain whole expected datas.
Wherein, described comparison module comprises,
PC (PC) is used to store and export one section emulation source data and expected data that meets the 3GPP agreement from emulation tool; Central processing unit (CPU), be used for placement algorithm information and sending controling instruction to the ASIC data processor, read and store expected data from PC, read the emulation source data and export interface module to from PC, read and the event memory data from interface module, and emulation tool be judged as obtain whole expected datas and interface module be judged as obtain whole result datas before to result data and expected data by the BIT comparatively validate, until to whole result datas and all expected datas finish BIT relatively.
Wherein, described comparison module comprises,
PC, be used to store one section emulation source data and expected data that meets the 3GPP agreement from emulation tool, output emulation source data is to CPU, read and the event memory data, and emulation tool be judged as obtain whole expected datas and interface module be judged as obtain whole result datas before to result data and expected data by the BIT comparatively validate, until to whole result datas and all expected datas finish BIT relatively; CPU is used for placement algorithm information and sending controling instruction to the ASIC data processor, reads the emulation source data and exports interface module to, reads and export result data to PC from interface module.
This device also comprises: input buffer (RAMIN), be used for receiving and buffer memory emulation source data from interface module, and export the emulation source data to interface module; And/or output state (RAMOUT), be used for receiving and the buffered results data from interface module, export result data to interface module.
The invention also discloses a kind of method of utilizing the emulation source data to carry out the ASIC checking, be applied to comprise in the demo plant of PC, ASIC data processor and CPU, main treatment step is:
1) circulation did not receive the one section emulation source data that meets the 3GPP agreement that emulation tool generates before the ASIC data processor was finished algorithm process, the emulation source data that is received is carried out the spread spectrum system algorithm process obtain the corresponding results data, simultaneously, described emulation tool carries out the spread spectrum system algorithm process that the ASIC data processor realized to the emulation source data that it generated and obtains corresponding expected data, be judged as when obtaining whole expected datas and partial results data execution in step 2); 2) the current emulation source data that obtains the partial results data is carried out the current resulting part expected data of algorithm process that obtains the partial results data, compare by BIT with the current partial results data that obtain, judge again whether the ASIC data processor obtains whole result datas, if then finish checking; Otherwise ASIC data processor reception emulation source data is carried out algorithm process and is obtained the partial results data, changes step 2 again over to).
Wherein, in the step 1), be judged as when obtaining whole result datas and part expected data execution in step 4); 4) the current emulation source data that obtains the part expected data is carried out the current resulting partial results data of algorithm process that obtain the part expected data, compare by BIT with the current part expected data that obtains, judge again whether emulation tool obtains whole expected datas, if then finish checking; Otherwise emulation tool carries out algorithm process to the emulation source data and obtains the part expected data, changes step 4) again over to.
In the step 1), the ASIC data processor receives before the emulation source data, further comprises, PC is stored in one section emulation source data that meets the 3GPP agreement that emulation tool generates in hard disk or the internal memory.In the step 1), ASIC data processor reception emulation source data is carried out algorithm process and is obtained further comprising after the result data that the ASIC data processor is sent result data into CPU.In the step 1), emulation tool carries out algorithm process to the emulation source data and obtains comprising that further PC is stored in expected data in hard disk or the internal memory after the expected data.In the step 1), the ASIC data processor is sent into result data after the CPU, further comprise, PC from CPU read result data and be stored in hard disk or internal memory; Described expected data and result data are relatively comprised by BIT: PC reads result data and expected data by BIT relatively from hard disk or internal memory.In the step 1), PC comprises that further CPU reads and store expected data from PC after being stored in expected data in hard disk or the internal memory; Described expected data and result data are relatively comprised by BIT: CPU reads expected data and result data by BIT relatively.
By such scheme as can be seen, a kind of apparatus and method of utilizing the emulation source data to carry out the ASIC checking provided by the present invention, the beneficial effect that is brought is:
1) among the present invention, PC memory has stored up one section emulation source data that meets the 3GPP agreement, and is provided with a RAMIN with this section emulation source data buffer memory.When verifying, interface module can circulate and read data among the RAMIN and come that data continuously send in the analog channel environment.Like this, guaranteed that the emulation source data of importing asic chip can cover spread spectrum system algorithm function point comprehensively.
2) because when apparatus of the present invention were worked, CPU also had a lot of other processes except that the transmission result data to need to handle, and it is the reception result data continuously, thereby the data transmission on the CPU is uneven.Therefore, the present invention is provided with a RAMOUT result data is carried out buffer memory, deposits the result data of ASIC data processor output in RAMOUT earlier by interface module, by interface module the result data of being deposited in the RAMOUT is sent into CPU again.Therefore, the present invention can make result data evenly intactly send into CPU by interface module.
3) interface module connects and controls the mutual transmission of data between CPU, ASIC data processor, RAMIN and the RAMOUT, makes the transmission and the processes complete, orderly, even of data, thus the accuracy of the checking that guarantees.
4) according to above description as can be known, CPU can the complete data of reception result in an orderly manner, and with the result data that receives or preserve or import PC and deposit in its hard disk or the internal memory, so CPU or PC can read result data and expected data and carry out comparatively validate by BIT.
5) the present invention needn't expend substantial contribution and Material Cost comes the instrument of purchasing price costliness and build to comprise the such actual channel environment of intermediate frequency and radio-frequency channel, and whole verification environment only needs a checking veneer and a PC.Therefore, the present invention also provides a kind of the most economic and simple proof scheme.
In sum, a kind of apparatus and method of utilizing the emulation source data to carry out the ASIC checking provided by the present invention, greatly reduce the cost of structure verification environment, can use the emulation source data that covers spread spectrum system algorithm function point, fast, neatly the spread spectrum system algorithm that disposes among the ASIC is carried out comparatively validate by BIT, thus the method for can be enough simple possible the algorithm function that ASIC realizes is accurately verified.
Description of drawings
Fig. 1 is the composition structural representation of prior art ASIC demo plant;
Fig. 2 carries out the composition structural representation of device one preferred embodiment of ASIC checking for the present invention utilizes the emulation source data;
Fig. 3 carries out the process flow diagram of method one preferred embodiment of ASIC checking for the present invention utilizes the emulation source data.
Embodiment
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
A kind of device that utilizes the emulation source data to carry out the ASIC checking provided by the present invention comprises following components: comparison module, interface module and ASIC data processor.Wherein, comparison module can be realized by PC and CPU; Interface module can be realized by programmable logic device (PLD) FPGA, EPLD or CPLD.Owing to only deposited one section emulation source data in the PC, in order to simulate the successive transmission of data under the actual channel environment as far as possible, make the emulation source data can cover all functions point of the spread spectrum system algorithm that the ASIC data processor adopted, apparatus of the present invention further comprise the RAMIN that is used for buffer memory emulation source data, and interface module can circulate and continuously read the emulation source data and send into the ASIC data processor from RAMIN; Simultaneously RAMIN makes the emulation source data can import the ASIC data processor equably to the buffer memory of emulation source data to carry out algorithm process, thereby has also guaranteed the accuracy of checking.
In addition, when CPU reads result data by interface module, because CPU will handle a lot of other processes except that reading result data simultaneously, can not continue to transmit uniformly result data, therefore apparatus of the present invention comprise further that also the RAMOUT that is used for the buffered results data makes that result data is complete imports CPU equably, and then have guaranteed the accuracy of checking.Here, the spread spectrum system algorithm that described ASIC data processor adopts is, the spread spectrum system algorithm that before checking, in the ASIC data processor, is disposed according to the checking demand, the ASIC data processor can adopt one or more algorithms in the spread spectrum system simultaneously, and the following stated algorithm just is meant a certain or several spread spectrum system algorithms that the ASIC data processor is adopted.Among the embodiment of following apparatus of the present invention, realize that with FPGA the interface module function is an example,, this interface module is called interface FPGA here.
Because the object of the invention is the spread spectrum system algorithm function that asic chip is realized and verifies, so suppose in following examples, described in the ASIC data processor part the asic chip, that is: DSP, RAMIN and RAMOUT are all working properly in PC, interface FPGA, CPU, the ASIC data processor.That is to say, do not consider the influence of asic chip external factor for the comparative analysis of result data, what promptly verify the result and proved is the situation that the inner spread spectrum system algorithm function of asic chip realizes.
Fig. 2 carries out the composition structural representation of device one preferred embodiment of ASIC checking for the present invention utilizes the system emulation source data.This device comprises following components: PC201, CPU202, RAMIN203, interface FPGA204, ASIC data processor 205 and RAMOUT206.Wherein, as shown in Figure 1 ASIC data processor 103 is the same in ASIC data processor 205 and the prior art, comprises two parts: asic chip 207 and DSP208.Here, CPU202, RAMIN203, interface FPGA204, ASIC data processor 205 and RAMOUT206 can be integrated on the checking veneer 209.
Wherein, PC201 is used to store the emulation source data of the data that meet the 3GPP agreement of one section emulation tool generation as the asic chip checking, result data after the storage ASIC data processor 205 spread spectrum system algorithm process, the storage emulation instrument carries out the expected data after the spread spectrum system algorithm process that ASIC data processor 205 adopted, and by BIT comparative result data and the expected data consistent checking result that draws whether; CPU202, be used to ASIC data processor 205 placement algorithm information and the sending controling instruction DSP208 to the ASIC data processor 205, read the configuration information of asic chip 207 in real time from DSP208, read the emulation source data of PC201 stored and export interface FPGA204 to from the PC201 network interface, read result data and export the PC201 network interface to from interface FPGA204; RAMIN203 is used for receiving and output emulation source data from interface FPGA204; ASIC data processor 205, be used for the emulation source data of input is carried out the spread spectrum system algorithm process and exported result data, this ASIC data processor 205 comprises DSP208 and asic chip 207, wherein, DSP208 is used for sending controling instruction to interface FPGA204, start FPGA204 and start working, asic chip 207 is used for receiving the emulation source data and exporting result data to interface FPGA204 from interface FPGA204; RAMOUT206 is used for buffer memory and exports result data.Data transmission between interface FPGA204 control CPU202, RAMIN203, ASIC data processor 205 and the RAMOUT206 guarantees the complete orderly of data transmission, be used for receiving the emulation source data and being sent to RAMIN203 from CPU202, receive the emulation source data and be sent to ASIC data processor 205 from RAMIN203, from ASIC data processor 205 reception result data and be sent to RAMOUT206, read result data and export CPU202 to from RAMOUT206.
Here, the comparatively validate of result data and expected data also can carry out in CPU202, and in this case, the PC201 in this device is mainly used to storage and output emulation source data, and the storage expected data also exports CPU202 to; CPU202 in this device then is used for being ASIC data processor 205 placement algorithm information, and the DSP208 of sending controling instruction to the ASIC data processor 205, read the configuration information of asic chip 207 in real time from DSP208, read the emulation source data of PC201 stored and export interface FPGA204 to from the PC201 network interface, and, read and store expected data from the PC201 network interface, read and the saving result data from interface FPGA204, CPU202 also is responsible for reading result data and expected data compares checking by BIT.
Owing to only stored one section emulation source data that meets the 3GPP agreement among the PC201, if CPU202 reads the emulation source data from PC201, and only send once this segment data and verify to interface FPGA204, can not guarantee that the emulation source data covers spread spectrum system algorithm function point comprehensively; And, even CPU202 reads the emulation source data from the PC201 circulation and is sent to interface FPGA204, because CPU202 is when the Propagation Simulation source data, also to handle other process except that the Propagation Simulation source data simultaneously, constant Propagation Simulation source data, therefore also just can not simulate the continuous transmission of data under the actual channel environment, the emulation source data be carried out buffer memory so be provided with RAMIN203.When checking, earlier deposit this section emulation source data in RAMIN203, when RAMIN203 is write full or this section emulation source data when all being sent to RAMIN203, read emulation source data among the RAMIN203 by interface FPGA204 again and send into ASIC data processor 205 and carry out algorithm process.If the emulation source data among the RAMIN203 can not satisfy the demand of algorithm process in the ASIC data processor 205, be after interface FPGA204 all has been sent to ASIC data processor 205 with the emulation source data among the RAMIN203, ASIC data processor 205 is not also finished algorithm process and is obtained whole result datas, interface FPGA204 reads emulation source data among the RAMIN203 with circulation and is sent to ASIC data processor 205 and handles, and finishes algorithm process up to ASIC data processor 205 and obtains whole result datas.Like this, the channel circumstance that can simulated data successively sends, thereby the emulation source data that guarantees input ASIC data processor 205 can cover spread spectrum system algorithm function point, and all sidedly the stability and the accuracy of ASIC data processor 205 is made evaluation.
In addition, there are a lot of other processes except that Propagation Simulation source data or result data to need to handle among the CPU202, can not guarantee to continue to read result data to ASIC data processor 205 output emulation source datas or from ASIC data processor 205 by interface FPGA204, therefore the data transmission among the CPU202 is uneven, and the speed of the source data of CPU202 output emulation sometimes can be greater than the reception data speed of ASIC data processor 205, or the speed of CPU202 reception result data can be less than the speed of ASIC data processor 205 output result datas.If directly import the emulation source data into ASIC data processor 205 from CPU202 by interface FPGA204, or directly the result data of ASIC data processor 205 outputs is sent into CPU202 by interface FPGA204, it is inhomogeneous all might data transmission to occur, even the phenomenon of loss of data.Therefore, be provided with RAMIN203 and RAMOUT206 and respectively emulation source data and result data carried out buffer memory, ASIC data processor 205 evenly reads the emulation source data by interface FPGA204 from RAMIN203, and CPU202 also evenly reads result data by interface FPGA204 from RAMOUT206.Make emulation source data and result data evenly intactly processed like this, guaranteed the accuracy of checking.
Because, be provided with RAMIN203 and RAMOUT205 data are carried out buffer memory, and the transmission of data is controlled by interface FPGA204, so result data is even, complete, pass through CPU202 in an orderly manner, perhaps deposited in the hard disk or internal memory of PC201, perhaps deposited in CPU202, thereby PC201 or CPU202 can read its expected data of storing and result data carries out by BIT relatively.
Wherein, have multiple to RAMOUT read-write control mode.For example:, again result data is read when RAMOUT is write when full; When RAMOUT is write data, also data are read; Perhaps RAMOUT is divided into two zones, when a zone writes data therein, also from another regional reading of data or the like mode.The RAMOUT that embodiment adopted of described apparatus of the present invention and method read-write control mode is: when RAMOUT is write when full, data are read again.Owing to the present invention relates to verification technique, the read-write control mode of RAMOUT is not an emphasis of the present invention, so other control mode is not done detailed description at this.
The present invention utilizes the emulation source data to carry out the device of ASIC checking, and its principle of work is as follows:
At first, CPU202 is ASIC data processor 205 placement algorithm information according to current spread spectrum system proof of algorithm demand, and transmission comprises the steering order of described algorithm information to DSP208, start 205 work of ASIC data processor, DSP208 starts interface FPGA204 work again to interface FPGA204 sending controling instruction then.
After interface FPGA204 is activated, send interrupt request to CPU202 earlier, CPU202 response interrupt request reads the emulation source data and exports interface FPGA204 to from hard disk or the internal memory of PC201.
Then, interface FPGA204 continues that the emulation source data that receives is sent into RAMIN203 and carries out buffer memory, until RAMIN203 be filled with or PC201 in the emulation source data all be sent among the RAMIN203.Interface FPGA204 reads the emulation source data and exports asic chip 207 to from the RAMIN203 circulation again, carries out the spread spectrum system algorithm process by ASIC data processor 205.Wherein, when ASIC data processor 205 carries out algorithm process, realize the spread spectrum system algorithm function, provide algorithm configuration and control for asic chip 207 by DSP208 by asic chip 207.
When interface FPGA204 receives the data of asic chip 207 outputs, show that ASIC data processor 205 begins to have result data output, this moment, asic chip 207 meetings were automatically with result data input interface FPGA204.Interface FPGA204 deposits the result data that receives in RAMOUT206 again.Here, interface FPGA204 continues result data is write RAMOUT206, has been write full or asic chip 207 does not have data output up to RAMOUT206.Asic chip 207 described here does not have data output to show that the data processing of ASIC data processor 205 finishes.
When RAMOUT206 has been write full or asic chip 207 when not having data output, interface FPGA204 reads result data and sends interrupt request to CPU202 from RAMOUT206, CPU202 response interrupt request reads result data from interface FPGA204 and sends into PC201, and PC201 is stored in result data in hard disk or the internal memory then.PC201 has also stored the expected data after the emulation tool spread spectrum system algorithm process simultaneously in hard disk or internal memory.At last, PC201 reads its result data of storing and expected data and carries out comparison by BIT, and relatively whether two data are consistent, are verified the result.
Here, if comparatively validate carries out in CPU202, then the interrupt request of CPU202 response interface FPGA204 reads and the event memory data from interface FPGA204; PC201 has also stored the expected data after the emulation tool spread spectrum system algorithm process simultaneously and has been sent to CPU202 in hard disk or internal memory, by CPU202 expected data is preserved; At last, CPU202 reads its result data of storing and expected data and carries out comparison by BIT, is verified the result.
Here, when ASIC data processor 205 carries out algorithm process, CPU202 will read the configuration information of algorithm process the asic chip 207 in real time from DSP208, be convenient to locate the problem that occurs in the checking.
In the such scheme, described emulation tool can be COSSAP or SPW.
Based on said apparatus, the present invention utilizes the emulation source data to carry out the method for ASIC checking, as shown in Figure 3, may further comprise the steps:
Step 300: emulation tool generates one section emulation source data that meets the 3GPP agreement, and it is stored in the hard disk or internal memory of PC.
Step 301: interface module reads the emulation source data and deposits RAMIN in from PC by CPU.
Step 302: interface module is judged whether RAMIN is write completely or whole emulation source datas in the PC has been sent into RAMIN, if change step 303 over to; If not, then return step 301, continue to write the emulation source data to RAMIN.
Step 303: from the beginning interface module reads the emulation source data among the RAMIN.
Step 304: interface module reads the emulation source data from RAMIN successively, and the current emulation source data that reads is sent into the ASIC data processor, and the ASIC data processor carries out the spread spectrum system algorithm process to the emulation source data of input again.
Step 305: interface module judges whether the ASIC data processor has data output, if having, shows that existing partial simulation source data is processed to be result data, changes step 306 over to; If no, showing does not also have the emulation source data to be processed to be result data, then returns step 305 and waits for.
Step 306: the result data that interface module is exported the ASIC data processor that receives writes RAMOUT.Here, when the ASIC data processor has result data to produce, can export result data to interface module automatically, interface module has certain spatial cache, can be before result data be write RAMOUT the buffered results data, therefore can not cause loss of data.
Step 307: it is full that interface module judges whether RAMOUT is write, if it is full to show that RAMOUT has been write, the result data in the RAMOUT need be read, and therefore changes step 309 over to; If not, show in the RAMOUT and also have living space, can continue to deposit in result data, then change step 308 over to.
Step 308: interface module judges whether the ASIC data processor has data output, if having, shows that judgement RAMOUT is not write full and also has result data in output in step 307, should continue to write result data to RAMOUT, therefore changes step 306 over to; If no, though show that RAMOUT is not write completely in step 307, this partial data is handled and is finished, and the result data in the RAMOUT need be read, and then changes step 309 over to.
Step 309: interface module reads result data from RAMOUT, again it is sent into CPU; PC reads result data from CPU, and it is stored in hard disk or the internal memory.Here, if comparatively validate carries out in CPU, then step 309 is: interface module reads result data and output from RAMOUT, and CPU reads and the event memory data.
Step 310: interface module judges whether the ASIC data processor has data output, if have,, also has result data in output though show that judgement RAMOUT is write completely in step 307, need to continue result data is buffered in the RAMOUT, therefore return step 306; If no, show that this partial data processing finishes, and then changes step 311 over to.
Step 311: interface module judges whether the ASIC data processor has obtained whole result datas, if then change step 313 over to; Otherwise, change step 312 over to.Here, when the ASIC data processor obtains whole result data, can send the signal that the expression algorithm process finishes to obtain whole result datas to interface module.
Step 312: interface module judges whether the ASIC data processor receives the emulation source data among the RAMIN fully, if, show that interface module sends to the ASIC data processor from the beginning to the end with one section emulation source data of being deposited among the RAMIN and handles, owing to handle also end in step 311 evaluation algorithm, therefore need circulation that the emulation source data among the RAMIN is sent to the ASIC data processor and carry out algorithm process, be that the emulation source data that from the beginning interface module should read among the RAMIN is sent to the ASIC data processor, then return step 303; Otherwise, show that interface module does not also all send to the ASIC data processor with one section emulation source data of being deposited among the RAMIN and handles, owing to handle also end in step 311 evaluation algorithm, therefore continue successively the emulation source data among the RAMIN to be sent to the ASIC data processor and carry out algorithm process, then return step 304.
Step 313: the simulation process that emulation tool carries out the spread spectrum system algorithm that the ASIC data processor adopted to the emulation source data that it generated generates expected data, and expected data is stored in the hard disk or internal memory of PC.Similarly, as described above the algorithm process of ASIC data processor is the same, if this section emulation source data can not satisfy the needs of algorithm process, be that emulation tool is handled whole emulation source datas, but the algorithm process of emulation tool also there is not end, also do not obtain whole expected datas, emulation tool also will circulate this section emulation source data will be handled this moment, up to the algorithm process end of emulation tool and obtain whole expected datas.Here, if comparatively validate carries out in CPU, then in the step 313 the expectation data storage in the hard disk of PC or internal memory after, comprise that further CPU reads and preserve expected data from PC.
Step 314:PC reads expected data and result data from hard disk or internal memory, and relatively whether two data are consistent to press BIT, are verified the result.Here, if comparatively validate carries out in CPU, then step 314 is: CPU reads expected data and result data compares checking.
Because the processing of step 313 is the processing for expected data, and is separate in the processing relevant with result data with other.Therefore step 313 can generate after the emulation source data and in the step 314 expected data and result data be handled by any moment before the BIT comparison by emulation tool in step 300.Equally, it is separate that PC or CPU read processing and step 310 decision process of interface module to the step 312 of result data and storage in the step 309, therefore, in the step 309 PC or CPU read result data and the storage processing and step 310 to step 312 also can executed in parallel.
In addition, the inventive method can adopt three kinds of processing modes that the spread spectrum system algorithm that the ASIC data processor is adopted is verified, wherein second kind of processing mode that shown in Figure 3 is, and described three kinds of processing modes are respectively:
One, emulation tool generates after the emulation source data in the step 300, in step 313, emulation tool to the emulation source data carry out algorithm process obtain whole expected datas be stored among the CPU or the hard disk or internal memory of PC in; In step 302, RAMIN has been filled with after emulation source data in the PC or emulation source data all be written into RAMIN, and from step 303 to step 310, the ASIC data processor receives the emulation source data and carries out algorithm process, obtains the partial results data; Change step 314 then over to, CPU or PC read the current emulation source data that obtains the partial results data and carry out the current resulting part expected data of algorithm process that obtains the partial results data, compare checking with the current partial results data that obtain, change step 311 judgement ASIC data processor again over to and whether obtain whole result datas, promptly whether the algorithm process of ASIC data processor finishes.Just setting, get rid of step 311 to step 313, is checking sub-process A the whole checking flow process from step 303 to step 314.After CPU or PC have stored whole expected datas that emulation tool generates, system can carry out this checking sub-process A repeatedly, and the judgement of execution in step 311 and step 312 after executing checking sub-process A each time, obtain whole result datas until judgement ASIC data processor in step 311, finish algorithm process, finally verified the result.
Here, this checking sub-process A also can be according to the several checking sub-process of the processing condition data at that time A different process parallel processing of correspondence respectively, preferable parallel mode is: just can not begin when previous checking sub-process A also finishes next checking sub-process A, but step identical with a back checking sub-process A among the previous checking sub-process A was all correspondingly carried out before the step of a back checking sub-process A, carried out and arrive by that analogy before the step 303 of the step 303 among the promptly previous checking sub-process A in a back checking sub-process A except that step 311 to the step 304 the step 313 and arrive step 314.
Two, RAMIN has been filled with after emulation source data in the PC or emulation source data all be written into RAMIN in the step 302, receive the emulation source data from step 303 to step 310ASIC data processor and carry out algorithm process, obtain the partial results data, change step 311 again over to and judge whether to obtain whole result datas; Just set, from step 303 to step 312 is that a result data generates sub-process the whole checking flow process, RAMIN has been filled with after emulation source data in the PC or emulation source data all be written into RAMIN in step 302, system can carry out this result data repeatedly and generate sub-process, obtains whole result datas and deposits CPU in or PC until carrying out algorithm process at step 311 judgement ASIC data processor.Then in step 313, emulation tool to the emulation source data carry out algorithm process obtain whole expected datas deposit among the CPU or the hard disk or internal memory of PC in; Change step 314 again over to, CPU or PC read whole expected datas and whole result data is verified, is finally verified the result.Here, also can generate whole expected datas in step 313 earlier, begin to handle obtaining whole result datas again from step 302, carry out the checking of total data in step 314 at last.
Here, this result data generates sub-process can generate the corresponding different respectively process parallel processing of sub-process according to the several result datas of processing condition data at that time, preferable parallel processing mode is: just can not begin when previous result data generation sub-process also finishes next result data generation sub-process, but previous result data generates step identical with back result data generation sub-process in the sub-process and all correspondingly carried out before the step of back result data generation sub-process, carries out also before the step 303 of the step 303 in the promptly previous result data generation sub-process in back result data generation sub-process and arrives step 304 by that analogy to step 312.
Three, RAMIN has been filled with after emulation source data in the PC or emulation source data all be written into RAMIN in the step 302, receive the emulation source data from step 303 to step 310ASIC data processor and carry out algorithm process, obtain the partial results data, change step 311 judgement again over to and whether obtain whole result datas, and judge in step 312 whether the ASIC data processor receives whole emulation source datas; Just set, from step 303 to step 312 is that a result data generates sub-process the whole checking flow process, RAMIN has been filled with after emulation source data in the PC or emulation source data all be written into RAMIN in step 302, system can carry out this result data repeatedly and generate sub-process, carries out algorithm process until the ASIC data processor and obtains whole result datas and deposit CPU in or PC.Then in step 313, emulation tool to the emulation source data carry out algorithm process obtain the part expected data deposit among the CPU or the hard disk or internal memory of PC in; Change step 314 again over to, CPU or PC read the current emulation source data that obtains the part expected data and carry out the current resulting partial results data of algorithm process that obtain the part expected data, verify with the current part expected data that obtains, and then return step 313 and obtain the part expected data.Just set, from step 313 to step 314 are checking sub-process B the whole checking flow process, after CPU or PC memory have stored up whole result datas, system can carry out this checking sub-process B repeatedly, carry out algorithm process until emulation tool and obtain whole expected datas, it is deposited in CPU or PC and carries out comparatively validate, finally verified the result.
Here, this result data generates sub-process or checking sub-process B also can generate sub-process or the corresponding different respectively process parallel processing of checking sub-process B according to the several result datas of processing condition data at that time, preferable parallel processing mode is: just can not begin when previous result data generation sub-process also finishes next result data generation sub-process, but previous result data generates step identical with back result data generation sub-process in the sub-process and all correspondingly carried out before the step of back result data generation sub-process, carries out also before the step 303 of the step 303 in the promptly previous result data generation sub-process in back result data generation sub-process and arrives step 304 by that analogy to step 312; Equally, when also finishing next checking sub-process B, previous checking sub-process B just can not begin, but step identical with a back checking sub-process B among the previous checking sub-process B was all correspondingly carried out before the step of a back checking sub-process B, carried out and arrive by that analogy step 314 before the step 313 of the step 313 among the promptly previous checking sub-process B in a back checking sub-process B.
By above description for three kinds of processing modes verifying in the inventive method as seen, adopt above-mentioned three kinds of processing modes all can finish comprehensive checking of the spread spectrum system algorithm that the ASIC data processor is adopted, thereby the algorithm function that asic chip is realized is made judgement accurately.
As seen, use the invention described above device or method one preferred embodiment all can use cover spread spectrum system algorithm function point the emulation source data fast, neatly the spread spectrum system algorithm of realizing among the ASIC is made checking, can accomplish simultaneously the result data of ASIC data processor output and the corresponding expected data of simulated environment output are carried out comparative analysis by BIT, thereby energy the most simple enough method is accurately verified the algorithm function that realizes in the asic chip.
Claims (16)
1. a device that utilizes the emulation source data to carry out the application-specific integrated circuit ASIC checking is characterized in that, comprising:
Emulation tool, the one section emulation source data that meets the 3GPP agreement that is used for self is generated is carried out the spread spectrum system algorithm process that the ASIC data processor is realized, obtains corresponding expected data, and judges whether to obtain whole expected datas;
Comparison module, be used to receive and store one section emulation source data and expected data from emulation tool, output emulation source data is to interface module, placement algorithm information and sending controling instruction are to the ASIC data processor, read and the event memory data from interface module, and be judged as at emulation tool and obtain whole expected datas and interface module and be judged as when obtaining the partial results data, the current emulation source data that obtains the partial results data is carried out the current resulting part expected data of algorithm process that obtains the partial results data, with the current partial results data that obtain by bit BIT comparatively validate, be judged as until interface module and obtain whole result datas;
The ASIC data processor is used to receive steering order, and the emulation source data of input is carried out the spread spectrum system algorithm process and exported result data;
Interface module is used to receive one section emulation source data and exports the ASIC data processor to, receives and the output result data from the ASIC data processor, and judges whether the ASIC data processor has obtained whole result datas.
2. device according to claim 1, it is characterized in that, described comparison module further comprises, be judged as at emulation tool to obtain whole expected datas and interface module and be judged as when obtaining whole result data, with whole expected datas and all result datas press the BIT comparison.
3. device according to claim 1, it is characterized in that, described comparison module further comprises, be judged as at emulation tool and obtain part expected data and interface module and be judged as when obtaining whole result data, the current emulation source data that obtains the part expected data is carried out the current resulting partial results data of algorithm process that obtain the part expected data, compare by BIT with the current part expected data that obtains, be judged as until emulation tool and obtain whole expected datas.
4. according to claim 1,2 or 3 described devices, it is characterized in that described comparison module comprises,
PC PC is used to store and export one section emulation source data and expected data that meets the 3GPP agreement from emulation tool;
Central processor CPU, be used for placement algorithm information and sending controling instruction to the ASIC data processor, read and store expected data from PC, read the emulation source data and export interface module to from PC, read and the event memory data from interface module, and emulation tool be judged as obtain whole expected datas and interface module be judged as obtain whole result datas before to result data and expected data by the BIT comparatively validate, until to whole result datas and all expected datas finish BIT relatively.
5. according to claim 1,2 or 3 described devices, it is characterized in that described comparison module comprises,
PC PC, be used to store one section emulation source data and expected data that meets the 3GPP agreement from emulation tool, output emulation source data is to central processor CPU, read and the event memory data, and emulation tool be judged as obtain whole expected datas and interface module be judged as obtain whole result datas before to result data and expected data by the BIT comparatively validate, until to whole result datas and all expected datas finish BIT relatively;
CPU is used for placement algorithm information and sending controling instruction to the ASIC data processor, reads the emulation source data and exports interface module to, reads and export result data to PC from interface module.
6. according to claim 1,2 or 3 described devices, it is characterized in that this device also comprises:
Input buffer RAMIN is used for receiving and buffer memory emulation source data from interface module, exports the emulation source data to interface module; And/or
Output state RAMOUT is used for receiving and the buffered results data from interface module, exports result data to interface module.
7. according to claim 1,2 or 3 described devices, it is characterized in that described interface module is a programmable logic device (PLD).
8. according to claim 1,2 or 3 described devices, it is characterized in that described emulation tool is COSSAP or SPW.
9. a method of utilizing the emulation source data to carry out the application-specific integrated circuit ASIC checking is applied to comprise in the demo plant of PC PC, ASIC data processor and central processor CPU, it is characterized in that, main treatment step is:
1) circulation did not receive the one section emulation source data that meets the 3GPP agreement that emulation tool generates before the ASIC data processor was finished algorithm process, the emulation source data that is received is carried out the spread spectrum system algorithm process obtain the corresponding results data, simultaneously, described emulation tool carries out the spread spectrum system algorithm process that the ASIC data processor realized to the emulation source data that it generated and obtains corresponding expected data, be judged as when obtaining whole expected datas and partial results data execution in step 2);
2) the current emulation source data that obtains the partial results data is carried out the current resulting part expected data of algorithm process that obtains the partial results data, compare by bit BIT with the current partial results data that obtain, judge again whether the ASIC data processor obtains whole result datas, if then finish checking; Otherwise ASIC data processor reception emulation source data is carried out algorithm process and is obtained the partial results data, changes step 2 again over to).
10. method according to claim 9 is characterized in that, this method further comprises:
In the step 1), obtain whole expected datas and all during result data, execution in step 3 being judged as);
3) whole expected datas and whole result data are pressed BIT relatively, finish checking.
11. method according to claim 9 is characterized in that, this method further comprises:
In the step 1), be judged as when obtaining whole result datas and part expected data execution in step 4);
4) the current emulation source data that obtains the part expected data is carried out the current resulting partial results data of algorithm process that obtain the part expected data, compare by BIT with the current part expected data that obtains, judge again whether emulation tool obtains whole expected datas, if then finish checking; Otherwise emulation tool carries out algorithm process to the emulation source data and obtains the part expected data, changes step 4) again over to.
12. according to each described method in the claim 9 to 11, it is characterized in that in the step 1), the ASIC data processor receives before the emulation source data, comprise that further PC is stored in one section emulation source data that meets the 3GPP agreement that emulation tool generates in hard disk or the internal memory.
13. according to each described method in the claim 9 to 11, it is characterized in that in the step 1), ASIC data processor reception emulation source data is carried out algorithm process and obtained after the result data, comprise that further the ASIC data processor is sent result data into CPU.
14., it is characterized in that in the step 1), emulation tool carries out algorithm process to the emulation source data and obtains comprising that further PC is stored in expected data in hard disk or the internal memory after the expected data according to each described method in the claim 9 to 11.
15. method according to claim 13 is characterized in that, in the step 1), the ASIC data processor is sent into result data after the CPU, further comprise, PC from CPU read result data and be stored in hard disk or internal memory;
Described expected data and result data are relatively comprised by BIT: PC reads result data and expected data by BIT relatively from hard disk or internal memory.
16. method according to claim 14 is characterized in that, in the step 1), PC comprises that further CPU reads and store expected data from PC after being stored in expected data in hard disk or the internal memory;
Described expected data and result data are relatively comprised by BIT: CPU reads expected data and result data by BIT relatively.
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| CN101042424B (en) * | 2007-04-26 | 2010-08-11 | 北京南山之桥信息技术有限公司 | Method and apparatus for detecting application-specific integrated circuits |
| CN102420982B (en) * | 2011-10-31 | 2013-09-04 | 展讯通信（上海）有限公司 | Chip, checking method and system thereof, and processor end |
| CN111443892B (en) * | 2019-01-16 | 2022-04-29 | 长鑫存储技术有限公司 | Comparison method of simulation results |
| CN114330221B (en) * | 2021-11-22 | 2022-09-23 | 北京百度网讯科技有限公司 | Score board implementation method, score board, electronic device and storage medium |
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| US6223272B1 (en) * | 1998-07-15 | 2001-04-24 | Siemens Aktiengesellschaft | Test vector verification system |
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