CN102004711B - Single-interrupt real-time data transmission method based on FPGA (Field Programmable Gate Array) - Google Patents

Abstract

The invention relates to a data transmission method, in particular to a real-time data transmission method in which the data of a plurality of asynchronous data sources is buffered through single-interrupt data transmission equipment based on an FPGA (Field Programmable Gate Array) and then sent to an upper computer, belonging to the technical field of real-time signal processing. The real-time data transmission method comprises the following steps of: firstly selecting an appropriate interrupt cycle according to a conditional inequality of data transmission without data loss; then establishing data buffers in the FPGA, and establishing writing state registers of the data buffers; and then generating a cyclic interrupt signal according to half full and full signals sent by the data buffers, wherein the upper computer triggers an interrupt service routine by responding to the cyclic interrupt signal so as to achieve the purpose of real-time continuous transmission. Compared with a multi-interrupt source trigger mode, the real-time data transmission method reduces the programming and debugging complexity of software and hardware and enhances the reliability of a system; in addition, the magnitude of data quantity generated by each interrupt is relatively stable, therefore the data is more convenient for intensive batch transmission and post processing.

Description

A kind of single Real-time Data Transfer Method of interrupting based on FPGA

Technical field

The present invention relates to a kind of data transmission method; Be particularly related to the data in a plurality of asynchronous datas source are carried out buffer memory through the single interrupt data transmission equipment based on FPGA; Re-send to a kind of Real-time Data Transfer Method of host computer, belong to the real-time signal processing technology field.

Background technology

Operations such as Modern Communication System for example often need be searched for rapidly various non-co-operation signals in the military communication reconnaissance system, intercepts and captures, measures, analyzes, discerned, supervision; This time requirement to digital signal processing is very harsh, must adopt the high-speed dedicated hardware system to finish the work.The high-speed real-time digital signal processing framework of FPGA+DSP/MCU/CPU etc. needs in the digital information processing system of high real-time very common in communication, radar system etc.Therefore, the high efficient and reliable transmission of high-speed data between these two kinds of modules such as FPGA and DSP/MCU/CPU just seems particularly important.FPGA usually can be as a high-speed data source as a kind of parallel high-speed hard wire logic device of realizing the complex digital algorithm logic.And DSP/MCU/CPU etc. are as a relative low speed but use Digital Signal Analysis treatment facility flexibly often to be in the data receiver position of (or claiming host computer).The characteristics of the data stream that FPGA produced are in the following several ways: uninterrupted continuous data stream, aperiodicity bursty traffic, periodic burst data stream etc., and various data stream possibly have different data rates.

For the different asynchronous data source of these speed, accomplish the real time continuous data transmission, traditional way is to produce the real-time continuous transmission that a plurality of different look-at-mes accomplish data for the method for host computer to different asynchronous data sources.But,, and cause various system stability, integrity problems such as system crash easily based on more complicated all such as the software and hardware programming in multiple interrupt source, debugging.

Summary of the invention:

The present invention is primarily aimed at the software and hardware detail programming complicacy of traditional multiple interrupt source formula Real-time Data Transfer Method, the shortcoming of poor reliability; A kind of single real time continuous data transmission method that interrupts based on FPGA has been proposed; This method has not only reduced the number of times that produces interruption; And make interrupt interval have the fixed cycle, improve the efficient of data transmission, and simplified the complexity of design.

Single Real-time Data Transfer Method of interrupting based on FPGA; Be through on FPGA, making up n and the corresponding data buffer (B1 in various asynchronous datas source earlier; B2;, Bn), assist to accomplish the real time continuous data transmission through the case pointer of writing that adopts suitable single interrupt source and n data buffer zone again.At first, in n asynchronous data source, select a data source to adopt the method for ping-pong buffers to set up the data buffer; Secondly; Set up the general data buffer zone of non-ping-pong for remaining n-1 asynchronous data source; Set up for n data buffer zone simultaneously and write the case pointer register; Wherein, the case pointer of writing of non-ping-pong buffer is current write operation address value, and the case pointer of ping-pong buffer can be only with 0 or 1 represent just to carry out write operation on/following data buffering half district; Then, set up single interrupt source data transmission trigger mechanism to unique ping-pong buffer with periodic feature; At last, accomplish the programming of host computer interrupt service subroutine, it should be noted that the data buffer that the case pointer storage of variables obtains when once interrupting on preserving of writing that in host computer procedure, also need set up a data buffer zone writes case pointer.

Might as well suppose that the B1 buffer zone is selected as ping-pong buffer, promptly the B1 buffer zone be divided into up and down two have an identical storage depth partly distinguish B1L and B1H, and utilize its half-full and full up signal to produce look-at-me.The write data speed of supposing the B1 data buffer is the W1 byte per second, and the memory data output of B1 ping-pong buffer B1L or B1H is the S0 byte, and then B1L or B1H buffer zone are write full required T1 storage time and be:

T1＝S1/W1

Obviously, T1 also is the interrupt cycle of interrupt source.And host computer has read B1L or B1H buffer data required time is:

T1’＝S1/R

Wherein R is a host computer read data speed, and unit is similarly byte per second.

So, then the B2 buffer zone T1 in the time institute's data quantity stored be S2=W2 * T1, W2 is a write data speed; And host computer has read this data required time be: T2 '=S2/R.In like manner, the Bk data buffer (k=1,2 ..., n) T1 in the time institute's data quantity stored be Sk=Wk*T1, it is Tk '=Sk/R that host computer has read all data required times, wherein, k=1,2 ..., n.It should be noted that each data buffer size must more than or equal to its T1 memory data output Sk in the time (k=1,2 ..., n) 2 times.

Host computer will read B1 fully, B2 ..., the time T s that all data that the Bn buffer zone stores up at the T1 time memory need is:

Ts＝T1’+T2’+...+Tn’

＝S1/R+S2/R+...+Sn/R

＝(W1+W2+...+Wn)×I1/R

Obviously, guarantee continuously transmission and obliterated data not need satisfy condition of data in real time:

Ts＜T1，

Also promptly, need satisfy condition:

W1+W2+...+Wn＜R

A kind of single real time continuous data transmission method that interrupts based on FPGA comprises following concrete steps:

Step 1: select suitable interrupt cycle

According to each asynchronous data source 1,2 ..., the read data speed R of the write data speed Wk of n and host computer utilizes not real time continuous data transmission conditions inequality W1+W2+...+Wn＜R under the obliterated data, the feasibility that at first affirmation system realizes.Under the attainable prerequisite of system, according to size and other restrictive conditions of FPGA hardware resource, select suitable T1 interrupt cycle, again because the total bytes of each data buffer is at least (W1+W2+...+Wn) * T1 * 2.

Step 2: create the data buffer

According to each asynchronous data source 1,2 ... The write data speed Wk of n and interrupt cycle T1, confirm that the buffer stores amount size in each asynchronous data source is Wk * T1 * 2, for setting up n data buffer zone in this n asynchronous data source; And confirm that some data buffers wherein are ping-pong buffer, and might as well suppose to select B1 is ping-pong buffer, its buffer zone is divided into bottom half B1L and B1H; Have half-full and full up indicator signal, other data buffer then gets final product for the general data buffer zone.

Step 3: that creates each data buffer writes the case pointer register

Create each data buffer write the case pointer register time, ping-pong buffer B1 wherein writes the value that the case pointer value is a current write operation address most significant digit, its value possibly be 0 or 1, and the case pointer of writing of other data buffers is current write operation address value.

Step 4: produce the periodic interruptions signal

Half-full and the full up signal of buffer zone that produces according to the write operation of ping-pong buffer B1 produces and the corresponding periodic interruptions signal of host computer; This look-at-me is sent to host computer can trigger interrupt service subroutine, reads each data buffer data manipulation among the FPGA thereby accomplish.

Step 5: set up each data buffer among host computer and the FPGA (B1, B2 ..., the EBI between Bn).

Read clock C, read operation address A and conversion of signals reading clock C, read to enable (E1 such as read to enable what comprise in the read operation of the host computer instruction for each data buffer; E2;, En) with read address (A1R, A2R;, AnR) signal and each buffer zone write the case pointer register read address signal AR etc.To read the data in the above-mentioned storage space.

Step 6: create the host computer interrupt service subroutine

The host computer interrupt service subroutine course of work is following: after the host computer interrupt service subroutine receives hardware interrupt; Do earlier and whether want initialized judgement: if system is firm electrification reset or other forms reset after; Then the historical write pointer register value with each buffer zone write address of FPGA and host computer is initialized as its corresponding start address, otherwise skips this initialization step.Read the current of each data buffer then and write the case pointer register value, and when preserving last the interruption in the host computer procedure each data buffer of storage write the case pointer register value, might as well be called history and write the case pointer register value.The data that read each data buffer appropriate address section among the FPGA are accomplished in the interim backup that interrupt service subroutine utilizes the current history of writing case pointer and host computer preservation to write case pointer then; And after history is write the backup of case pointer register value and before the host computer read operation; Write the case pointer register value to history and be updated to the current case pointer register value of writing, can correctly read the data of each buffer zone appropriate address section when guaranteeing that interrupt next time.The host computer interrupt service subroutine is carried out and is finished after read operation finishes, and gets into and waits for next interruption status.

Step 7: host computer is interrupt service subroutine described in the recursive call step 6 under the triggering of periodic interruptions signal, can reach the real time continuous data transmission destination.

Beneficial effect

The inventive method contrasts the data transmission method of traditional multiple interrupt source triggering mode; Greatly reduce the complexity of software and hardware detail programming; Thereby make that the real-time Data Transmission of system is stable more, reliable because interruption is single; Reduced the unsettled possibility of system, the data volume size of each interruption generating is relatively stable, and data are more convenient for concentrating and are carried out bulk transfer and aftertreatment.

Description of drawings:

Fig. 1-list interrupts real-time Data Transmission device synoptic diagram;

Fig. 2-host computer interrupt service subroutine process flow diagram.

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is further specified.

Suppose to have a real-time Data Transmission device as shown in Figure 1. Asynchronous data source 1,2 ..., n is writing clock C1 separately, C2 ..., the write data speed under the Cn effect is respectively W1, W2 ..., Wn.We might as well suppose that the number in asynchronous data source is 3, i.e. the write data speed in n=3, and setting data source 1,2,3 is respectively 50KB/s, 100KB/s, 150KB/s.Simultaneously, the read data speed of setting host computer processor is 1200KB/s.

Step 1: judge whether to satisfy the not real-time Data Transmission condition of obliterated data.Obviously, because the write data speed sum W1+W2+W3 of three data sources equals 300KB/s, much smaller than host computer read data speed 1200KB/s, therefore, the continuous real-time data transmission of obliterated data can not realize.In addition, we suppose that the FPGA resource is enough abundant, and selection interrupt cycle is 10ms, i.e. 0.01s.

Step 2: confirm each data buffer size, set up 3 data buffer zones.We might as well select the buffer zone of data source 1 as ping-pong buffer.Obviously the size of the buffer zone B1 of data source 1 should be W1 * T1 * 2, and wherein, T1 is to be 0.01s in the interrupt source cycle, and W1=50KB/s is so the total size of the ping-pong buffer of data source 1 is 1KB.In like manner, the buffer size of data source 2 is W2 * T1 * 2=2KB, and the buffer size of data source 3 is W3 * T1 * 2=3KB.Because data source 2 and 3 buffer zone are non-ping-pong buffer and need not be used to produce look-at-me,, avoid new data before reading, to be covered by follow-up data so its buffer size selection can be slightly larger than 2KB and 3KB to guarantee the continuity of data better.

Step 3: create each data buffer B1, B2, B3 writes the case pointer storage register.Wherein, data buffer B1 writes the value that the case pointer value equals the most significant digit of current write operation address A1W, and the case pointer value of writing of data buffer B2 and B3 just equals its current write operation address A2W and A3W.

Step 4: utilize the half-full or full up signal of table tennis data buffer B1 to produce look-at-me.Half-full or the full up signal of B1 buffer zone is obviously relevant with the value of its write operation address, and the data width of supposing the B1 buffer zone is 1 byte and storage depth is 1KB, and then the address realm of B1 buffer zone write operation address A1W is 0 to 1023.Obviously, the B1 buffer zone is half-full when the write operation address is 511, and buffer zone is full up when the write operation address is 1023.All should produce an interruption pulse signal when B1 buffer zone is half-full or full up and issue host computer.In Fig. 1, by the interruption generating module according to the size of the write operation address A1W of B1 buffer zone whether equal 511 or 1023 produce pulsed look-at-me give the host computer processor.

Step 5: set up each data buffer B1 among host computer and the FPGA, B2, the bus interface module between B3, as shown in fig. 1.Bus interface module is used for reading clock C, read address A and reading to enable conversion of signals such as E for each data buffer and write reading clock C, read address A1R, A2R, A3R, AR and reading to enable E1 of case pointer storage register what contain from the read operation of host computer instruction; E2, signals such as E3 are to realize host computer reading smoothly readable data in these storage spaces.

Step 6: create the host computer interrupt service subroutine, its process flow diagram is as shown in Figure 2.In the moment of interrupting arriving, at first accomplish keeping the scene intact.Secondly, judge whether current system is just to have carried out electrification reset or other forms of replacement operation, if then carry out the historical initialization operation of writing the case pointer register, otherwise skip this initialization step.Then, system reads the current case pointer register value stored of writing among the FPGA earlier, again the history of preserving in the interrupt service subroutine is write the case pointer register value and backups in the temporary variable, uses in order to follow-up host computer read operation.Then, system update history is write the case pointer register value, also promptly, the current case pointer register result assignment of writing of the FPGA that has just read is write the case pointer register in order to interrupt use next time to history.Next; Host computer is write the scope that the case pointer register value calculates the read operation address A that produces this interruption according to the current case pointer register value of writing that reads in the preceding step with the history that backups in the temporary variable, carries out the read operation function according to this address realm then.After data read and finish, carry out and recover execute-in-place, interrupt service subroutine finishes to withdraw from, and waits for the arrival of next time interrupting.

Step 7: under the periodic interruptions signal triggering, host computer interrupt service subroutine described in the execution in step six repeatedly can be accomplished the real time continuous data transmission in many asynchronous datas source.

Claims (1)

1. the list based on FPGA interrupts Real-time Data Transfer Method, it is characterized in that comprising following concrete steps:

Step 1: select suitable interrupt cycle

According to each asynchronous data source 1,2 ... The read data speed R of the write data speed Wk of n and host computer utilizes not real time continuous data transmission conditions inequality W1+W2+...+Wn＜R under the obliterated data, the feasibility that at first affirmation system realizes; Under the attainable prerequisite of system; According to size and other restrictive conditions of FPGA hardware resource, select suitable T1 interrupt cycle, again because the total bytes of each data buffer is at least (W1+W2+...+Wn) * T1 * 2;

Step 2: create the data buffer

According to each asynchronous data source 1,2 ... The write data speed Wk of n and interrupt cycle T1, confirm that the buffer stores amount size in each asynchronous data source is Wk * T1 * 2, for setting up n data buffer zone in this n asynchronous data source; And confirm that some data buffers wherein are ping-pong buffer, and might as well suppose to select B1 is ping-pong buffer, its buffer zone is divided into bottom half B1L and B1H; Have half-full and full up indicator signal, other data buffer then gets final product for the general data buffer zone;

Step 3: that creates each data buffer writes the case pointer register

Create each data buffer write the case pointer register time, ping-pong buffer B1 wherein writes the value that the case pointer value is a current write operation address most significant digit, its value possibly be 0 or 1, and the case pointer of writing of other data buffers is current write operation address value;

Step 4: produce the periodic interruptions signal

Half-full and the full up signal of buffer zone that produces according to the write operation of ping-pong buffer B1 produces and the corresponding periodic interruptions signal of host computer; This look-at-me is sent to host computer can trigger interrupt service subroutine, reads each data buffer data manipulation among the FPGA thereby accomplish;

Step 5: set up each data buffer B1 among host computer and the FPGA, B2 ..., the EBI between the Bn;

With comprise in the read operation of the host computer instruction read clock C, read operation address A and read enable signal convert reading clock C, reading to enable E1 of each data buffer into; E2 ..., En with read address A1R; A2R;, AnR signal and each buffer zone write the case pointer register read address signal AR, to read the data in the above-mentioned storage space;

Step 6: create the host computer interrupt service subroutine

The host computer interrupt service subroutine course of work is following: after the host computer interrupt service subroutine receives hardware interrupt; Do earlier and whether want initialized judgement: if system is firm electrification reset or other forms reset after; Then the historical write pointer register value with each buffer zone write address of FPGA and host computer is initialized as its corresponding start address; Otherwise skip this initialization step; Read the current case pointer register value of writing of each data buffer then; And when preserving last the interruption in the host computer procedure each data buffer of storage write the case pointer register value; Might as well be called history and write the case pointer register value, the data that read each data buffer appropriate address section among the FPGA are accomplished in the interim backup that interrupt service subroutine utilizes the current history of writing case pointer and host computer preservation to write case pointer then, and after history is write the backup of case pointer register value and before the host computer read operation; Write the case pointer register value to history and be updated to the current case pointer register value of writing; Can correctly read the data of each buffer zone appropriate address section when guaranteeing that interrupt next time, the host computer interrupt service subroutine is carried out the read operation back that finishes and is finished, and gets into and waits for next interruption status;

Step 7: host computer is interrupt service subroutine described in the recursive call step 6 under the triggering of periodic interruptions signal, can reach the real time continuous data transmission destination.

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