CN104076811B - Test device and method of simulation iic chip - Google Patents
Test device and method of simulation iic chip Download PDFInfo
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- CN104076811B CN104076811B CN201410259698.9A CN201410259698A CN104076811B CN 104076811 B CN104076811 B CN 104076811B CN 201410259698 A CN201410259698 A CN 201410259698A CN 104076811 B CN104076811 B CN 104076811B
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Abstract
The invention discloses a test device of a simulation iic chip. The test device of the simulation iic chip comprises a control unit, a communication unit, a configuration unit and an iic simulation response unit, wherein three communication ends of the control unit are connected with the communication unit, the configuration unit and the iic simulation response unit respectively, the iic simulation response unit is connected with an iic secondary interface unit, and the iic secondary interface unit carries out data communication with an iic main interface unit of equipment to be tested through an iic bus. The test device of the simulation iic chip can reduce interference of actual iic peripheral equipment devices, various iic peripheral equipment devices can be simulated through the equipment, and the efficiency of detecting whether the embedded equipment is normal or not is obviously improved.
Description
Technical field
The present invention relates to iic (inter-integrated circuit, IC bus) equipment technical field of measurement and test,
In particular to a kind of test equipment of simulation iic chip and method.
Background technology
Iic bus is applied quite varied, in order to verify that can embedded device correctly control iic in embedded systems
Ancillary equipment, in the research and development of embedded device, test, production phase, embedded device will enter for these iic ancillary equipment
Row test and checking.Current conventional method is by the iic interface of embedded device and corresponding various iic ancillary equipment
Iic interface is joined directly together and is detected, but iic type of peripheral device is a lot, is difficult to all be attached various iic ancillary equipment
Test, and which needs manual physical connection, detection efficiency is low.
Content of the invention
Present invention aim to providing a kind of test equipment of simulation iic chip and method, this equipment and method energy
Reduce the intervention of actual iic ancillary equipment device, various iic ancillary equipment devices just can be simulated hence it is evident that carrying by an equipment
The high whether normal efficiency of detection embedded device.
For realizing this purpose, the test equipment of the simulation iic chip designed by the present invention it is characterised in that: it includes controlling
Unit processed, communication unit, dispensing unit and iic analog response unit, wherein, control unit connection communication unit, configuration respectively
Unit and iic analog response unit, described iic analog response unit is connected with iic from interface unit, and described iic is from interface list
Row data communication can enter by the iic master interface unit of iic bus and equipment to be checked in unit.
A kind of test equipment using above-mentioned simulation iic chip to the method for testing equipment to be checked it is characterised in that
It comprises the steps:
Step 1: the test equipment electrifying startup of simulation iic chip, the test equipment of this simulation iic chip is with iic from setting
Standby mode works, and equipment to be checked is worked in the way of iic main equipment；
Step 2: the iic ancillary equipment that host computer is simulated as needed generates corresponding analog device configuration information, and will
Above-mentioned analog device configuration information is stored in dispensing unit by communication unit and by control unit；
Step 3: the analog device configuration information of dispensing unit memory storage is loaded into iic analog response unit by control unit
In, now iic analog response unit can simulate real iic ancillary equipment according to above-mentioned analog device configuration information；
Step 4: the iic peripheral type that equipment to be checked is simulated as required passes through iic bus to iic analog response list
Unit sends addressed command；
After step 5:iic analog response unit receives addressed command, with the analog device configuration in iic analog response unit
Device type address information in information is compared, such as the device type address in addressed command and analog device configuration information
Information match, then iic analog response unit to device replied to be checked confirm character, otherwise do not reply, now test process knot
Bundle；
Step 6: equipment to be checked passes through iic bus and sends operational order, iic analog response list to iic analog response unit
Unit determines the data content that aforesaid operations order is replied according to described analog device configuration information, and will reply the content of data
The bus frequency of the reply data determining by analog device configuration information gives equipment to be checked by iic bus transfer；
Step 7: equipment to be checked receives above-mentioned reply data and completes test process.
After the completion of above-mentioned steps 7, repeat step 4～step 7, complete the response of iic devices various to equipment to be checked
Test.
Beneficial effects of the present invention:
1st, the present invention passes through to import analog device configuration information in the test equipment of simulation iic chip so that iic chip
Test equipment can simulate various real simulation iic devices, it is to avoid in exploitation and test, connected using real devices.Logical
Cross the iic ancillary equipment corresponding analog device configuration information of generation that host computer can be simulated as needed, reach simulation multiple
The purpose of types of devices.
2nd, the present invention can reduce the intervention of practical devices, is independent of specific device physicses, by accessing simulation iic periphery
The test equipment of equipment, reaches the demand meeting exploitation and stress test.Sometimes the particular type of iic ancillary equipment cannot obtained
Number, only analog device configuration information when, this equipment also alternative meet require.
3rd, the test equipment itself of the simulation iic chip of the present invention is independently-powered, does not have real devices will consider when accessing
Chip operating voltage problem.
Brief description
Structural representation when Fig. 1 uses for the present invention；
Wherein, 1 control unit, 2 communication units, 3 dispensing units, 4 iic analog response units, 5 iic from
Interface unit, 6 equipment to be checked, 7 iic master interface units, 8 iic buses, 9 host computers.
Specific embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail:
A kind of test equipment of simulation iic chip as shown in Figure 1, it includes control unit 1, communication unit 2, configuration list
First 3 and iic analog response units 4, wherein, control unit 1 connection communication unit 2, dispensing unit 3 and iic analog response respectively
Unit 4, described iic analog response unit 4 is connected with iic from interface unit 5, and described iic can be total by iic from interface unit 5
Line 8 and equipment to be checked 6 (equipment 6 to be checked is embedded device, has the function of iic main equipment, externally pass through iic bus and iic from
Equipment be connected) iic master interface unit 7 enter row data communication.Described communication unit 2 is used for realizing host computer 9 and control unit 1
Between data communication.
In technique scheme, iic analog response unit 4 is used for simulating iic ancillary equipment, passes through iic to equipment 6 to be checked
The iic protocol package that bus 8 sends is responded.Iic analog response unit 4 is a fpga (field-programmable
Gate array, field programmable gate array), iic analog response unit 4 receives simulator from host computer 9 by communication unit 2
It is stored in after part configuration information in local dispensing unit 3, using the default configuration starting as next time, pass through data/address bus simultaneously
By config update to iic analog response unit 4.
The iic protocol package that iic analog response unit 4 sends to equipment 6 to be checked is analyzed, and is configured according to analog device
Information is responded to it.Iic analog response unit 4 is realized using field programmable gate array, to guarantee multipath concurrence execution.
Iic analog response unit 4 is sampled to clock bus, determines clock frequency according to clock bus sampled value, and takes out according to this
Data in bidirectional data line, and bus frequency reply content being determined according to analog device configuration information and replying data.
A kind of method to testing equipment to be checked for test equipment using above-mentioned simulation iic chip, it includes as follows
Step:
Step 1: the test equipment electrifying startup of simulation iic chip, the test equipment of this simulation iic chip is with iic from setting
Standby mode works, and equipment 6 to be checked is worked in the way of iic main equipment；
Step 2: the iic ancillary equipment that host computer 9 is simulated as needed generates corresponding analog device configuration information, and will
Above-mentioned analog device configuration information passes through communication unit 2 and is stored in dispensing unit 3 by control unit 1；
Step 3: the analog device configuration information of dispensing unit 3 memory storage is loaded into iic analog response list by control unit 1
In unit 4, now iic analog response unit 4 can simulate real iic ancillary equipment according to above-mentioned analog device configuration information；
Step 4: the iic peripheral type that equipment 6 to be checked is simulated as required passes through iic bus 8 to iic analog response
Unit 4 sends addressed command；
After step 5:iic analog response unit 4 receives addressed command, join with the analog device in iic analog response unit 4
Device type address information in confidence breath is compared, such as device type in addressed command and analog device configuration information
Location information match, then iic analog response unit 4 to equipment 6 to be checked reply confirm character, otherwise do not reply, now tested
Journey terminates (now can not save the resource of system to equipment 6 return information to be checked)；
Step 6: equipment 6 to be checked passes through iic bus 8 and sends operational order, iic analog response to iic analog response unit 4
Unit 4 determines the data content that aforesaid operations order is replied according to described analog device configuration information, and will reply data
The bus frequency of the reply data that content is determined by analog device configuration information is transferred to equipment 6 to be checked by iic bus 8；
Step 7: equipment 6 to be checked receives above-mentioned reply data and completes test process.
In technique scheme, analog device configuration information includes device type address information, bus frequency information and seeks
Location address information.
After the completion of above-mentioned steps 7, repeat step 4～step 7, complete the response of iic devices various to equipment to be checked
Test.
The content that this specification is not described in detail belongs to prior art known to professional and technical personnel in the field.
Claims (4)
1. a kind of test equipment of simulation iic chip it is characterised in that: it include control unit (1), communication unit (2), configuration
Unit (3) and iic analog response unit (4), wherein, control unit (1) respectively connection communication unit (2), dispensing unit (3) and
Iic analog response unit (4), described iic analog response unit (4) is connected with iic from interface unit (5), and described iic is from interface
Unit (5) can enter row data communication by the iic master interface unit (7) of iic bus (8) and equipment (6) to be checked；
The test equipment of described simulation iic chip works in the way of iic is from equipment, and equipment (6) to be checked is with the side of iic main equipment
Formula works；
The iic protocol package that described iic analog response unit (4) sends to described equipment (6) to be checked is responded.
2. simulation iic chip according to claim 1 test equipment it is characterised in that: described communication unit (2) is used for
Realize the data communication between host computer (9) and control unit (1)；
Described host computer (9) is used for sending analog device by described control unit (1) to described iic analog response unit (4)
Configuration information, described iic analog response unit (4) sends to described equipment (6) to be checked according to described analog device configuration information
Iic protocol package responded.
3. a kind of method to testing equipment to be checked for the test equipment of simulation iic chip described in utilization claim 2, it is special
Levy and be, it comprises the steps:
Step 1: the test equipment electrifying startup of simulation iic chip, the test equipment of this simulation iic chip is with iic from equipment
Mode works, and equipment (6) to be checked is worked in the way of iic main equipment；
Step 2: the iic ancillary equipment that host computer (9) is simulated as needed generates corresponding analog device configuration information, and will be upper
State analog device configuration information to pass through communication unit (2) and stored in dispensing unit (3) by control unit (1)；
Step 3: the analog device configuration information of dispensing unit (3) memory storage is loaded into iic analog response list by control unit (1)
In first (4), now iic analog response unit (4) can be simulated real iic periphery according to above-mentioned analog device configuration information and be set
Standby；
Step 4: the iic peripheral type that equipment (6) to be checked is simulated as required passes through iic bus (8) to iic analog response
Unit (4) sends addressed command；
After step 5:iic analog response unit (4) receives addressed command, join with the analog device in iic analog response unit (4)
Device type address information in confidence breath is compared, such as device type in addressed command and analog device configuration information
Location information match, then iic analog response unit (4) to equipment to be checked (6) reply confirm character, otherwise do not reply, now survey
Examination process terminates；
Step 6: equipment (6) to be checked is passed through iic bus (8) and sent operational order to iic analog response unit (4), and iic simulation rings
Answer unit (4) to determine, according to described analog device configuration information, the data content that aforesaid operations order is replied, and number will be replied
According to the bus frequency of reply data that determines by analog device configuration information of content to be checked setting is transferred to by iic bus (8)
Standby (6)；
Step 7: equipment (6) to be checked receives above-mentioned reply data and complete test process.
4. method of testing according to claim 3 it is characterised in that: after the completion of above-mentioned steps 7, repeat step 4～
Step 7, completes the response test of iic devices various to equipment to be checked.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410259698.9A CN104076811B (en) | 2014-06-12 | 2014-06-12 | Test device and method of simulation iic chip |
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| CN201410259698.9A CN104076811B (en) | 2014-06-12 | 2014-06-12 | Test device and method of simulation iic chip |
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| CN104076811A CN104076811A (en) | 2014-10-01 |
| CN104076811B true CN104076811B (en) | 2017-01-25 |
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| CN114048520B (en) * | 2022-01-11 | 2022-04-08 | 沐曦集成电路(上海)有限公司 | Detection system for cross-chip access control |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101158708A (en) * | 2007-10-23 | 2008-04-09 | 无锡汉柏信息技术有限公司 | Multiple chips automatic test method based on programmable logic device |
| CN101398467A (en) * | 2007-09-26 | 2009-04-01 | 鸿富锦精密工业（深圳）有限公司 | Internal integrate circuit bus interface test system and method |
| CN201876522U (en) * | 2009-12-31 | 2011-06-22 | 杭州士兰微电子股份有限公司 | General test equipment |
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2014
- 2014-06-12 CN CN201410259698.9A patent/CN104076811B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101398467A (en) * | 2007-09-26 | 2009-04-01 | 鸿富锦精密工业（深圳）有限公司 | Internal integrate circuit bus interface test system and method |
| CN101158708A (en) * | 2007-10-23 | 2008-04-09 | 无锡汉柏信息技术有限公司 | Multiple chips automatic test method based on programmable logic device |
| CN201876522U (en) * | 2009-12-31 | 2011-06-22 | 杭州士兰微电子股份有限公司 | General test equipment |
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Address after: Hubei Province, Wuhan City, South Lake Road 430070 Hongshan District No. 53 WCMC agricultural city shop floor 4 Patentee after: Wuhan fine test electronics group Limited by Share Ltd Address before: Hubei Province, Wuhan City, South Lake Road 430070 Hongshan District No. 53 WCMC agricultural city shop floor 4 Patentee before: Wuhan Jingce Electronic Technology Co., Ltd. |