CN109585302A - A kind of process improving VDMOS product E AS ability - Google Patents
A kind of process improving VDMOS product E AS ability Download PDFInfo
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- CN109585302A CN109585302A CN201910042248.7A CN201910042248A CN109585302A CN 109585302 A CN109585302 A CN 109585302A CN 201910042248 A CN201910042248 A CN 201910042248A CN 109585302 A CN109585302 A CN 109585302A
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 230000008569 process Effects 0.000 title claims abstract description 16
- 238000001259 photo etching Methods 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 238000000137 annealing Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 6
- 239000003292 glue Substances 0.000 claims abstract description 5
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 4
- 239000000956 alloy Substances 0.000 claims abstract description 4
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 claims abstract description 4
- 230000008020 evaporation Effects 0.000 claims abstract description 4
- 238000001704 evaporation Methods 0.000 claims abstract description 4
- 238000004544 sputter deposition Methods 0.000 claims abstract description 4
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000010992 reflux Methods 0.000 claims description 3
- 238000006735 epoxidation reaction Methods 0.000 claims description 2
- 238000007363 ring formation reaction Methods 0.000 claims description 2
- 238000006386 neutralization reaction Methods 0.000 claims 1
- 239000013049 sediment Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 230000001413 cellular effect Effects 0.000 description 4
- 230000006872 improvement Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of processes for improving VDMOS product E AS ability, comprising the following steps: potential dividing ring is formed；Active area is opened；Polysilicon gate reticle first time uses, and carries out enriching P-BODY band glue and injects, remove photoresist simultaneously high annealing later；Surface low dose AS+ injects comprehensively, and the partially dense impurity in the surface P-BODY is suitably neutralized part, guarantees not because generating influence bigger than normal to VTH after P-BODY enriching；Gate oxide growth, polycrystalline silicon deposit, polysilicon doping, polycrystalline photoetching, polycrystal etching；Source region is formed；Fairlead is formed；It includes the sputtering of front side aluminum silicon, front metal photoetching, front metal etching and alloy annealing that front metal, which is formed,；Thinning back side, the evaporation of back side multiple layer metal.A kind of process improving VDMOS product E AS ability provided by the invention improves the purpose of EAS ability, is skillfully constructed, is novel and without destroying normal VDMOS structure and principle, practical.
Description
Technical field
The present invention relates to semiconductor components and devices technical fields, and in particular to a kind of technique for improving VDMOS product E AS ability
Method.
Background technique
The method for improving VDMOS product E AS ability at present is mainly designed using reasonable laying out pattern, preferable cellular
And the epitaxial material of optimization in place, but these methods only optimize improvement on outer foxing part, to influence EAS ability
Internal factor is unable to get improvement, because there is the parasitic NPN pipe that can not change inside cellular, as shown in FIG. 1, FIG. 1 is cellulars
Structural schematic diagram forms endophyte NPN by the area N+ (E) and the area P-BODY (B) and the drift region N- (C) three inside cellular
Pipe, although the maturation domain area Hui Ba N+ and p type island region when fairlead is routed carries out short circuit processing at present, VDMOS is not theoretically
Have second breakdown characteristic, but in snap switch state transformation inside still have electric current and flow through p-type base area below N+, if
Flow through BE knot positive cut-in voltage threshold values (general feelings of the forward voltage drop beyond parasitic NPN pipe that the transverse current of p-type base area generates
It is 0.6V under condition), then the unlatching of parasitic NPN pipe can occur, internal breakdown voltage can be quickly fallen to BVCEO by BVCBO at this time, and
BVCEO generally only has 60% or so of BVCBO, to generate second breakdown, once second breakdown occurs, device can fail, after
Fruit is very serious, so how to prevent the unlatching of parasitic NPN pipe is that technique must solve the problems, such as.Conventional VDMOS product process flow
It is all using first gate oxide growth, polycrystalline deposition, polycrystalline doping, then polycrystalline photoetching, polycrystal etching is P- using polysilicon gate
BODY implant blocking layer, high annealing, the later source N+ photoetching, a series of fixed process operations such as N+ injection.
From Principles of Transistors it is found that being opened to parasitic NPN pipe does not occur, it is necessary to which accomplish to give several points: (1) N+ width is set
Count the smaller the better, the more shallow N+ junction depth the better, certainly can not be too shallow too light, it is necessary to it is good to can guarantee that the area N+ front metal is formed
Ohmic contact；(2) the deeper p-type base area longitudinal the better, and resistance value is the smaller the better, and under the premise of not influencing VTH, it is generally desirable to P-
The injection of BODY implanted dopant is as more as possible, and junction depth reaches design requirement as far as possible.
Summary of the invention
(1) the technical issues of solving
The present invention provides a kind of process for improving VDMOS product E AS ability, solves existing raising VDMOS product
The method of EAS ability is unable to get improvement to the internal factor for influencing EAS ability, and parasitic NPN pipe is opened in VDMOS product use
The problem of causing second breakdown.
(2) technical solution
In order to solve the above technical problems, the invention provides the following technical scheme: a kind of improve VDMOS product E AS ability
Process, comprising the following steps:
Step 1: potential dividing ring is formed, and the potential dividing ring formation includes: an oxide growth, potential dividing ring photoetching, potential dividing ring burn into point
Pressure ring injection, partial pressure epoxidation and potential dividing ring annealing；
Step 2: active area is opened, including active area photoetching, active area corrosion and the thin oxide growth of active area；
Step 3: carrying out JFET injection and annealing；
Step 4: polysilicon gate reticle uses for the first time, carries out enriching P-BODY band glue and injects, removes photoresist later and high temperature moves back
Fire；
Step 5: surface low dose AS+ injects comprehensively, and the partially dense p type impurity of channel surface is carried out appropriateness with N-type impurity
It neutralizes, guarantees not because generating influence bigger than normal to VTH size after P-BODY injection enriching；
Step 6: gate oxide growth, polycrystalline silicon deposit, polysilicon doping, polycrystalline photoetching, polycrystal etching；
Step 7: source region is formed, including source region N+ photoetching, source region N+ are injected, source region N+ anneals, shallow P+ injects comprehensively, TEOS
Film deposit, bpsg film deposit and reflux；
Step 8: fairlead is formed, including fairlead photoetching and fairlead etching；
Step 9: front metal is formed, including the sputtering of front side aluminum silicon, front metal photoetching, front metal etching and alloy move back
Fire；
Step 10: thinning back side processing, the evaporation of back side multiple layer metal.
(3) beneficial effect
Compared to conventional VDMOS product process flow, the process provided by the invention for improving VDMOS product E AS ability
P-BODY implantation dosage can be increased substantially, it is specific as follows: after active area is opened, first to grow oxide layer, then use polycrystalline
The photoresist of gate figure carries out band glue P-BODY enriching and injects, and P-BODY high annealing is carried out after removing photoresist, increases by a step table later
The partially dense P-BODY impurity of channel surface is neutralized a part, guarantees subsequent normal VTH by the injection of face low dose AS+ impurity
Required surface P channel impurity concentration, but the square of entire P-BODY is much smaller compared to normal process, parasitic NPN pipe
The difficulty of unlatching increases, and effectively improves EAS ability, carries out normal gate oxide growth, polycrystalline deposition again later, and polycrystalline is mixed
Miscellaneous, polysilicon gate chemical wet etching machined certainly since P-BODY is injected with annealing, in advance so can directly carry out the photoetching of the source N+
Be filled with, follow-up process with normal the same, it is no additionally increase reticle under the premise of, only making polysilicon gate reticle more
With once, process conditions are just had activated significantly, to achieve the purpose that improve EAS ability, are skillfully constructed, are novel and no broken
Bad normal VDMOS structure and principle, it is practical.
Detailed description of the invention
Fig. 1 is structure cell schematic diagram.
Specific embodiment
Below in conjunction with the embodiment of the present invention, technical scheme in the embodiment of the invention is clearly and completely described,
Obviously, described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based in the present invention
Embodiment, every other embodiment obtained by those of ordinary skill in the art without making creative efforts, all
Belong to the scope of protection of the invention.
A kind of process improving VDMOS product E AS ability provided by the invention, steps are as follows:
Step 1: forming potential dividing ring, including field oxide growth, potential dividing ring photoetching, the injection of potential dividing ring burn into potential dividing ring, potential dividing ring
Oxidation and potential dividing ring annealing；
Step 2: active area is opened, including active area photoetching, active area corrosion and the thin oxide growth of active area；
Step 3: carrying out JFET injection and annealing；
Step 4: polysilicon gate reticle uses for the first time, carries out enriching P-BODY band glue and injects, removes photoresist later and high temperature moves back
Fire；
Step 5: surface low dose AS+ injects comprehensively, and the partially dense p type impurity of channel surface is carried out appropriateness with N-type impurity
It neutralizes, guarantees not because generating influence bigger than normal to VTH size after P-BODY enriching；
Step 6: gate oxide growth, polycrystalline silicon deposit, polysilicon doping, polycrystalline photoetching, polycrystal etching；
Step 7: forming source region, including source region N+ photoetching, source region N+ are injected, source region N+ anneals, shallow P+ injects comprehensively, TEOS
Film deposit, bpsg film deposit and reflux；
Step 8: forming fairlead, including fairlead photoetching and fairlead etching；
Step 9: forming front metal, including the sputtering of front side aluminum silicon, front metal photoetching, front metal etching and alloy move back
Fire；
Step 10: thinning back side processing, the evaporation of back side multiple layer metal.
It is illustrated with a 4N60 conventional products, normal process processing, EAS current capacity only has 4A or so, using the present invention
After the method for offer, EAS current capacity can be improved 30% or more up to 6A or so, the same product, EAS ability, improve width
Degree is obvious；Certainly the present invention also can be used for IGBT device, improve LATCH-UP.Raising VDMOS product E AS energy provided by the invention
The process of power is skillfully constructed, novel and without destroying normal VDMOS structure and principle, practical.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
A variety of variations, modification, replacement can be carried out to these embodiments without departing from the principles and spirit of the present invention by understanding
And modification, the scope of the present invention is defined by the appended.
Claims (1)
1. a kind of process for improving VDMOS product E AS ability, which comprises the following steps:
Step 1: potential dividing ring is formed, and the potential dividing ring formation includes: an oxide growth, potential dividing ring photoetching, potential dividing ring burn into potential dividing ring
Injection, partial pressure epoxidation and potential dividing ring annealing；
Step 2: active area is opened, including active area photoetching, active area corrosion and the thin oxide growth of active area；
Step 3: carrying out JFET injection and annealing；
Step 4: polysilicon gate reticle first time uses, and carries out enriching P-BODY band glue and injects, remove photoresist simultaneously high annealing later；
Step 5: surface low dose AS+ injects comprehensively, and the partially dense p type impurity of channel surface is carried out appropriate neutralization with N-type impurity,
Guarantee not because generating influence bigger than normal to VTH size after P-BODY injection enriching；
Step 6: gate oxide growth, polycrystalline silicon deposit, polysilicon doping, polycrystalline photoetching, polycrystal etching；
Step 7: source region is formed, including source region N+ photoetching, source region N+ are injected, source region N+ annealing, shallow P+ injects comprehensively, TEOS film forms sediment
Product, bpsg film deposit and reflux；
Step 8: fairlead is formed, including fairlead photoetching and fairlead etching；
Step 9: it includes the sputtering of front side aluminum silicon, front metal photoetching, front metal etching and alloy annealing that front metal, which is formed,；
Step 10: thinning back side, the evaporation of back side multiple layer metal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910042248.7A CN109585302A (en) | 2019-01-17 | 2019-01-17 | A kind of process improving VDMOS product E AS ability |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910042248.7A CN109585302A (en) | 2019-01-17 | 2019-01-17 | A kind of process improving VDMOS product E AS ability |
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| CN109585302A true CN109585302A (en) | 2019-04-05 |
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|---|---|---|---|
| CN201910042248.7A Pending CN109585302A (en) | 2019-01-17 | 2019-01-17 | A kind of process improving VDMOS product E AS ability |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545908A (en) * | 1991-12-09 | 1996-08-13 | Nippondenso Co., Ltd. | Vertical type insulated-gate semiconductor device |
| US5973361A (en) * | 1996-03-06 | 1999-10-26 | Magepower Semiconductor Corporation | DMOS transistors with diffusion merged body regions manufactured with reduced number of masks and enhanced ruggedness |
| CN106098782A (en) * | 2016-08-19 | 2016-11-09 | 华越微电子有限公司 | A kind of P-channel VDMOS device production method |
| CN106531810A (en) * | 2016-12-23 | 2017-03-22 | 西安锴威半导体有限公司 | Discrete power mos field effect transistor and manufacturing method thereof |
-
2019
- 2019-01-17 CN CN201910042248.7A patent/CN109585302A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5545908A (en) * | 1991-12-09 | 1996-08-13 | Nippondenso Co., Ltd. | Vertical type insulated-gate semiconductor device |
| US5973361A (en) * | 1996-03-06 | 1999-10-26 | Magepower Semiconductor Corporation | DMOS transistors with diffusion merged body regions manufactured with reduced number of masks and enhanced ruggedness |
| CN106098782A (en) * | 2016-08-19 | 2016-11-09 | 华越微电子有限公司 | A kind of P-channel VDMOS device production method |
| CN106531810A (en) * | 2016-12-23 | 2017-03-22 | 西安锴威半导体有限公司 | Discrete power mos field effect transistor and manufacturing method thereof |
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