CN106098782A - A kind of P-channel VDMOS device production method - Google Patents
A kind of P-channel VDMOS device production method Download PDFInfo
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- CN106098782A CN106098782A CN201610693325.1A CN201610693325A CN106098782A CN 106098782 A CN106098782 A CN 106098782A CN 201610693325 A CN201610693325 A CN 201610693325A CN 106098782 A CN106098782 A CN 106098782A
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- oxide layer
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- vdmos device
- epitaxial layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 229910052796 boron Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000003292 glue Substances 0.000 claims abstract description 6
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 230000006641 stabilisation Effects 0.000 abstract description 4
- 238000011105 stabilization Methods 0.000 abstract description 4
- 238000002513 implantation Methods 0.000 abstract 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 13
- 229910052760 oxygen Inorganic materials 0.000 description 13
- 239000001301 oxygen Substances 0.000 description 13
- 238000000034 method Methods 0.000 description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000013049 sediment Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The open a kind of P-channel VDMOS device production method of the present invention, is included on epitaxial layer generation oxide layer, covers photoresist layer, then band glue N-type impurity implantation step in oxide layer；Required N-type base junction depth step is formed at epitaxial layer upper surface after high annealing；Oxide layer carries out boron impurity implantation step；Epitaxial layer generates grid oxide layer, on grid oxide layer, then carries out polysilicon deposit and doping, and form polycrystalline silicon grid layer step again with polysilicon gate reticle；Regional area at grid oxide layer covers photoresist, the most directly carries out source P+ processing, forms P+ district step in N-type base；And metal dielectric layer in finally deposit, the upper and lower surface at epitaxial layer is respectively provided with metal level and forms the VDMOS device step of standard simultaneously.Above-mentioned P-channel VDMOS device production method, can realize the Vth value stabilization of P-channel VDMOS device between 2 ~ 4V, have high stability and reasonability.
Description
Technical field
The present invention relates to a kind of P-channel VDMOS device production method, belong to semiconductor production field.
Background technology
At present, the production technology of P-channel VDMOS device is the most consistent with N-channel VDMOS device, specific as follows:
The VTH forming process of N-type VDMOS device, after gate oxide growth and polysilicon gate have etched, by polysilicon gate autoregistration
Technique first injects the p type impurity of doses, then high annealing, forms the p-type base of certain junction depth, then again with many
Brilliant grid self-registered technology carries out source N+ heavy dose and injects and anneal, and so, laterally expands the secondary of p-type base with N+ source region
The difference formation raceway groove that eliminating stagnation is deep, final VTH size determines with the maximum compensated impurity concentration in gate oxide thickness and raceway groove, maximum
Compensate concentration and be normally in p-type base the place near p-type base N+ knot.For N-type VDMOS, gate oxide thickness
After Gu Ding, as long as adjusting p type impurity dosage just can easily modulate required VTH value, the VTH mono-of current N-type VDMOS
As control between 2 ~ 4V, central value require at 3.0V, N-type VDMOS product can meet, it appears that the realization of this parameter is not
One very difficult thing, but same flow process is used in p-type VDMOS technique, and result is the most undesirable, contrasts, p-type from surface
VDMOS has simply changed N-type impurity into base, and source region has been changed into P+ by N+, domain and structure all with N-type VDMOS as.
Using the base implanted dopant (phosphorus and boron) of same dose, identical base annealing time, gate oxide thickness is the most identical, domain also
Sample, the most corresponding dopant type converts, and the result drawn differs greatly, and for N-channel VDMOS, its VTH only has 4V,
And P-channel VDMOS, its VTH have reached 12V, differ nearly three times of relations, use the P-channel that current conventional flowsheet produces
VDMOS device Vth main cause bigger than normal is as follows:
A: high-temperature heat treatment process causes heavily doped phosphorus impurities in polysilicon easily to cross grid oxygen arrival channel surface, causes similar
Impurities accumulation, directly results in Vth bigger than normal；
B: oxide charge affects, and especially after grid oxygen, pyroprocess can cause positive oxide charge to accumulate, and positive oxidation
Electric charge can cause the Vth of P-channel VDMOS to become big；
The diffusion coefficient of C: two kinds of base impurities there are differences and causes, and the base of N-channel VDMOS is boron impurity, boron impurity due to
Atomic is little, therefore diffusion coefficient is big, and under same temperature and time, impurity is easily to laterally and longitudinally moving, so,
Impurity would not be at surface sediment, and the base of P-channel VDMOS is phosphorus impurities, and the atomic of phosphorus impurities is relatively big, therefore diffusion system
Number is little, and compared with boron impurity, same temperature and time knot, impurity is more easy at surface sediment, thus causes the concentration on surface
Too high, this is also the key factor that P-channel VDMOS VTH is higher.
In view of this, this is studied by the present inventor, develops a kind of P-channel VDMOS device production method specially, this
Case thus produces.
Summary of the invention
It is an object of the invention to provide a kind of P-channel VDMOS device production method, it is possible to use the most ready-made N-channel
VDMOS device domain is developed and flowing water, it is achieved the Vth value stabilization of P-channel VDMOS device, between 2 ~ 4V, has high
Stability and reasonability.
To achieve these goals, the solution of the present invention is:
A kind of P-channel VDMOS device production method, comprises the steps:
After step 1), epitaxial layer active area are opened, carry out thin oxide growth, generate oxide layer, oxide layer covers photoresist again
Layer, and require to remove photoresist in local according to design, then use polysilicon gate reticle to carry out band glue N-type impurity and inject；
Step 2), remove remaining photoresist on removing oxide layer, form required N-type base at epitaxial layer upper surface after high annealing
District's junction depth；
Step 3), in oxide layer, carry out boron impurity injection, between N-type base junction depth, form JFET district, the injection one of boron impurity
Aspect reduces the VTH value that the surface concentration of N-type base requires with satisfied design, on the other hand improves the doping content in JFET district,
Reduce JFET resistance；
Step 4), rinse oxide layer, epitaxial layer carries out normal gate oxide growth, generate grid oxide layer, then at grid oxide layer
On carry out polysilicon deposit with doping, and again with polysilicon gate reticle formed polycrystalline silicon grid layer, required for N-type base
High temperature knot would have been completed before grid oxygen, so being no longer needed for high-temperature process after grid oxygen,
Step 5), grid oxide layer regional area cover photoresist, the most directly carry out source P+ processing, in N-type base formed P
+ district, border when P+ region, source is injected is polysilicon, and another side defines P+ source and the short of N-type base with photoresist
Point；
In step 6), finally deposit, metal dielectric layer covers polysilicon gate and thicker PSG/BPSG film and carries out at backflow
Reason, the upper and lower surface at epitaxial layer is respectively provided with metal level simultaneously, as source electrode and drain electrode, forms the VDMOS of standard
Device.
P-channel VDMOS device production method of the present invention, it is possible to achieve the Vth value stabilization of P-channel VDMOS device
Between 2 ~ 4V.There is following several advantage:
1) before, the annealing of high temperature base being placed on gate oxide growth, it is to avoid the high annealing after N-type VDMOS technique grid oxygen, this
Sample one, does not has pyroprocess after adulterating due to grid oxygen polycrystalline, does not worries that the heavy doping N+ in polysilicon gate can go under grid oxygen
Silicon face (epitaxial layer) on, additionally there is no high-temperature heat treatment after grid oxygen, reduce oxide layer positive charge, it is to avoid VTH is born
Face rings；
2) production method of the present invention almost avoids the negative effect that all meetings are bigger than normal to VTH, although more than once light
It is carved into this, but performance is improved significantly；
3) although middle base injects does not uses conventional polysilicon gate self-registered technology, but due to current stepper
Extensive application, front and back secondary deviation of the alignment is within 0.2um, in fact band glue inject with polysilicon gate autoregistration injection effect several
Consistent, do not worry affecting structure cell.
Below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.
Accompanying drawing explanation
Fig. 1 be the present embodiment step 1) after P-channel VDMOS device structural representation；
Fig. 2 is the step 2 of the present embodiment) P-channel VDMOS device structural representation afterwards；
Fig. 3 be the present embodiment step 3) after P-channel VDMOS device structural representation；
Fig. 4 be the present embodiment step 4) after P-channel VDMOS device structural representation；
Fig. 5 be the present embodiment step 5) after P-channel VDMOS device structural representation；
Fig. 6 be the present embodiment step 6) after P-channel VDMOS device structural representation.
Detailed description of the invention
A kind of P-channel VDMOS device production method, comprises the steps:
After step 1), epitaxial layer 1 active area are opened, first carry out thin oxide growth, generate oxide layer 2, oxide layer 2 covers light again
Photoresist layer 3, and require to remove photoresist in local according to design, then use polysilicon gate reticle to carry out band glue N-type impurity (ph+) and inject,
As shown in Figure 1；
Step 2), remove remaining photoresist on removing oxide layer 2, form required N-type at epitaxial layer 1 upper surface after high annealing
Base junction depth, as shown in Figure 2；
Step 3), oxide layer 2 carries out the comprehensively low dose of of boron impurity (B+) inject, between N-type base junction depth, form JFET
District, as it is shown on figure 3, on the one hand the most low dose of injection of boron impurity reduce the surface concentration of N-type base with satisfied setting requirement
VTH value, on the other hand improve the doping content in JFET district between N-type base, reduce JFET resistance；
Step 4), rinse oxide layer 2, epitaxial layer 1 carries out normal gate oxide growth, generate grid oxide layer 4, then at grid oxygen
Polysilicon deposit and doping is carried out on layer 4, and again with polysilicon gate reticle formation polycrystalline silicon grid layer 5, as shown in Figure 4, by
High temperature knot required for N-type base would have been completed before grid oxygen, so being no longer needed for high-temperature process after grid oxygen.
Before the annealing of high temperature base has been placed on gate oxide growth, it is to avoid the high annealing after N-type VDMOS technique grid oxygen, so, by
After grid oxygen polycrystalline adulterates, there is no pyroprocess, do not worry that the heavy doping N+ in polysilicon gate can go to the silicon table under grid oxide layer 4
On face (epitaxial layer 1), additionally there is no high-temperature heat treatment after grid oxygen, reduce grid oxide layer 4 positive charge, it is to avoid negative to VTH value
Impact；
Step 5), grid oxide layer 4 regional area cover photoresist 6, the most directly carry out source P+ processing, shape in N-type base
Becoming P+ district, as it is shown in figure 5, border when P+ region, source is injected is polysilicon, another side defines P+ source and N-type with photoresist
The short-circuiting percentage of base；
In step 6), finally deposit, metal dielectric layer 7 covers polycrystalline silicon grid layer 5 and thicker PSG/BPSG film (interior metal
Insulating barrier 7) and carry out reflow treatment, the upper and lower surface at epitaxial layer is respectively provided with metal level 8 simultaneously, as source electrode and
Drain electrode, forms the VDMOS device of standard.
Applicant uses existing N-type VDMOS device 30N60 reticle to carry out p-type VDMOS device 10P60 flowing water, passes through
Production method described in the present embodiment, a flowing water success, VTH controls within requiring, data are as shown in table 1:
Table 1:
VTH design is worth 2.5V centered by requiring, actual flowing water result fully meets！Additionally from RDON data it has also been discovered that, just
Often the RDON of 30N60 is about 35 milliohms, and as p-type product 60V flowing water, its RDON, about 100 milliohms, is similar N-type
Three times of product, comply fully with theory.
Use the P-channel VDMOS device production method described in the present embodiment, it is possible to achieve the Vth of P-channel VDMOS device
Value stabilization is between 2 ~ 4V.Although base injects does not uses conventional polysilicon gate self-registered technology, but due to current stepping
The extensive application of formula litho machine, front and back secondary deviation of the alignment is within 0.2um, and in fact band glue injects and notes with polysilicon gate autoregistration
Enter effect almost consistent, do not worry affecting structure cell.It is right that production method of the present invention almost avoids all meetings
The negative effect that VTH is bigger than normal, although more than once photoetching cost, but performance is improved significantly.
Above-described embodiment and the product form of the graphic and non-limiting present invention and style, any art common
Technical staff is suitably changed what it did or modifies, and all should be regarded as the patent category without departing from the present invention.
Claims (1)
1. a P-channel VDMOS device production method, it is characterised in that comprise the steps:
After step 1), epitaxial layer active area are opened, carry out thin oxide growth, generate oxide layer, oxide layer covers photoresist again
Layer, and require to remove photoresist in local according to design, then use polysilicon gate reticle to carry out band glue N-type impurity and inject；
Step 2), remove remaining photoresist on removing oxide layer, form required N-type base at epitaxial layer upper surface after high annealing
District's junction depth；
Step 3), in oxide layer, carry out boron impurity injection, between N-type base junction depth, form JFET district；
Step 4), rinse oxide layer, epitaxial layer carries out normal gate oxide growth, generate grid oxide layer, then at grid oxide layer
On carry out polysilicon deposit with doping, and again with polysilicon gate reticle formed polycrystalline silicon grid layer；
Step 5), grid oxide layer regional area cover photoresist, the most directly carry out source P+ processing, in N-type base formed P
+ district；
In step 6), finally deposit, metal dielectric layer covers polysilicon gate and thicker PSG/BPSG film and carries out at backflow
Reason, the upper and lower surface at epitaxial layer is respectively provided with metal level simultaneously, as source electrode and drain electrode, forms the VDMOS of standard
Device.
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| CN201610693325.1A CN106098782B (en) | 2016-08-19 | 2016-08-19 | A kind of P-channel VDMOS device production method |
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| CN201610693325.1A CN106098782B (en) | 2016-08-19 | 2016-08-19 | A kind of P-channel VDMOS device production method |
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| CN106098782A true CN106098782A (en) | 2016-11-09 |
| CN106098782B CN106098782B (en) | 2019-10-18 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783621A (en) * | 2016-12-13 | 2017-05-31 | 中国电子科技集团公司第四十七研究所 | A kind of manufacture method of VDMOS device |
| CN109585302A (en) * | 2019-01-17 | 2019-04-05 | 厦门中能微电子有限公司 | A kind of process improving VDMOS product E AS ability |
| CN111403272A (en) * | 2020-03-27 | 2020-07-10 | 中国电子科技集团公司第五十八研究所 | Process method for improving threshold voltage precision of radiation-resistant planar VDMOS |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000039858A2 (en) * | 1998-12-28 | 2000-07-06 | Fairchild Semiconductor Corporation | Metal gate double diffusion mosfet with improved switching speed and reduced gate tunnel leakage |
| KR100612072B1 (en) * | 2004-04-27 | 2006-08-14 | 이태복 | Semiconductor device of high breakdown voltage and manufacturing method thereof |
| US20130181280A1 (en) * | 2012-01-16 | 2013-07-18 | Microsemi Corporation | Pseudo self aligned radhard mosfet and process of manufacture |
-
2016
- 2016-08-19 CN CN201610693325.1A patent/CN106098782B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000039858A2 (en) * | 1998-12-28 | 2000-07-06 | Fairchild Semiconductor Corporation | Metal gate double diffusion mosfet with improved switching speed and reduced gate tunnel leakage |
| KR100612072B1 (en) * | 2004-04-27 | 2006-08-14 | 이태복 | Semiconductor device of high breakdown voltage and manufacturing method thereof |
| US20130181280A1 (en) * | 2012-01-16 | 2013-07-18 | Microsemi Corporation | Pseudo self aligned radhard mosfet and process of manufacture |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783621A (en) * | 2016-12-13 | 2017-05-31 | 中国电子科技集团公司第四十七研究所 | A kind of manufacture method of VDMOS device |
| CN109585302A (en) * | 2019-01-17 | 2019-04-05 | 厦门中能微电子有限公司 | A kind of process improving VDMOS product E AS ability |
| CN111403272A (en) * | 2020-03-27 | 2020-07-10 | 中国电子科技集团公司第五十八研究所 | Process method for improving threshold voltage precision of radiation-resistant planar VDMOS |
| CN111403272B (en) * | 2020-03-27 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Process method for improving threshold voltage precision of radiation-resistant planar VDMOS |
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