CN109585273A - 一种氧化嫁器件隔离区的制备方法 - Google Patents
一种氧化嫁器件隔离区的制备方法 Download PDFInfo
- Publication number
- CN109585273A CN109585273A CN201811450087.7A CN201811450087A CN109585273A CN 109585273 A CN109585273 A CN 109585273A CN 201811450087 A CN201811450087 A CN 201811450087A CN 109585273 A CN109585273 A CN 109585273A
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- Prior art keywords
- oxidation
- preparation
- transferred
- mask layer
- isolated area
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- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 238000002955 isolation Methods 0.000 title claims abstract description 22
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 69
- 230000003647 oxidation Effects 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims abstract description 39
- 238000005516 engineering process Methods 0.000 claims abstract description 16
- 238000000137 annealing Methods 0.000 claims description 9
- 238000011161 development Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 230000003628 erosive effect Effects 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000006378 damage Effects 0.000 abstract description 5
- 238000005530 etching Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 238000006701 autoxidation reaction Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
- H01L21/4757—After-treatment
- H01L21/47573—Etching the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/7605—Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Weting (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims (10)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811450087.7A CN109585273B (zh) | 2018-11-30 | 2018-11-30 | 一种氧化镓器件隔离区的制备方法 |
PCT/CN2018/121423 WO2020107544A1 (zh) | 2018-11-30 | 2018-12-17 | 一种氧化镓器件隔离区的制备方法 |
US17/036,126 US11244821B2 (en) | 2018-11-30 | 2020-09-29 | Method for preparing isolation area of gallium oxide device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811450087.7A CN109585273B (zh) | 2018-11-30 | 2018-11-30 | 一种氧化镓器件隔离区的制备方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109585273A true CN109585273A (zh) | 2019-04-05 |
CN109585273B CN109585273B (zh) | 2020-04-28 |
Family
ID=65924117
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811450087.7A Active CN109585273B (zh) | 2018-11-30 | 2018-11-30 | 一种氧化镓器件隔离区的制备方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US11244821B2 (zh) |
CN (1) | CN109585273B (zh) |
WO (1) | WO2020107544A1 (zh) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101207063A (zh) * | 2006-12-18 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | 浅沟槽隔离的形成方法 |
US20160042949A1 (en) * | 2014-08-06 | 2016-02-11 | Tamura Corporation | METHOD OF FORMING HIGH-RESISTIVITY REGION IN Ga2O3-BASED SINGLE CRYSTAL, AND CRYSTAL LAMINATE STRUCTURE AND SEMICONDUCTOR ELEMENT |
CN107464844A (zh) * | 2017-07-20 | 2017-12-12 | 中国电子科技集团公司第十三研究所 | 氧化镓场效应晶体管的制备方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6642128B1 (en) * | 2002-05-06 | 2003-11-04 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for high temperature oxidations to prevent oxide edge peeling |
US7005339B2 (en) * | 2003-12-15 | 2006-02-28 | United Microelectronics Corp. | Method of integrating high voltage metal oxide semiconductor devices and submicron metal oxide semiconductor devices |
US20060094171A1 (en) * | 2004-11-04 | 2006-05-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Isolation trench thermal annealing method for non-bulk silicon semiconductor substrate |
JP2007335573A (ja) * | 2006-06-14 | 2007-12-27 | Hitachi Ltd | 半導体装置およびその製造方法 |
US9209181B2 (en) * | 2013-06-14 | 2015-12-08 | Globalfoundries Inc. | Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures |
CN108615769A (zh) * | 2018-05-25 | 2018-10-02 | 中国电子科技集团公司第十三研究所 | 氧化镓mosfet器件的制备方法 |
-
2018
- 2018-11-30 CN CN201811450087.7A patent/CN109585273B/zh active Active
- 2018-12-17 WO PCT/CN2018/121423 patent/WO2020107544A1/zh active Application Filing
-
2020
- 2020-09-29 US US17/036,126 patent/US11244821B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101207063A (zh) * | 2006-12-18 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | 浅沟槽隔离的形成方法 |
US20160042949A1 (en) * | 2014-08-06 | 2016-02-11 | Tamura Corporation | METHOD OF FORMING HIGH-RESISTIVITY REGION IN Ga2O3-BASED SINGLE CRYSTAL, AND CRYSTAL LAMINATE STRUCTURE AND SEMICONDUCTOR ELEMENT |
CN107464844A (zh) * | 2017-07-20 | 2017-12-12 | 中国电子科技集团公司第十三研究所 | 氧化镓场效应晶体管的制备方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2020107544A1 (zh) | 2020-06-04 |
US20210013027A1 (en) | 2021-01-14 |
US11244821B2 (en) | 2022-02-08 |
CN109585273B (zh) | 2020-04-28 |
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Inventor after: Lv Yuanjie Inventor after: Intelligence Inventor after: Wang Yuangang Inventor after: Zhou Xingye Inventor after: Tan Xin Inventor after: Song Xubo Inventor after: Liang Shixiong Inventor after: Feng Zhihong Inventor before: Lv Yuanjie Inventor before: Wang Yuangang Inventor before: Zhou Xingye Inventor before: Tan Xin Inventor before: Song Xubo Inventor before: Liang Shixiong Inventor before: Feng Zhihong |