CN109582516B - SSD back-end performance analysis method and device, computer equipment and storage medium - Google Patents
SSD back-end performance analysis method and device, computer equipment and storage medium Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
Abstract
The application relates to a method and a device for analyzing the performance of a back end of an SSD, a computer device and a storage medium, wherein the method comprises the following steps: firstly, acquiring a SSD rear end performance analysis request; calculating the total number of descriptors to be issued according to the SSD back-end performance analysis request; judging whether the total number of the descriptors to be issued is greater than the total number of the recycle descriptors; if the total number of the descriptors to be issued is not more than the total number of the recovery descriptors, recording the execution time of the descriptors; and calculating a data transmission rate according to the time of the descriptor execution and the data size of the descriptor operation so as to analyze the SSD back-end performance. In addition, the performance obtained by comparing the performance obtained by the method with the theoretical performance of the rear-end module can better analyze the performance bottleneck of software and hardware of the system, and provides reference and direction for improving the performance of the whole system.
Description
Technical Field
The invention relates to the technical field of performance analysis of solid state disks, in particular to a method and a device for analyzing the performance of a SSD (solid state disk), computer equipment and a storage medium.
Background
At present, a whole system of a SSD (Solid State Disk) is composed of a plurality of modules, and a common system performance analysis is usually performed on the performance of the whole system. Common SSD performance test software CrystalDiskMark, PCMArk and the like only analyze the overall performance and cannot obtain the performance of each module.
In the conventional technology, the whole system is usually tested by using CrystalDiskMark, and codes are based on an FPGA platform. The performance of the whole system is tested, that is, all modules comprise a Controller, a DRAM and a FLASH, and the Controller mainly comprises PCIe, NVMe, DPM, FTL, NFC, DDR, Platform module and the like, and is used for performing performance analysis on the whole. Therefore, when the system performance is low and needs to be optimized, the performance of each module of the system is difficult to know by the testing method, and the performance bottleneck of the system cannot be located.
Disclosure of Invention
In view of the foregoing, it is desirable to provide an SSD back-end performance analysis method, an apparatus, a computer device and a storage medium, which can implement independent analysis of SSD back-end performance.
A SSD back-end performance analysis method, the method comprising:
acquiring a SSD rear-end performance analysis request;
calculating the total number of descriptors to be issued according to the SSD back-end performance analysis request;
judging whether the total number of the descriptors to be issued is greater than the total number of the recycle descriptors;
if the total number of the descriptors to be issued is not more than the total number of the recovery descriptors, recording the execution time of the descriptors;
and calculating a data transmission rate according to the time of the descriptor execution and the data size of the descriptor operation so as to realize the analysis of the SSD back-end performance.
In one embodiment, after the step of determining whether the total number of the descriptors to be issued is greater than the total number of the recycle descriptors, the method further includes:
if the total number of the descriptors to be issued is greater than the total number of the recovery descriptors, issuing the descriptors according to die;
judging whether the cdma channel fifo in the NFC is full or not;
if the cdma channel fifo in the NFC is full, acquiring a corresponding descriptor according to the number of die, and checking the state of the corresponding descriptor;
judging whether the descriptor is executed successfully;
if the descriptor is successfully executed, adding 1 to the count of the recycle descriptor;
and if the descriptor is not successfully executed, resetting the cdma channel in the NFC until the descriptor is successfully executed.
In one embodiment, the step of determining whether the cdma channel fifo in NFC is full further includes:
and if the cdma channel fifo in the NFC is not full, continuing to send down the descriptor according to die until the cdma channel fifo in the NFC is full.
In one embodiment, the step of calculating the total number of descriptors to be issued according to the SSD back-end performance analysis request includes:
acquiring the number of die, block and page of NAND used by an issued descriptor;
and calculating the total number of the descriptors to be issued according to the number of the die of the NAND, the number of the block of the NAND and the number of the page of the NAND.
An SSD back-end performance analysis device, the SSD back-end performance analysis device comprising:
an acquisition module, configured to acquire an SSD back-end performance analysis request;
the first calculation module is used for calculating the total number of the descriptors to be issued according to the SSD back-end performance analysis request;
the first judging module is used for judging whether the total number of the descriptors to be issued is greater than the total number of the recycling descriptors;
the recording time module is used for recording the execution time of the descriptors if the total number of the descriptors to be issued is not more than the total number of the recovery descriptors;
a second calculation module, configured to calculate a data transmission rate according to the time of the descriptor execution and the data size of the descriptor operation, so as to implement analysis on SSD backend performance.
In one embodiment, the SSD back-end performance analysis device further includes:
the issuing module is used for issuing the descriptors according to die if the total number of the descriptors to be issued is larger than the total number of the recovery descriptors;
the second judging module is used for judging whether the cdma channel fifo in the NFC is full or not; if the cdma channel fifo in the NFC is full, acquiring a corresponding descriptor according to the number of die, and checking the state of the corresponding descriptor;
a third judging module, configured to judge whether the descriptor is successfully executed; if the descriptor is successfully executed, adding 1 to the count of the recycle descriptor; and if the descriptor is not successfully executed, resetting the cdma channel in the NFC until the descriptor is successfully executed.
In one embodiment, the second determining module is further configured to:
and if the cdma channel fifo in the NFC is not full, continuing issuing descriptors according to die until the cdma channel fifo in the NFC is full.
In one embodiment, the first computing module is further configured to:
acquiring the number of die, block and page of NAND used by an issued descriptor;
and calculating the total number of the descriptors to be issued according to the number of the die of the NAND, the number of the block of the NAND and the number of the page of the NAND.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any of the above methods when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of any of the above-mentioned methods.
According to the SSD back-end performance analysis method, the SSD back-end performance analysis device, the computer equipment and the storage medium, firstly, an SSD back-end performance analysis request is obtained; calculating the total number of descriptors to be issued according to the SSD back-end performance analysis request; judging whether the total number of the descriptors to be issued is greater than the total number of the recycle descriptors; if the total number of the descriptors to be issued is not more than the total number of the recovery descriptors, recording the execution time of the descriptors; and calculating a data transmission rate according to the time of the descriptor execution and the data size of the descriptor operation so as to realize the analysis of the SSD back-end performance. In addition, the performance obtained by comparing the performance obtained by the method with the theoretical performance of the SSD rear-end module can better analyze the performance bottleneck of software and hardware of the system, and provides reference and direction for improving the performance of the whole system.
Drawings
FIG. 1 is a diagram of a system architecture for SSD performance analysis in the prior art;
FIG. 2 is a system architecture diagram of a SSD back-end performance analysis method in one embodiment;
FIG. 3 is a schematic flow chart diagram of a SSD backend performance analysis method in one embodiment;
FIG. 4 is a schematic flow chart diagram of a SSD backend performance analysis method in another embodiment;
FIG. 5 is a flow diagram of a complete SSD back-end performance analysis in one embodiment;
FIG. 6 is a flowchart illustrating the steps of calculating the total number of descriptors to be issued according to an SSD backend performance analysis request in one embodiment;
FIG. 7 is a block diagram of an SSD back-end performance analysis device in one embodiment;
FIG. 8 is a block diagram of an SSD backend performance analysis apparatus in another embodiment;
FIG. 9 is a diagram of an internal structure of a computer device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
As shown in fig. 1, the complete system architecture of the existing SSD mainly includes Controller, DRAM and FLASH, and the Controller mainly includes PCIe, NVMe, DPM, FTL, NFC, DDR and Platform modules. The conventional NAND FLASH program is generally divided into two processes, that is, first writing HOST data into DRAM, and then NFC reads data in DRAM by filling in a descriptor and writes the data into NAND. The Read process is similar to the Program process, and is also divided into two stages, namely the NAND data is moved to the DRAM by the NFC, and the data is Read from the DRAM to the Host cache by the DPM. The performance of the whole system is tested, which means that all the modules are taken as a whole for performance analysis. Therefore, when the system performance is low and needs to be optimized, the performance of each module of the system is difficult to know by the testing method, and the performance bottleneck of the system cannot be located. As shown in fig. 2, fig. 2 is a system architecture applied to the SSD back-end performance analysis method provided by the present invention, and compared with the complete SSD system of fig. 1, the system does not have NVME, DPM, FTL, and only has an NFC back-end module. The model is continuously sent to NFC after host prepares the descriptor to analyze the performance of the backend separately.
In one embodiment, as shown in fig. 3, there is provided an SSD back-end performance analysis method applied in the system architecture of fig. 2, the method comprising:
step 302, acquiring an SSD back-end performance analysis request;
step 304, calculating the total number of descriptors to be issued according to the SSD rear-end performance analysis request;
step 306, judging whether the total number of the descriptors needing issuing is greater than the total number of the recycling descriptors;
step 308, if the total number of the descriptors to be issued is not more than the total number of the recycle descriptors, recording the execution time of the descriptors;
and step 310, calculating a data transmission rate according to the time of the execution of the descriptor and the data size of the descriptor operation so as to analyze the SSD back-end performance.
Specifically, in this embodiment, first, a SSD back-end performance analysis request is obtained; calculating the total number of descriptors to be issued according to the SSD back-end performance analysis request; judging whether the total number of the descriptors needing issuing is greater than the total number of the recycling descriptors; if the total number of the descriptors needing issuing is not more than the total number of the recovery descriptors, recording the execution time of the descriptors; and calculating the data transmission rate according to the execution time of the descriptor and the data size of the descriptor operation so as to analyze the SSD back-end performance. In addition, the performance obtained by comparing the performance obtained by the method with the theoretical performance of the SSD rear-end module can better analyze the performance bottleneck of software and hardware of the system, and provides reference and direction for improving the performance of the whole system.
In one specific embodiment, referring to fig. 4, a method for analyzing SSD backend performance is provided, wherein the step of determining whether the total number of descriptors to be issued is greater than the total number of recycle descriptors further includes:
402, if the total number of the descriptors needing to be issued is greater than the total number of the recycling descriptors, issuing the descriptors according to die;
step 404, judging whether the cdma channel fifo in the NFC is full;
step 406, if the cdma channel fifo in the NFC is not full, continuing to issue descriptors according to die until the cdma channel fifo in the NFC is full;
step 408, if the cdma channel fifo in the NFC is full, acquiring a corresponding descriptor according to the number of die, and checking the state of the corresponding descriptor;
step 410, judging whether the descriptor is executed successfully;
step 412, if the descriptor is not executed successfully, the cdma channel in the NFC is reset until the descriptor is executed successfully;
in step 414, if the descriptor is successfully executed, the count of the recycle descriptor is incremented by 1.
Specifically, referring to fig. 5, fig. 5 is a flowchart of a complete SSD back end performance analysis, including:
1. calculating the total number of descriptors to be issued to be equal to die _ cnt _ blk _ cnt _ page _ cnt according to the number die _ cnt of the NAND used for issuing the descriptors, the number blk _ cnt of the NAND block, and the number page _ cnt of the NAND page, and performing a flow 2 if the number of the descriptors to be issued is less than the total number of the descriptors to be issued; if the number of the delivered descriptors is greater than or equal to the total number of the required delivered descriptors, the flow 6 is performed.
2. Because the cdma channel of NFC corresponds to DIE of NAND, the descriptor is issued as DIE when it is issued.
3. The cdma channel has a fifo depth, and when the fifo is not full, the flow 2 is continued; when fifo is full, flow 4 is followed.
4. And acquiring a corresponding descriptor according to the die, checking the state of the descriptor, if the state of the descriptor is the execution failure, resetting the corresponding cdma channel, and then performing the flow 5.
5. The count of the issued descriptor is incremented by 1. Then, the process proceeds to scheme 1.
6. And calculating the data transmission rate, namely the performance of the NFC back end according to the execution time of all the descriptors and the data size of all the descriptor operations.
In this embodiment, because the frequency of the NFC CORE on the FPGA platform is limited to 25MHz, the theoretical performance of NFC can be obtained according to the equal proportion calculation, the performance of the NFC rear end can be obtained through the designed model, the performance obtained through comparing the model and the theoretical performance of NFC can be better to analyze the system software and hardware performance bottleneck, and a reference and a direction are provided for improving the performance of the entire system.
In one specific embodiment, referring to fig. 6, a method for analyzing SSD backend performance is provided, where the step of calculating the total number of descriptors to be issued according to the SSD backend performance analysis request includes:
step 602, acquiring the number of die, block and page of the NAND used by the issued descriptor;
and step 604, calculating the total number of the descriptors to be issued according to the number of the die of the NAND, the number of the blocks of the NAND and the number of the pages of the NAND.
In this embodiment, the total number of descriptors to be issued is calculated by the number of die of the NAND, the number of blocks of the NAND, and the number of pages of the NAND.
It should be understood that although the various steps in the flow diagrams of fig. 3-6 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least some of the steps in fig. 3-6 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or alternatingly with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, as shown in fig. 7, there is provided an SSD back end performance analysis apparatus 700, the apparatus comprising:
an obtaining module 701, configured to obtain an SSD back-end performance analysis request;
a first calculating module 702, configured to calculate a total number of descriptors to be issued according to the SSD back-end performance analysis request;
a first determining module 703, configured to determine whether the total number of descriptors to be issued is greater than the total number of descriptors to be recovered;
a record time module 704, configured to record the execution time of the descriptor if the total number of the descriptors that need to be issued is not greater than the total number of the recycle descriptors;
the second calculation module 705 is configured to calculate a data transmission rate according to the time of the descriptor execution and the data size of the descriptor operation to implement the SSD back-end performance analysis.
In one embodiment, as shown in fig. 8, there is provided an SSD back end performance analysis apparatus 700, the apparatus further comprising:
the issuing module 706 is configured to issue the descriptors according to die if the total number of the descriptors to be issued is greater than the total number of the recycle descriptors;
a second determining module 707, configured to determine whether the cdma channel fifo in the NFC is full; if the cdma channel fifo in the NFC is full, acquiring a corresponding descriptor according to the number of die, and checking the state of the corresponding descriptor;
a third determining module 708, configured to determine whether the descriptor is executed successfully; if the descriptor is successfully executed, adding 1 to the count of the recycle descriptor; if the descriptor is not executed successfully, the cdma channel in NFC is reset until the descriptor is executed successfully.
In one embodiment, the second determining module 707 is further configured to: and if the cdma channel fifo in the NFC is not full, continuing to send down the descriptor according to die until the cdma channel fifo in the NFC is full.
In one embodiment, the first calculation module 702 is further configured to: acquiring the number of die, block and page of NAND used by an issued descriptor; and calculating the total number of the descriptors to be issued according to the number of die of the NAND, the number of block of the NAND and the number of page of the NAND.
For specific limitations of the SSD back-end performance analysis device 700, reference may be made to the above limitations of the SSD back-end performance analysis method, which is not described herein again.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 9. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operating system and the computer program to run on the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement an SSD back-end performance analysis method.
Those skilled in the art will appreciate that the architecture shown in fig. 9 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method embodiments when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above respective method embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include non-volatile and/or volatile memory. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.
Claims (10)
1. A SSD back-end performance analysis method, the method comprising:
acquiring an SSD back-end performance analysis request;
calculating the total number of descriptors to be issued according to the SSD back-end performance analysis request; the descriptor is used for describing a data structure for storing information;
judging whether the total number of the descriptors to be issued is greater than the total number of the recycle descriptors;
if the total number of the descriptors to be issued is not more than the total number of the recovery descriptors, recording the execution time of the descriptors;
and calculating a data transmission rate according to the time of the descriptor execution and the data size of the descriptor operation so as to realize the analysis of the SSD back-end performance.
2. The SSD back-end performance analyzing method of claim 1, further comprising, after the step of determining whether the total number of the to-be-issued descriptors is greater than the total number of recycle descriptors:
if the total number of the descriptors to be issued is greater than the total number of the recovery descriptors, issuing the descriptors according to die;
judging whether the cdma channel fifo in the NFC is full or not; the NFC is a Nand Flash controller, and the cdma channel is a CDMA channel;
if the cdma channel fifo in the NFC is full, acquiring a corresponding descriptor according to the number of die, and checking the state of the corresponding descriptor;
judging whether the descriptor is executed successfully;
if the descriptor is successfully executed, adding 1 to the count of the recycling descriptor;
and if the descriptor is not successfully executed, resetting the cdma channel in the NFC until the descriptor is successfully executed.
3. The SSD back-end performance analyzing method of claim 2, wherein the step of determining whether the cdma channel fifo in NFC is full further comprises:
and if the cdma channel fifo in the NFC is not full, continuing issuing descriptors according to die until the cdma channel fifo in the NFC is full.
4. The SSD back-end performance analysis method of any one of claims 1 to 3, wherein the step of calculating the total number of descriptors that need to be issued according to the SSD back-end performance analysis request comprises:
acquiring the number of die, block and page of NAND used by an issued descriptor;
and calculating the total number of the descriptors to be issued according to the number of the die of the NAND, the number of the block of the NAND and the number of the page of the NAND.
5. An SSD back-end performance analysis device, comprising:
the acquisition module is used for acquiring the SSD back-end performance analysis request;
the first calculation module is used for calculating the total number of descriptors to be issued according to the SSD rear-end performance analysis request; the descriptor is used for describing a data structure for storing information;
the first judging module is used for judging whether the total number of the descriptors to be issued is greater than the total number of the recycling descriptors;
the recording time module is used for recording the execution time of the descriptors if the total number of the descriptors to be issued is not more than the total number of the recovery descriptors;
a second calculation module, configured to calculate a data transmission rate according to the time of the descriptor execution and the data size of the descriptor operation, so as to implement analysis on SSD backend performance.
6. The SSD backend performance analysis device of claim 5, further comprising:
the issuing module is used for issuing the descriptors according to die if the total number of the descriptors to be issued is larger than the total number of the recovery descriptors;
the second judgment module is used for judging whether the cdma channel fifo in the NFC is full or not; if the cdma channel fifo in the NFC is full, acquiring a corresponding descriptor according to the number of die, and checking the state of the corresponding descriptor; the NFC is a Nand Flash controller, and the cdma channel is a CDMA channel;
a third determining module, configured to determine whether the descriptor is executed successfully; if the descriptor is successfully executed, adding 1 to the count of the recycling descriptor; and if the descriptor is not successfully executed, resetting the cdma channel in the NFC until the descriptor is successfully executed.
7. The SSD backend performance analysis apparatus of claim 6, wherein the second determining module is further configured to:
and if the cdma channel fifo in the NFC is not full, continuing to send down the descriptor according to die until the cdma channel fifo in the NFC is full.
8. The SSD backend performance analysis apparatus of any one of claims 5 to 7, wherein the first computing module is further configured to:
acquiring the number of die, block and page of NAND used by an issued descriptor;
and calculating the total number of the descriptors to be issued according to the number of the die of the NAND, the number of the block of the NAND and the number of the page of the NAND.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method of any of claims 1 to 4 are implemented when the computer program is executed by the processor.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 4.
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