CN114047880B - NAND write power consumption optimization method and device for multi-Pass programming and computer equipment - Google Patents
NAND write power consumption optimization method and device for multi-Pass programming and computer equipment Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
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- G06F11/14—Error detection or correction of the data by redundancy in operation
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The application relates to a NAND write power consumption optimization method, device, computer equipment and storage medium for multi-Pass programming, wherein the method comprises the following steps: acquiring a NAND write power consumption optimization request of multi-Pass programming; in the process of page programming of multi-Pass programming according to the power consumption optimization request, ECC encoding is carried out only in a Pass 1 programming stage through an ECC engine; backing up the check data generated by the ECC engine in a memory; sending data to NAND for Pass 1 programming; in the subsequent Pass programming, the user data, the metadata and the locally stored check data are directly sent to the NAND for programming without passing through the ECC engine. Aiming at the scene of multi-Pass programming, the scheme provided by the invention only stores and backs up the check data into the memory in the first Pass programming, and the subsequent Pass programming does not need to be calculated again, so that the power consumption expenditure is effectively reduced.
Description
Technical Field
The present invention relates to the field of storage systems, and in particular, to a method and apparatus for optimizing NAND write power consumption in multi-Pass programming, a computer device, and a storage medium.
Background
With the development of Solid State Disk technology, SSD (Solid State Disk) has been widely used in various occasions, and the PC market has gradually replaced the conventional HDD (Hard Disk Drive), so as to provide better experience for users in terms of reliability and performance. With the improvement of the speed of the host interface and the NAND interface, the SSD performance is higher and higher, and further with the improvement of the whole machine endurance, the power consumption requirement on the SSD is higher and higher. The lower the SSD power consumption, the higher the endurance of the whole machine.
At present, when the SOC chip in the SSD handles high-speed data access, various complex operations are required, so the power consumption overhead is relatively large. Taking the SSD of PCIe Gen 4 as an example, the writing speed can reach 6GB/s, and the data can be subjected to ECC code generation before being written on NAND, so that error correction can be performed when the subsequent reading is in error. In the conventional technology, for NAND with Multi-Pass programming (such as QLC typically), each programming requires multiple data transfers to the NAND, and thus multiple ECC generation operations are required, resulting in a large power consumption overhead.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a NAND write power consumption optimization method, apparatus, computer device and storage medium for multi-Pass programming.
A NAND write power consumption optimization method of multi Pass programming, the method comprising:
acquiring a NAND write power consumption optimization request of multi-Pass programming;
in the process of page programming of multi-Pass programming according to the power consumption optimization request, ECC encoding is carried out only in a Pass 1 programming stage through an ECC engine;
backing up the check data generated by the ECC engine in a memory;
sending data to NAND for Pass 1 programming;
in the subsequent Pass programming, the user data, the metadata and the locally stored check data are directly sent to the NAND for programming without passing through the ECC engine.
In one embodiment, the method further comprises:
the host writes data and judges whether the NAND Pass 1 is programmed;
if the NAND Pass 1 is programmed, the data is subjected to ECC encoding through an ECC engine;
backing up check data generated by the ECC engine into the memory;
data is sent to the NAND for Pass 1 programming.
In one embodiment, the step of the host writing data and determining whether to program NAND Pass 1 further comprises:
if the NAND Pass 1 programming is not, the data is directly sent to the NAND for the programming of the corresponding Pass.
In one embodiment, the step of sending data to the NAND for Pass 1 programming further comprises:
judging whether programming of all Pass is completed or not;
if not, jumping to the step of judging whether the NAND Pass 1 programming is performed to perform the subsequent Pass programming; if yes, programming is finished, and the memory used for backing up the check data is released.
A NAND write power consumption optimization apparatus of multi Pass programming, the apparatus comprising:
the acquisition module is used for acquiring NAND write power consumption optimization requests of multi-Pass programming;
the encoding module is used for performing ECC encoding through an ECC engine only in a Pass 1 programming stage in the process of performing page programming of multi-Pass programming according to the power consumption optimization request;
the backup module is used for backing up the check data generated by the ECC engine in the memory;
the programming module is used for sending data to the NAND to carry out Pass 1 programming; in the subsequent Pass programming, the user data, the metadata and the locally stored check data are directly sent to the NAND for programming without passing through the ECC engine.
In one embodiment, the programming module is further configured to:
the host writes data and judges whether the NAND Pass 1 is programmed;
if the NAND Pass 1 is programmed, the data is subjected to ECC encoding through an ECC engine;
backing up check data generated by the ECC engine into the memory;
data is sent to the NAND for Pass 1 programming.
In one embodiment, the programming module is further configured to:
if the NAND Pass 1 programming is not, the data is directly sent to the NAND for the programming of the corresponding Pass.
In one embodiment, the programming module is further configured to:
judging whether programming of all Pass is completed or not;
if not, jumping to the step of judging whether the NAND Pass 1 programming is performed to perform the subsequent Pass programming; if yes, programming is finished, and the memory used for backing up the check data is released.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any one of the methods described above when the computer program is executed.
A computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of any of the methods described above.
According to the NAND write power consumption optimization method, device, computer equipment and storage medium for multi-Pass programming, the NAND write power consumption optimization request for multi-Pass programming is obtained; in the process of page programming of multi-Pass programming according to the power consumption optimization request, ECC encoding is carried out only in a Pass 1 programming stage through an ECC engine; backing up the check data generated by the ECC engine in a memory; sending data to NAND for Pass 1 programming; in the subsequent Pass programming, the user data, the metadata and the locally stored check data are directly sent to the NAND for programming without passing through the ECC engine. Aiming at the scene of multi-Pass programming, the scheme provided by the invention only stores and backs up the check data into the memory in the first Pass programming, and the subsequent Pass programming does not need to be calculated again, so that the SSD power consumption overhead is effectively reduced.
Drawings
FIG. 1 is a schematic diagram of a typical NAND composition;
FIG. 2 is a schematic diagram of a typical NAND multi-Pass programming model;
FIG. 3 is a flow chart of a NAND write power consumption optimization method of multi-Pass programming in one embodiment;
FIG. 4 is a schematic diagram of an introduced NAND multi-Pass programming optimization model of the present invention;
FIG. 5 is a flow chart of a corresponding NAND multi-Pass write process of the present invention;
FIG. 6 is a block diagram of a NAND write power consumption optimization device with multiple Pass programming in one embodiment;
fig. 7 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
As shown in fig. 1, a typical NAND composition is as follows, including: a DIE, units that can operate independently concurrently; a Block, an independently erasable unit in which the data at each physical location must be erased after writing and before the next writing; page, read-write unit, page within the same physical block must be programmed in order of 0- >1- >2- >3 …. As NAND technology evolves, its Page programming model becomes more complex. Taking QLC as an example, it requires multiple times of programming of Page according to certain rules to reach a stable state. During this time, the data to be stored needs to be transferred onto the NAND a plurality of times.
As shown in fig. 2, a typical NAND multipass programming model is shown. Specifically, NAND Page programmed data is generally composed of three types, including: user data for data written for the host; metadata for managing data for the SSD internal system; and the check data is used for encoding the user data and the metadata for ECC check data so as to correct and check errors in subsequent read-out.
Typically, user data and metadata will remain backed up in memory, while check data is dynamically generated by a specialized ECC encoding engine. During multi-Pass programming, each Pass (Pass 1/2/3 … N) inputs the user data and the metadata stored at this time to an ECC engine, and verification data is dynamically generated. Finally, the user data, metadata, and verification data are transferred to the NAND for programming. In the process, each Pass programming needs to dynamically generate check data by the ECC engine, so that the power consumption overhead requirement is extremely high, the overall power consumption of the SSD is further influenced, and the endurance capacity of the whole machine is reduced.
Based on the above, the invention provides a NAND write power consumption optimization method of multi-Pass programming, aiming at avoiding multiple ECC codes to reduce power consumption.
In one embodiment, as shown in FIG. 3, a NAND write power consumption optimization method of multi-Pass programming is provided, the method comprising:
step 302, obtaining a NAND write power consumption optimization request of multi-Pass programming;
step 304, in the process of page programming of multi-Pass programming according to the power consumption optimization request, ECC encoding is performed only in the Pass 1 programming stage through an ECC engine;
step 306, the check data generated by the ECC engine is backed up in the memory;
step 308, send data to NAND for Pass 1 programming;
in step 310, the user data, metadata and locally stored verification data are directly sent to the NAND for programming without going through the ECC engine in subsequent Pass programming.
In this embodiment, a NAND write power consumption optimization method for multi Pass programming is provided, and the specific implementation process of the method is as follows:
first, a NAND write power consumption optimization request for multi-Pass programming is obtained. Next, for Multi-Pass programmed granules, the ECC engine is passed through while Pass 1 is being programmed.
Then, the check data generated by the ECC engine is backed up in the memory; and then the data is sent to the NAND to complete Pass 1 programming. Therefore, the check data can be stored, and ECC encoding can be avoided for a plurality of times, so that the power consumption is reduced.
Finally, during subsequent Pass programming, user data, metadata and locally stored check data are directly sent to the NAND for programming without going through an ECC engine. Through the strategy, ECC coding is only carried out when Pass 1 is programmed, and recoding is not needed in subsequent Pass programming, so that the operation requirement of the SOC is reduced, and further, the power consumption is effectively reduced.
In the embodiment, the NAND write power consumption optimization request of the multi-Pass programming is obtained; in the process of page programming of multi-Pass programming according to the power consumption optimization request, ECC encoding is carried out only in a Pass 1 programming stage through an ECC engine; backing up the check data generated by the ECC engine in a memory; sending data to NAND for Pass 1 programming; in the subsequent Pass programming, the user data, the metadata and the locally stored check data are directly sent to the NAND for programming without passing through the ECC engine. Aiming at the scene of multi-Pass programming, the scheme only stores and backs up the check data into the memory in the first Pass programming, and the subsequent Pass programming does not need to be calculated again, so that the power consumption cost is effectively reduced.
In one embodiment, a NAND write power consumption optimization method for multi Pass programming is provided, the method further comprising:
the host writes data and judges whether the NAND Pass 1 is programmed;
if the NAND Pass 1 is programmed, the data is subjected to ECC encoding through an ECC engine; if the programming is not the NAND Pass 1 programming, directly sending the data to the NAND to carry out the programming of the corresponding Pass;
backing up check data generated by the ECC engine into the memory;
sending data to NAND for Pass 1 programming;
judging whether programming of all Pass is completed or not;
if not, jumping to the step of judging whether the NAND Pass 1 programming is performed to perform the subsequent Pass programming; if yes, programming is finished, and the memory used for backing up the check data is released.
In this embodiment, referring to fig. 5, a method for completely optimizing NAND write power consumption of multi Pass programming is provided, and the method specifically includes the following steps:
and 5.1, writing data by the host.
Step 5.2, whether to program NAND Pass 1. If not, jumping to the step 5.5; if yes, continue step 5.3.
And 5.3, encoding the data through an ECC engine.
And 5.4, backing up check data generated by the ECC engine into the memory.
Step 5.5, data is sent to NAND to perform corresponding Pass programming.
Step 5.6, whether programming of all Pass is completed. If not, jumping to the step 5.2, and performing subsequent Pass programming; if yes, the programming is finished, and the memory used for backing up the check data is released.
It should be understood that, although the steps in the flowcharts of fig. 1-5 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1-5 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor do the order in which the sub-steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the sub-steps or stages of other steps or steps.
In one embodiment, as shown in FIG. 6, a NAND write power consumption optimization apparatus 600 for multiple Pass programming is provided, the apparatus comprising:
an acquisition module 601, configured to acquire a NAND write power consumption optimization request of multi Pass programming;
the encoding module 602 is configured to perform ECC encoding only in a Pass 1 programming stage by using an ECC engine during page programming of multi-Pass programming according to the power consumption optimization request;
the backup module 603 is configured to backup the check data generated by the ECC engine in a memory;
a programming module 604 for sending data to the NAND for Pass 1 programming; in the subsequent Pass programming, the user data, the metadata and the locally stored check data are directly sent to the NAND for programming without passing through the ECC engine.
In one embodiment, programming module 604 is further to:
the host writes data and judges whether the NAND Pass 1 is programmed;
if the NAND Pass 1 is programmed, the data is subjected to ECC encoding through an ECC engine;
backing up check data generated by the ECC engine into the memory;
data is sent to the NAND for Pass 1 programming.
In one embodiment, programming module 604 is further to:
if the NAND Pass 1 programming is not, the data is directly sent to the NAND for the programming of the corresponding Pass.
In one embodiment, programming module 604 is further to:
judging whether programming of all Pass is completed or not;
if not, jumping to the step of judging whether the NAND Pass 1 programming is performed to perform the subsequent Pass programming; if yes, programming is finished, and the memory used for backing up the check data is released.
For specific limitations on the NAND write power consumption optimizing apparatus of the multi Pass programming, reference may be made to the above limitation on the NAND write power consumption optimizing method of the multi Pass programming, and the description thereof will not be repeated here.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 7. The computer device includes a processor, a memory, and a network interface connected by a device bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The nonvolatile storage medium stores an operating device, a computer program, and a database. The internal memory provides an environment for the operation of the operating device and the computer program in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by a processor, implements a NAND write power consumption optimization method of multi-Pass programming.
It will be appreciated by those skilled in the art that the structure shown in fig. 7 is merely a block diagram of some of the structures associated with the present application and is not limiting of the computer device to which the present application may be applied, and that a particular computer device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided that includes a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps in the method embodiments above when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, carries out the steps of the above method embodiments.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A method for optimizing NAND write power consumption for multi Pass programming, the method comprising:
acquiring a NAND write power consumption optimization request of multi-Pass programming;
in the process of page programming of multi-Pass programming according to the power consumption optimization request, ECC encoding is carried out only in a Pass 1 programming stage through an ECC engine;
backing up the check data generated by the ECC engine in a memory;
sending data to NAND for Pass 1 programming;
in the subsequent Pass programming, the user data, the metadata and the locally stored check data are directly sent to the NAND for programming without passing through the ECC engine.
2. The NAND write power consumption optimization method of multi Pass programming of claim 1, further comprising:
the host writes data and judges whether the NAND Pass 1 is programmed;
if the NAND Pass 1 is programmed, the data is subjected to ECC encoding through an ECC engine;
backing up check data generated by the ECC engine into the memory;
data is sent to the NAND for Pass 1 programming.
3. The method of optimizing NAND write power consumption for multi-Pass programming of claim 2, further comprising, after the step of the host writing data and determining whether to program NAND Pass 1:
if the NAND Pass 1 programming is not, the data is directly sent to the NAND for the programming of the corresponding Pass.
4. The method of optimizing NAND write power consumption for multi-Pass programming of claim 3 further comprising, after said step of sending data to NAND for Pass 1 programming:
judging whether programming of all Pass is completed or not;
if not, jumping to the step of judging whether the NAND Pass 1 programming is performed to perform the subsequent Pass programming; if yes, programming is finished, and the memory used for backing up the check data is released.
5. A NAND write power consumption optimizing device for multiple Pass programming, the device comprising:
the acquisition module is used for acquiring NAND write power consumption optimization requests of multi-Pass programming;
the encoding module is used for performing ECC encoding through an ECC engine only in a Pass 1 programming stage in the process of performing page programming of multi-Pass programming according to the power consumption optimization request;
the backup module is used for backing up the check data generated by the ECC engine in the memory;
the programming module is used for sending data to the NAND to carry out Pass 1 programming; in the subsequent Pass programming, the user data, the metadata and the locally stored check data are directly sent to the NAND for programming without passing through the ECC engine.
6. The NAND write power consumption optimization apparatus of multi Pass programming of claim 5 wherein the programming module is further configured to:
the host writes data and judges whether the NAND Pass 1 is programmed;
if the NAND Pass 1 is programmed, the data is subjected to ECC encoding through an ECC engine;
backing up check data generated by the ECC engine into the memory;
data is sent to the NAND for Pass 1 programming.
7. The NAND write power consumption optimization apparatus of multi Pass programming of claim 6 wherein the programming module is further configured to:
if the NAND Pass 1 programming is not, the data is directly sent to the NAND for the programming of the corresponding Pass.
8. The NAND write power consumption optimization apparatus of multi Pass programming of claim 7 wherein the programming module is further configured to:
judging whether programming of all Pass is completed or not;
if not, jumping to the step of judging whether the NAND Pass 1 programming is performed to perform the subsequent Pass programming; if yes, programming is finished, and the memory used for backing up the check data is released.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any one of claims 1 to 4 when the computer program is executed.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 4.
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| CN107168816A (en) * | 2016-03-07 | 2017-09-15 | 北京忆恒创源科技有限公司 | ECC Frame Size Adjustments method and its device |
| CN111081308A (en) * | 2018-10-19 | 2020-04-28 | 奈奎斯特半导体有限公司 | System and method for hybrid non-volatile storage system |
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