CN109547013A - Tri-state gate - Google Patents
Tri-state gate Download PDFInfo
- Publication number
- CN109547013A CN109547013A CN201811263858.1A CN201811263858A CN109547013A CN 109547013 A CN109547013 A CN 109547013A CN 201811263858 A CN201811263858 A CN 201811263858A CN 109547013 A CN109547013 A CN 109547013A
- Authority
- CN
- China
- Prior art keywords
- nmos tube
- tri
- grid
- state gate
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Abstract
The invention discloses a kind of tri-state gates.Tri-state gate includes the first NMOS tube, the second NMOS tube, third NMOS tube and the first phase inverter.The number of metal-oxide-semiconductor required for the present invention is fewer than the prior art.
Description
Technical field
The present invention relates to technical field of integrated circuits more particularly to tri-state gates.
Background technique
Metal-oxide-semiconductor at least eight required for the tri-state gate circuit of the prior art, in order to simplify, circuit design is a kind of only to be needed
Want the tri-state gate of five metal-oxide-semiconductors.
Summary of the invention
Present invention seek to address that the deficiencies in the prior art, provide a kind of tri-state gate that required metal-oxide-semiconductor is few.
Tri-state gate, including the first NMOS tube, the second NMOS tube, third NMOS tube and the first phase inverter:
The grid of first NMOS tube meets input terminal A, and drain electrode meets supply voltage VCC, and source electrode connects the leakage of second NMOS tube
Pole and output end OUT as tri-state gate；The grid of second NMOS tube connects the output end of first phase inverter, and drain electrode connects
The source electrode of first NMOS tube and output end OUT as tri-state gate, source electrode connect the drain electrode of the third NMOS tube；Described
The grid of three NMOS tubes meets input terminal B, and drain electrode connects the source electrode of second NMOS tube, source electrode ground connection；First phase inverter
Input termination input terminal B, output terminate the grid of second NMOS tube.
When the input terminal A of tri-state gate is high level, when input terminal B is high level or low level, first NMOS tube
Grid be high level, the grid of second NMOS tube is low level, and the output end OUT of tri-state gate is high level；Work as tri-state
When the input terminal A of door is low level, when input terminal B is high level, the grid of second NMOS tube is high level, the third
The grid of NMOS tube is high level, and the output end OUT of tri-state gate is low level；When the input terminal A of tri-state gate is low level, input
When end B is low level, the grid of first NMOS tube is low level, and the grid of the third NMOS tube is low level, tri-state
The output end OUT of door is high-impedance state.
Detailed description of the invention
Fig. 1 is the circuit diagram of tri-state gate of the invention.
Specific embodiment
The content of present invention is further illustrated below in conjunction with attached drawing.
Tri-state gate, as shown in Figure 1, including the first NMOS tube 10, the second NMOS tube 20, third NMOS tube 30 and the first reverse phase
Device 40:
The grid of first NMOS tube 10 meets input terminal A, and drain electrode meets supply voltage VCC, and source electrode connects second NMOS tube 20
Drain electrode and output end OUT as tri-state gate；The grid of second NMOS tube 20 connects the output of first phase inverter 40
End, drain electrode connects the source electrode of first NMOS tube 10 and the output end OUT as tri-state gate, source electrode connect the third NMOS tube 30
Drain electrode；The grid of the third NMOS tube 30 meets input terminal B, and drain electrode connects the source electrode of second NMOS tube 20, source electrode ground connection；
The input of first phase inverter 40 terminates input terminal B, and output terminates the grid of second NMOS tube 20.
When the input terminal A of tri-state gate is high level, when input terminal B is high level or low level, first NMOS tube
10 grid is high level, and the grid of second NMOS tube 20 is low level, and the output end OUT of tri-state gate is high level；When
When the input terminal A of tri-state gate is low level, when input terminal B is high level, the grid of second NMOS tube 20 is high level, institute
The grid for stating third NMOS tube 30 is high level, and the output end OUT of tri-state gate is low level；The input terminal A of tri-state gate is low electricity
Usually, when input terminal B is low level, the grid of first NMOS tube 10 is low level, the grid of the third NMOS tube 30
For low level, the output end OUT of tri-state gate is high-impedance state.
Claims (1)
1. tri-state gate, it is characterised in that: including the first NMOS tube, the second NMOS tube, third NMOS tube and the first phase inverter；
The grid of first NMOS tube meets input terminal A, and drain electrode meets supply voltage VCC, and source electrode connects the leakage of second NMOS tube
Pole and output end OUT as tri-state gate；The grid of second NMOS tube connects the output end of first phase inverter, and drain electrode connects
The source electrode of first NMOS tube and output end OUT as tri-state gate, source electrode connect the drain electrode of the third NMOS tube；Described
The grid of three NMOS tubes meets input terminal B, and drain electrode connects the source electrode of second NMOS tube, source electrode ground connection；First phase inverter
Input termination input terminal B, output terminate the grid of second NMOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811263858.1A CN109547013A (en) | 2018-10-28 | 2018-10-28 | Tri-state gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811263858.1A CN109547013A (en) | 2018-10-28 | 2018-10-28 | Tri-state gate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109547013A true CN109547013A (en) | 2019-03-29 |
Family
ID=65845609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811263858.1A Pending CN109547013A (en) | 2018-10-28 | 2018-10-28 | Tri-state gate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109547013A (en) |
-
2018
- 2018-10-28 CN CN201811263858.1A patent/CN109547013A/en active Pending
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190329 |