CN109545754B - Chip packaging structure, chip packaging method and display device - Google Patents
Chip packaging structure, chip packaging method and display device Download PDFInfo
- Publication number
- CN109545754B CN109545754B CN201811399916.3A CN201811399916A CN109545754B CN 109545754 B CN109545754 B CN 109545754B CN 201811399916 A CN201811399916 A CN 201811399916A CN 109545754 B CN109545754 B CN 109545754B
- Authority
- CN
- China
- Prior art keywords
- chip
- groove
- circuit board
- photoresist
- filling material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Abstract
The invention discloses a chip packaging structure, a chip packaging method and a display device, relates to the technical field of packaging, and aims to solve the problem that when a chip is packaged, a hole phenomenon is easily generated between the chip and a circuit board after bottom filling operation is carried out, so that the reliability of chip packaging is reduced. The packaging structure of the chip comprises: the circuit board is arranged on the chip of the chip packaging area and filled with filling materials between the chip and the circuit board; the chip comprises a plurality of pins which are in one-to-one correspondence with a plurality of bonding pads on the circuit board, and the pins are electrically connected with the corresponding bonding pads to form a conductive part; at least part of the area of the circuit board corresponding to the gap between the adjacent conductive parts is provided with a first groove; and/or a second groove is arranged in at least partial area of the chip corresponding to the gap between the adjacent conductive parts. The packaging structure of the chip provided by the invention is used for providing a driving signal.
Description
Technical Field
The invention relates to the technical field of packaging, in particular to a chip packaging structure, a chip packaging method and a display device.
Background
The flip chip packaging technology is a packaging mode that solder balls are deposited on pins of a flip chip, then the flip chip is overturned and heated, and the flip chip is combined with a circuit board by utilizing the melted solder balls. When the chip is packaged by adopting the packaging mode, after the chip is combined with the circuit board, the underfill is also carried out between the chip and the circuit board by using the filling material, and the main purpose of the underfill is as follows: the contact area between the chip and the circuit board is increased, the bonding strength between the chip and the circuit board is improved, the thermal stress between the chip and the circuit board is released, and the solder balls are protected.
However, with the enhancement of the transmission capability of the chip, the number of the pins of the chip is increased, so that after the chip is combined with the circuit board, the density of the pins between the chip and the circuit board, the bonding pads connected with the pins on the circuit board and the density of the solder balls used for connecting the chip and the bonding pads are increased, so that when the bottom filling operation is carried out, the resistance borne by the filling material is increased, and meanwhile, because the flowing speed of the filling material in the edge area of the chip is higher, and the flowing speed is slower due to the resistance borne by the pins, the bonding pads and the solder balls in the middle area of the chip, the hole phenomenon is generated in the middle area of the packaged chip, and the reliability of.
Disclosure of Invention
The invention aims to provide a chip packaging structure, a chip packaging method and a display device, which are used for solving the problem that when a chip is packaged, a hole phenomenon is easily generated between the chip and a circuit board after an underfill operation, so that the reliability of chip packaging is reduced.
In order to achieve the above purpose, the invention provides the following technical scheme:
a first aspect of the present invention provides a chip package structure, including:
the chip packaging region of the circuit board comprises a plurality of welding pads which are arranged at intervals;
the chip is arranged in the chip packaging area and comprises a plurality of pins which are in one-to-one correspondence with the bonding pads, the orthographic projections of the pins on the circuit board are at least partially overlapped with the orthographic projections of the corresponding bonding pads on the circuit board, and the pins are electrically connected with the corresponding bonding pads to form a conductive part;
a filling material filled between the chip and the circuit board;
a first groove is formed in at least partial area of the circuit board corresponding to the area of the gap between the adjacent conductive parts; and/or the presence of a gas in the gas,
and second grooves are arranged in at least partial areas of the chips corresponding to the gaps between the adjacent conductive parts.
Optionally, the circuit board is provided with a first groove corresponding to all regions of the gap between adjacent conductive parts; and/or the presence of a gas in the gas,
and second grooves are formed in all the areas of the chip corresponding to the gaps between the adjacent conductive parts.
Optionally, the first groove extends along a flow direction when the filling material is filled between the chip and the circuit board; or the first groove extends along a direction perpendicular to a flow direction when the filling material is filled between the chip and the circuit board;
and/or the presence of a gas in the gas,
the second groove extends along a flow direction when the filling material is filled between the chip and the circuit board; or the second groove extends in a direction perpendicular to a flow direction when the filling material is filled between the chip and the circuit board.
Optionally, the width of the first groove in the direction perpendicular to the extending direction of the first groove is equal to the distance between the pads on two sides of the first groove in the direction perpendicular to the extending direction of the first groove; and/or the presence of a gas in the gas,
the width of the second groove in the direction perpendicular to the extending direction of the second groove is equal to the distance between the pins on two sides of the second groove in the direction perpendicular to the extending direction of the second groove.
Optionally, the circuit board is provided with a third groove around a peripheral region of all the conductive parts; and/or the presence of a gas in the gas,
the chip is provided with a fourth groove around the peripheral area of all the conductive parts.
Optionally, the depths of the first groove and the third groove in the direction perpendicular to the circuit board are both 1/3H-1/2H, where H is the thickness of the circuit board; and/or the presence of a gas in the gas,
the depth of the second groove and the depth of the fourth groove in the direction vertical to the circuit board are both 1/3D-1/2D, and D is the thickness of the chip in the direction vertical to the circuit board.
Based on the technical solution of the above chip package structure, a second aspect of the present invention provides a display device, including the above chip package structure.
Based on the above technical solution of the chip packaging structure, a third aspect of the present invention provides a chip packaging method, including:
manufacturing a circuit board, wherein a plurality of bonding pads are arranged in a chip packaging area of the circuit board at intervals;
manufacturing a chip, wherein the chip comprises a plurality of pins which are in one-to-one correspondence with the bonding pads;
the step of manufacturing a circuit board specifically comprises: manufacturing a first groove in at least partial area of the circuit board corresponding to the gap between the adjacent welding plates; and/or the step of manufacturing a chip specifically comprises: manufacturing a second groove in at least partial region of the chip corresponding to the gap between the adjacent pins;
welding the chip on a chip packaging area of the circuit board, so that the orthographic projection of the pin on the circuit board is at least partially overlapped with the orthographic projection of the corresponding pad on the circuit board, and the pin is electrically connected with the corresponding pad to form a conductive part;
injecting a flowing filling material between the chip and the circuit board, and curing the filling material after the filling material fills the gap between the circuit board and the chip.
Optionally, the step of manufacturing a circuit board further specifically includes:
manufacturing a third groove in the peripheral area of the circuit board surrounding all the bonding pads;
and/or the presence of a gas in the gas,
the step of fabricating a chip further comprises:
and manufacturing a fourth groove in the peripheral area of the chip surrounding all the pins.
Optionally, the step of forming the first groove and the third groove on the circuit board specifically includes:
forming a first photoresist on one side of the circuit board on which the bonding pad is formed;
exposing the first photoresist to form a first photoresist reserved region and a first photoresist removed region, wherein the first photoresist removed region corresponds to the regions where the first groove and the third groove are located, and the first photoresist reserved region corresponds to other regions except the regions where the first groove and the third groove are located;
developing the exposed first photoresist, and removing the first photoresist in the first photoresist removing area;
etching the circuit board in the first photoresist removing area to form the first groove and the third groove;
the step of forming the second groove and the fourth groove on the chip specifically includes:
forming a second photoresist on one side of the chip on which the pins are formed;
exposing the second photoresist to form a second photoresist reserved region and a second photoresist removed region, wherein the second photoresist removed region corresponds to the region where the second groove and the fourth groove are located, and the second photoresist reserved region corresponds to other regions except the region where the second groove and the fourth groove are located;
developing the exposed second photoresist, and removing the second photoresist in the second photoresist removing area;
and etching the chip positioned in the second photoresist removing area to form the second groove and the fourth groove.
In the technical scheme provided by the invention, at least partial area of the circuit board corresponding to the gap between the adjacent conductive parts is provided with a first groove; and/or a second groove is arranged in at least partial area of the chip corresponding to the gap between the adjacent conductive parts; make the accommodation space who forms between chip and circuit board increase in the direction of perpendicular to circuit board, make the middle zone at the chip on the direction of perpendicular to circuit board promptly, filling material's flow space grow, according to the parallel flat board theory, when filling material between chip and circuit board, filling material reduces at the middle zone resistance that receives of chip, filling material has faster flow speed in the middle zone of chip, thereby make filling material can be more even, more quick completion underfill process, effectively avoided producing the hole in the middle zone of chip, the reliability of chip package has been guaranteed. In addition, the flow speed of the filling material in the chip and the circuit board is increased, so that the filling efficiency of the filling material is improved, and the production efficiency of the chip packaging structure is improved better.
In addition, in the technical scheme provided by the invention, the accommodating space formed between the chip and the circuit board is enlarged by forming the groove, and the reliability of chip packaging is ensured under the condition of not changing the thickness of the packaging structure of the chip.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a cross-sectional view of a chip package in the prior art;
FIG. 2 is a schematic cross-sectional view of a prior art injection of a filler material between a chip and a circuit board;
FIG. 3 is a schematic top view of a prior art injection of a fill material between a chip and a circuit board;
FIG. 4 is a schematic cross-sectional view of a prior art method for forming a hole between a chip and a circuit board;
FIG. 5 is a schematic top view of a prior art method for forming a hole between a chip and a circuit board;
fig. 6 is a first cross-sectional view of a chip package structure according to an embodiment of the invention;
fig. 7 is a second cross-sectional view of a chip package structure according to an embodiment of the invention;
fig. 8 is a third schematic cross-sectional view of a chip package structure according to an embodiment of the invention;
FIG. 9 is a schematic cross-sectional view of an embodiment of the present invention showing a filling material injected between the chip and the circuit board;
FIG. 10 is a schematic cross-sectional view of a filling material filled between a chip and a circuit board according to an embodiment of the present invention;
FIG. 11 is a schematic top view of a filling material filled between a chip and a circuit board according to an embodiment of the present invention;
FIG. 12 is an extension of the second groove according to the present invention;
fig. 13 is another extension of the second groove according to the embodiment of the present invention.
Reference numerals:
1-a circuit board, 10-a bonding pad,
2-chip, 20-pin,
3-a filling material, 4-a conductive part,
40-tin balls, 5-holes,
61-first groove, 62-second groove,
63-third groove, 64-fourth groove.
Detailed Description
In order to further explain the chip packaging structure, the chip packaging method, and the display device provided by the embodiments of the present invention, the following detailed description is made with reference to the accompanying drawings.
As shown in fig. 1, when the chip 2 is packaged on the circuit board 1, the chip 2 is generally packaged in a chip packaging area on the circuit board 1, the chip packaging area includes pads 10 corresponding to the pins 20 in the chip 2 one by one, during packaging, a solder ball 40 is firstly deposited on the pin 20 of the chip 2, then one side of the chip 2 where the pin 20 is formed faces the circuit board 1, each pin 20 in the chip 2 is in contact with the corresponding pad 10 on the circuit board 1, and then the solder ball 40 between the pin 20 and the pad 10 is heated, so as to realize the electrical connection between the pin 20 and the corresponding pad 10; as shown in fig. 2 and 3, an underfill operation is then performed, in which the filling material 3 is injected between the chip 2 and the circuit board 1 from one side of the chip 2 by a syringe, and the filling material 3 flows between the chip 2 and the circuit board 1 from one side of the chip 2 until the entire space between the chip 2 and the circuit board 1 is filled.
As shown in fig. 4 and 5, with the enhancement of the transmission capability of the chip 2, the number of the pins 20 of the chip 2 is increased, so that after the chip 2 is combined with the circuit board 1, the densities of the pins 20, the pads 10 and the solder balls 40 between the chip 2 and the circuit board 1 are increased, and the resistance received by the filling material 3 in the flowing process is increased, and because the flowing speed of the filling material 3 in the edge area of the chip 2 is high, the flowing speed of the resistance received by the pins 20, the pads 10 and the solder balls 40 in the middle area of the chip 2 is low, the holes 5 are easily generated in the middle area of the packaged chip 2, and the reliability of the package of the chip 2 is seriously affected.
In order to solve the above problem, the inventors of the present invention have studied and found that the above problem can be solved by increasing the accommodating space formed between the chip 2 and the circuit board 1, in which the filling material 3 is accommodated. Specifically, referring to fig. 6-8 and 10, an embodiment of the present invention provides a chip package structure, including: a circuit board 1, a chip 2 and a filling material 3; the chip packaging area of the circuit board 1 comprises a plurality of pads 10 arranged at intervals; the chip 2 is arranged in a chip packaging area of the circuit board 1, the chip 2 comprises a plurality of pins 20 which are in one-to-one correspondence with the plurality of bonding pads 10, orthographic projections of the pins 20 on the circuit board 1 are at least partially overlapped with orthographic projections of the corresponding bonding pads 10 on the circuit board 1, and the pins 20 are electrically connected with the corresponding bonding pads 10 to form a conductive part 4; the filling material 3 is filled between the chip 2 and the circuit board 1; in the area of the circuit board 1 corresponding to the gap between the adjacent conductive parts 4, at least part of the area is provided with a first groove 61; and/or, in the area of the chip 2 corresponding to the gap between the adjacent conductive parts 4, at least a partial area is provided with a second groove 62.
Specifically, when the chip 2 is packaged on the circuit board 1, the solder balls 40 are firstly deposited on the pins 20 of the chip 2, then one side of the chip 2, where the pins 20 are formed, is opposite to one side of the circuit board 1, where the pads 10 are formed, so that each pin 20 in the chip 2 is in contact with a corresponding pad 10 on the circuit board 1, and then the solder balls 40 between the pins 20 and the pads 10 are heated, so that the pins 20 are electrically connected with the corresponding pads 10 to form the conductive part 4, and the conductive part 4 can realize signal transmission between the chip 2 and the circuit board 1; since the leads 20 protrude from the chip 2 and the pads 10 protrude from the circuit board 1, after the leads 20 are electrically connected to the corresponding chip 2 to form the conductive portions 4, an accommodating space surrounding each conductive portion 4 is formed between the chip 2 and the circuit board 1, as shown in fig. 9, a filling material 3 flowing between the chip 2 and the circuit board 1 is injected by an injector, and after the filling material 3 fills up the gap between the circuit board 1 and the chip 2, the filling material 3 is cured, thereby completing the packaging of the chip 2 on the circuit board 1.
According to the specific structure and the packaging process of the chip packaging structure, in the chip packaging structure provided by the embodiment of the invention, at least part of the area of the circuit board 1 corresponding to the gap between the adjacent conductive parts 4 is provided with a first groove 61; and/or, in the area of the chip 2 corresponding to the gap between the adjacent conductive parts 4, at least partial area is provided with a second groove 62; the containing space formed between the chip 2 and the circuit board 1 is increased in the direction perpendicular to the circuit board 1 (as shown in fig. 6-8, the height L of the containing space in the direction perpendicular to the circuit board 1 is increased), that is, the flow space of the filling material 3 is increased in the direction perpendicular to the circuit board 1 in the middle area of the chip 2, according to the parallel plate theory, when the filling material 3 is filled between the chip 2 and the circuit board 1, the resistance of the filling material 3 in the middle area of the chip 2 is reduced, the filling material 3 has a faster flow speed in the middle area of the chip 2, so that the filling material 3 can be more uniform, the underfill process can be completed more quickly, holes are effectively prevented from being generated in the middle area of the chip 2, and the reliability of packaging the chip 2 is ensured.
In addition, the flowing speed of the filling material 3 in the chip 2 and the circuit board 1 is increased, so that the filling efficiency of the filling material 3 is improved, and the production efficiency of the chip packaging structure is improved better.
In addition, in the chip packaging structure provided by the embodiment of the invention, the accommodating space formed between the chip 2 and the circuit board 1 is enlarged by forming the groove, and the packaging reliability of the chip 2 is ensured under the condition that the thickness of the chip packaging structure is not changed.
It should be noted that the parallel plate theory refers to: when the space formed by the upper and lower parallel plates is filled with the material having fluidity, when the distance between the upper and lower parallel plates increases, the resistance to the flow of the material having fluidity between the upper and lower flat plates decreases, thereby enabling the material having fluidity to be filled more quickly and uniformly between the upper and lower flat plates.
Further, the circuit board 1 is provided with a first groove 61 corresponding to the whole area of the gap between the adjacent conductive parts 4; and/or the chip 2 is provided with a second recess 62 for the whole area of the gap between the adjacent conductive parts 4.
Specifically, as shown in fig. 10 and 11, a first groove 61 is disposed in all the areas of the circuit board 1 corresponding to the gaps between the adjacent conductive parts 4, and/or a second groove 62 is disposed in all the areas of the chip 2 corresponding to the gaps between the adjacent conductive parts 4, so that the accommodating space formed between the chip 2 and the circuit board 1 is increased to a greater extent in the direction perpendicular to the circuit board 1, and thus when the filling material 3 is filled between the chip 2 and the circuit board 1, the resistance of the filling material 3 in the middle area of the chip 2 is further reduced, the flow speed of the filling material 3 in the middle area of the chip 2 and the uniformity of the flow are further improved, thereby more effectively avoiding the generation of holes in the middle area of the chip 2, and ensuring the reliability of the package of the chip 2.
The sizes and specific arrangement of the first groove 61 and the second groove 62 mentioned in the above embodiments are various, and in some embodiments, the first groove 61 may be arranged to extend in the flow direction when the filling material 3 is filled between the chip 2 and the circuit board 1; or the first groove 61 extends in a direction perpendicular to the flow direction when the filling material 3 is filled between the chip 2 and the circuit board 1; and/or, as shown in fig. 13, the second groove 62 extends in the flow direction when the filling material 3 is filled between the chip 2 and the circuit board 1; as shown in fig. 12, or the second groove 62 extends in a direction perpendicular to the flow direction when the filling material 3 is filled between the chip 2 and the circuit board 1.
Specifically, when the first groove 61 and/or the second groove 62 are provided to extend in the flow direction when the filling material 3 is filled between the chip 2 and the circuit board 1, it is possible to more facilitate the rapid flow of the filling material 3, thereby achieving efficient filling. When the first groove 61 and/or the second groove 62 are/is arranged to extend in a direction perpendicular to the flow direction of the filling material 3 filled between the chip 2 and the circuit board 1, the filling material 3 can be more favorably and uniformly diffused between the chip 2 and the circuit board 1, and the filling uniformity can be better ensured.
Preferably, the first groove 61 may be provided to extend in a flow direction when the filling material 3 is filled between the chip 2 and the circuit board 1, and at the same time, the second groove 62 may be provided to extend in a direction perpendicular to the flow direction when the filling material 3 is filled between the chip 2 and the circuit board 1; alternatively, the first groove 61 may be provided to extend in a direction perpendicular to the flow direction when the filling material 3 is filled between the chip 2 and the circuit board 1, and at the same time, the second groove 62 may be provided to extend in the flow direction when the filling material 3 is filled between the chip 2 and the circuit board 1; above-mentioned two kinds of setting mode more are favorable to quick, the even packing of filler material 3 between chip 2 and circuit board 1, the reliability and the encapsulation efficiency of promotion chip 2 encapsulation that can be better.
Further, the width of the first groove 61 in the direction perpendicular to the extending direction thereof may be set to be equal to the distance between the pads 10 located on both sides of the first groove 61 in the direction perpendicular to the extending direction of the first groove 61; and/or the width of the second groove 62 perpendicular to the extending direction of the second groove 62 is equal to the distance between the pins 20 positioned at two sides of the second groove 62 in the extending direction of the second groove 62.
Specifically, above-mentioned mode of setting up can make first recess 61 and second recess 62 have the biggest width for the accommodation space maximize that forms between chip 2 and circuit board 1, thereby filler material 3 when flowing in accommodation space, the resistance furthest's that receives reduces, filler material 3 is at the flow velocity of the middle zone of chip 2, and the effectual promotion of homogeneity that flows, thereby more effectively avoided producing the hole at the middle zone of chip 2, guaranteed the reliability of chip 2 encapsulation.
Further, as shown in fig. 6 to 8, the circuit board 1 provided in the above embodiment is provided with a third groove 63 around the peripheral area of all the conductive parts 4; and/or a fourth recess 64 is provided in the chip 2 around the perimeter area of all the conductive parts 4.
Specifically, above-mentioned mode of setting up can make the marginal zone at chip 2 in the direction of perpendicular to circuit board 1, filling material 3's flow space grow, make filling material 3 when flowing in by the marginal zone of chip 2, in the direction of perpendicular to circuit board 1, filling material 3's flow distance increases, thereby the speed of filling material 3 when marginal zone flows in has been slowed down, the speed that makes filling material 3 fill whole accommodation space becomes more even, thereby make filling material 3 can be more even, quick completion underfill process, thereby effectively avoided producing the hole at the middle zone of chip 2, the reliability of chip 2 encapsulation has been guaranteed.
Further, as shown in fig. 6 to 8, the depths of the first groove 61, the second groove 62, the third groove 63 and the fourth groove 64 provided in the above embodiments may be set according to actual needs, for example, the depths H of the first groove 61 and the third groove 63 in the direction perpendicular to the circuit board 1 are both between 1/3H and 1/2H, where H is the thickness of the circuit board 1; and/or the depth D of the second groove 62 and the fourth groove 64 in the direction vertical to the circuit board 1 is between 1/3D and 1/2D, and D is the thickness of the chip 2 in the direction vertical to the circuit board 1.
Specifically, setting the depths of the first groove 61, the second groove 62, the third groove 63, and the fourth groove 64 within the above-described ranges not only increases the accommodation space formed between the chip 2 and the circuit board 1 to a large extent in the direction perpendicular to the circuit board 1, but also does not adversely affect the workability of the chip 2 and the circuit board 1. The packaging structure of the chip ensures good working performance and better ensures the packaging reliability of the chip 2.
The embodiment of the invention also provides a display device which comprises the packaging structure of the chip provided by the embodiment.
Because the packaging structure of the chip provided by the embodiment has high reliability and good working performance, the display device provided by the embodiment of the invention can also realize good working performance and good reliability when the packaging structure of the chip provided by the embodiment is included.
The embodiment of the invention also provides a chip packaging method, which is used for realizing the chip packaging structure provided by the embodiment, and the packaging method comprises the following steps:
manufacturing a circuit board 1, wherein a plurality of bonding pads 10 are arranged at intervals in a chip packaging area of the circuit board 1;
manufacturing a chip 2, wherein the chip 2 comprises a plurality of pins 20 which correspond to a plurality of bonding pads 10 one by one;
the steps of manufacturing a circuit board 1 specifically include: manufacturing a first groove 61 in at least partial area of the circuit board 1 corresponding to the gap between the adjacent welding pads 10; and/or, the step of manufacturing a chip 2 specifically comprises: manufacturing a second groove 62 in at least partial area of the chip 2 corresponding to the gap between the adjacent pins 20;
welding the chip 2 on a chip packaging area of the circuit board 1, so that the orthographic projection of the pin 20 on the circuit board 1 is at least partially overlapped with the orthographic projection of the corresponding pad 10 on the circuit board 1, and the pin 20 is electrically connected with the corresponding pad 10 to form a conductive part 4;
a flowing filling material 3 is injected between the chip 2 and the circuit board 1, and after the filling material 3 fills the gap between the circuit board 1 and the chip 2, the filling material 3 is cured.
Specifically, when the circuit board 1 is manufactured, a plurality of bonding pads 10 arranged at intervals are manufactured in a chip packaging area of the circuit board 1, and the bonding pads 10 are all bumps protruding out of the circuit board 1; when the chip 2 is manufactured, the chip 2 can be a flip chip, and a plurality of pins 20 manufactured on the chip 2 are all bumps protruding out of the chip 2; moreover, when the circuit board 1 is manufactured, the first groove 61 can be manufactured in at least partial area of the circuit board 1 corresponding to the gap between the adjacent pads 10; and/or, when the chip 2 is manufactured, the second groove 62 can be manufactured in at least partial area of the chip 2 corresponding to the gap between the adjacent pins 20; then depositing solder balls 40 on the pins 20 of the chip 2, making the side of the chip 2 where the pins 20 are formed opposite to the side of the circuit board 1 where the pads 10 are formed, making each pin 20 in the chip 2 contact with the corresponding pad 10 on the circuit board 1, and then heating the solder balls 40 between the pins 20 and the pads 10, so that the pins 20 and the corresponding pads 10 are electrically connected to form a conductive part 4, wherein the conductive part 4 can realize signal transmission between the chip 2 and the circuit board 1; since the leads 20 protrude from the chip 2 and the pads 10 protrude from the circuit board 1, after the leads 20 are electrically connected with the corresponding chip 2 to form the conductive parts 4, an accommodating space surrounding each conductive part 4 is formed between the chip 2 and the circuit board 1, a flowing filling material 3 is injected between the chip 2 and the circuit board 1 by using an injector, and after the filling material 3 fills up a gap between the circuit board 1 and the chip 2, the filling material 3 is cured, so that the chip 2 is packaged on the circuit board 1.
In the chip packaging method provided by the embodiment of the invention, a first groove 61 is formed in at least partial area in the area of the circuit board 1 corresponding to the gap between the adjacent conductive parts 4; and/or, in the area of the chip 2 corresponding to the gap between the adjacent conductive parts 4, at least partial area forms a second groove 62; make the accommodation space that forms between chip 2 and circuit board 1 increase in the direction of perpendicular to circuit board 1, make the middle zone at chip 2 in the direction of perpendicular to circuit board 1 promptly, filling material 3's flow space grow, according to the parallel flat plate theory, when filling material 3 between chip 2 and circuit board 1, filling material 3 reduces at the middle zone resistance that receives of chip 2, filling material 3 has faster flow velocity in the middle zone of chip 2, thereby make filling material 3 can be more even, the more quick completion underfill process, effectively avoided producing the hole in the middle zone of chip 2, the reliability of chip 2 encapsulation has been guaranteed.
In addition, the flow speed of the filling material 3 in the chip 2 and the circuit board 1 is increased, so that the filling efficiency of the filling material 3 is improved, and the packaging efficiency of the chip 2 is improved better.
In addition, in the chip packaging method provided by the embodiment of the invention, the accommodating space formed between the chip 2 and the circuit board 1 is enlarged by forming the groove, and the packaging reliability of the chip 2 is ensured under the condition that the thickness of the packaging structure of the chip is not changed.
Further, the steps of manufacturing the circuit board 1 provided in the above embodiment further include: a third groove 63 is formed in the peripheral area of the circuit board 1 surrounding all the bonding pads 10; and/or, the step of manufacturing a chip 2 further comprises: a fourth recess 64 is made in the peripheral region of the chip 2 around all the pins 20.
Specifically, the third groove 63 and the first groove 61 may be formed in the same patterning process, the fourth groove 64 and the second groove 62 may be formed in the same patterning process, and the third groove 63 and the fourth groove 64 may surround all the conductive portions 4 formed between the chip 2 and the circuit board 1.
The third groove 63 is arranged on the circuit board 1, and the fourth groove 64 is arranged on the chip 2, so that the edge area of the chip 2 is in the direction perpendicular to the circuit board 1, the flowing space of the filling material 3 is enlarged, when the edge area of the chip 2 flows in, the filling material 3 is in the direction perpendicular to the circuit board 1, the flowing distance of the filling material 3 is increased, the flowing speed of the filling material 3 in the edge area is reduced, the speed of the filling material 3 for filling the whole accommodating space is more uniform, the filling material 3 can more uniformly and quickly complete the underfill process, holes are effectively prevented from being generated in the middle area of the chip 2, and the packaging reliability of the chip 2 is ensured.
In some embodiments, the step of forming the first groove 61 and the third groove 63 on the circuit board 1 may specifically include:
forming a first photoresist on one side of the circuit board 1 where the pad 10 is formed;
exposing the first photoresist to form a first photoresist reserved region and a first photoresist removed region, wherein the first photoresist removed region corresponds to the regions where the first groove 61 and the third groove 63 are located, and the first photoresist reserved region corresponds to other regions except the regions where the first groove 61 and the third groove 63 are located;
developing the exposed first photoresist, and removing the first photoresist in the first photoresist removing area;
the circuit board 1 located in the first photoresist removal region is etched to form a first groove 61 and a third groove 63.
Specifically, a first photoresist may be formed by coating on one side of the circuit board 1 where the pad 10 is formed, and then the first photoresist is exposed by using a mask including a light-transmitting region and a light-shielding region to form a first photoresist remaining region and a first photoresist removing region, where the first photoresist removing region corresponds to regions where the first groove 61 and the third groove 63 are located, and the first photoresist remaining region corresponds to other regions except the regions where the first groove 61 and the third groove 63 are located; and developing the exposed first photoresist by using a developing solution to remove the first photoresist in the first photoresist removing region, exposing the circuit board 1 in the first photoresist removing region, and finally etching the circuit board 1 in the first photoresist removing region to form a first groove 61 and a third groove 63.
It should be noted that, when the circuit board 1 is etched, the circuit board 1 may be etched by a wet etching process, but is not limited thereto. In addition, when the circuit board 1 is etched, the conductive film layer in the circuit board 1 is prevented from being etched, that is, the circuit board 1 still has stable working performance after the circuit board 1 is etched.
In some embodiments, the step of forming the second groove 62 and the fourth groove 64 on the chip 2 specifically includes:
forming a second photoresist on the side of the chip 2 where the leads 20 are formed;
exposing the second photoresist to form a second photoresist reserved region and a second photoresist removed region, wherein the second photoresist removed region corresponds to the regions where the second groove 62 and the fourth groove 64 are located, and the second photoresist reserved region corresponds to other regions except the regions where the second groove 62 and the fourth groove 64 are located;
developing the exposed second photoresist, and removing the second photoresist in the second photoresist removing area;
the chip 2 located in the second photoresist removal region is etched to form a second groove 62 and a fourth groove 64.
Specifically, a second photoresist may be formed by coating on the side of the chip 2 where the leads 20 are formed, and then the second photoresist is exposed by using a mask including a light-transmitting region and a light-shielding region, so as to form a second photoresist remaining region and a second photoresist removing region, where the second photoresist removing region corresponds to the regions where the second groove 62 and the fourth groove 64 are located, and the second photoresist remaining region corresponds to the other regions except the regions where the second groove 62 and the fourth groove 64 are located; and then developing the exposed second photoresist by using a developing solution to remove the second photoresist in the second photoresist removal region, exposing the chip 2 in the second photoresist removal region, and finally etching the chip 2 in the second photoresist removal region to form a second groove 62 and a fourth groove 64.
It should be noted that, when etching the chip 2, the chip 2 may be etched by using a dry etching process, but is not limited thereto. In addition, when the chip 2 is etched, the conductive film layer in the chip 2 is prevented from being etched, that is, the chip 2 still has stable working performance after the chip 2 is etched.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A package structure for a chip, comprising:
the chip packaging region of the circuit board comprises a plurality of welding pads which are arranged at intervals;
the chip is arranged in the chip packaging area and comprises a plurality of pins which are in one-to-one correspondence with the bonding pads, the orthographic projections of the pins on the circuit board are at least partially overlapped with the orthographic projections of the corresponding bonding pads on the circuit board, and the pins are electrically connected with the corresponding bonding pads to form a conductive part;
a filling material filled between the chip and the circuit board;
the circuit board is characterized in that a first groove is formed in at least partial area of the circuit board corresponding to the gap between the adjacent conductive parts; and/or the presence of a gas in the gas,
at least part of the area of the chip corresponding to the gap between the adjacent conductive parts is provided with a second groove;
the first groove is formed on the surface of the part of the circuit board bearing the bonding pad;
the second groove is formed on the surface of the part of the chip bearing the pins;
at least part of the openings of the first grooves are opposite to the openings of the second grooves.
2. The chip package structure according to claim 1, wherein the circuit board is provided with a first groove corresponding to all regions of the gap between the adjacent conductive portions; and/or the presence of a gas in the gas,
and second grooves are formed in all the areas of the chip corresponding to the gaps between the adjacent conductive parts.
3. The chip package structure of claim 1,
the first groove extends along a flow direction when the filling material is filled between the chip and the circuit board; or the first groove extends along a direction perpendicular to a flow direction when the filling material is filled between the chip and the circuit board;
and/or the presence of a gas in the gas,
the second groove extends along a flow direction when the filling material is filled between the chip and the circuit board; or the second groove extends in a direction perpendicular to a flow direction when the filling material is filled between the chip and the circuit board.
4. The chip package structure of claim 3,
the width of the first groove in the direction perpendicular to the extending direction of the first groove is equal to the distance between the pads on two sides of the first groove in the direction perpendicular to the extending direction of the first groove; and/or the presence of a gas in the gas,
the width of the second groove in the direction perpendicular to the extending direction of the second groove is equal to the distance between the pins on two sides of the second groove in the direction perpendicular to the extending direction of the second groove.
5. The chip package structure according to any one of claims 1 to 4,
the circuit board is provided with a third groove around the peripheral area of all the conductive parts; and/or the presence of a gas in the gas,
the chip is provided with a fourth groove around the peripheral area of all the conductive parts.
6. The chip package structure of claim 5,
the depths of the first groove and the third groove in the direction vertical to the circuit board are both 1/3H-1/2H, and H is the thickness of the circuit board; and/or the presence of a gas in the gas,
the depth of the second groove and the depth of the fourth groove in the direction vertical to the circuit board are both 1/3D-1/2D, and D is the thickness of the chip in the direction vertical to the circuit board.
7. A display device comprising the chip package according to any one of claims 1 to 6.
8. A method for packaging a chip, comprising:
manufacturing a circuit board, wherein a plurality of bonding pads are arranged in a chip packaging area of the circuit board at intervals;
manufacturing a chip, wherein the chip comprises a plurality of pins which are in one-to-one correspondence with the bonding pads;
the step of manufacturing a circuit board specifically comprises: manufacturing a first groove in at least partial area of the circuit board corresponding to the gap between the adjacent welding plates; and/or the step of manufacturing a chip specifically comprises: manufacturing a second groove in at least partial region of the chip corresponding to the gap between the adjacent pins; the first groove is formed on the surface of the part of the circuit board bearing the bonding pad; the second groove is formed on the surface of the part of the chip bearing the pins; at least part of the openings of the first grooves are opposite to the openings of the second grooves;
welding the chip on a chip packaging area of the circuit board, so that the orthographic projection of the pin on the circuit board is at least partially overlapped with the orthographic projection of the corresponding pad on the circuit board, and the pin is electrically connected with the corresponding pad to form a conductive part;
injecting a flowing filling material between the chip and the circuit board, and curing the filling material after the filling material fills the gap between the circuit board and the chip.
9. The method for packaging a chip according to claim 8, wherein the step of fabricating a circuit board further comprises:
manufacturing a third groove in the peripheral area of the circuit board surrounding all the bonding pads;
and/or the presence of a gas in the gas,
the step of fabricating a chip further comprises:
and manufacturing a fourth groove in the peripheral area of the chip surrounding all the pins.
10. The chip packaging method according to claim 9, wherein the step of forming the first groove and the third groove on the circuit board specifically comprises:
forming a first photoresist on one side of the circuit board on which the bonding pad is formed;
exposing the first photoresist to form a first photoresist reserved region and a first photoresist removed region, wherein the first photoresist removed region corresponds to the regions where the first groove and the third groove are located, and the first photoresist reserved region corresponds to other regions except the regions where the first groove and the third groove are located;
developing the exposed first photoresist, and removing the first photoresist in the first photoresist removing area;
etching the circuit board in the first photoresist removing area to form the first groove and the third groove;
the step of forming the second groove and the fourth groove on the chip specifically includes:
forming a second photoresist on one side of the chip on which the pins are formed;
exposing the second photoresist to form a second photoresist reserved region and a second photoresist removed region, wherein the second photoresist removed region corresponds to the region where the second groove and the fourth groove are located, and the second photoresist reserved region corresponds to other regions except the region where the second groove and the fourth groove are located;
developing the exposed second photoresist, and removing the second photoresist in the second photoresist removing area;
and etching the chip positioned in the second photoresist removing area to form the second groove and the fourth groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811399916.3A CN109545754B (en) | 2018-11-22 | 2018-11-22 | Chip packaging structure, chip packaging method and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811399916.3A CN109545754B (en) | 2018-11-22 | 2018-11-22 | Chip packaging structure, chip packaging method and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109545754A CN109545754A (en) | 2019-03-29 |
| CN109545754B true CN109545754B (en) | 2021-01-26 |
Family
ID=65849335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811399916.3A Active CN109545754B (en) | 2018-11-22 | 2018-11-22 | Chip packaging structure, chip packaging method and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109545754B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023042615A1 (en) * | 2021-09-14 | 2023-03-23 | ローム株式会社 | Semiconductor device and mounting structure for semiconductor element |
| CN115023024B (en) * | 2021-09-26 | 2023-10-20 | 荣耀终端有限公司 | Circuit board and electronic equipment |
| CN115090981A (en) * | 2022-06-29 | 2022-09-23 | 中机智能装备创新研究院(宁波)有限公司 | Grain wear-resistant coating brazing preparation method and preparation device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288451B1 (en) * | 1998-06-24 | 2001-09-11 | Vanguard International Semiconductor Corporation | Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength |
| US6750546B1 (en) * | 2001-11-05 | 2004-06-15 | Skyworks Solutions, Inc. | Flip-chip leadframe package |
| WO2008111345A1 (en) * | 2007-03-09 | 2008-09-18 | Nec Corporation | Electronic device, and electronic device manufacturing method |
| US20090160039A1 (en) * | 2007-12-20 | 2009-06-25 | National Semiconductor Corporation | Method and leadframe for packaging integrated circuits |
| CN103531560A (en) * | 2013-10-31 | 2014-01-22 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging structure and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3491827B2 (en) * | 2000-07-25 | 2004-01-26 | 関西日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JP2006222126A (en) * | 2005-02-08 | 2006-08-24 | Murata Mfg Co Ltd | Circuit board |
| JP2013131508A (en) * | 2010-04-06 | 2013-07-04 | Murata Mfg Co Ltd | Electronic device |
| CN103633037A (en) * | 2012-08-27 | 2014-03-12 | 国碁电子(中山)有限公司 | Encapsulation structure and manufacturing method thereof |
-
2018
- 2018-11-22 CN CN201811399916.3A patent/CN109545754B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288451B1 (en) * | 1998-06-24 | 2001-09-11 | Vanguard International Semiconductor Corporation | Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength |
| US6750546B1 (en) * | 2001-11-05 | 2004-06-15 | Skyworks Solutions, Inc. | Flip-chip leadframe package |
| WO2008111345A1 (en) * | 2007-03-09 | 2008-09-18 | Nec Corporation | Electronic device, and electronic device manufacturing method |
| US20090160039A1 (en) * | 2007-12-20 | 2009-06-25 | National Semiconductor Corporation | Method and leadframe for packaging integrated circuits |
| CN103531560A (en) * | 2013-10-31 | 2014-01-22 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109545754A (en) | 2019-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109545754B (en) | Chip packaging structure, chip packaging method and display device | |
| CN101578695B (en) | Semiconductor element mounting structure and semiconductor element mounting method | |
| CN103715150B (en) | Die cap and the Flip-Chip Using with die cap | |
| US6210992B1 (en) | Controlling packaging encapsulant leakage | |
| KR20130071792A (en) | Pcb(printed circuit board) for muf(molded underfill) and molding structure of the same pcb | |
| US20100271792A1 (en) | Electronic component package and method of manufacturing the same | |
| JP2907188B2 (en) | Semiconductor device, method of mounting semiconductor device, and method of manufacturing semiconductor device | |
| JP7189672B2 (en) | Semiconductor device and its manufacturing method | |
| TWI452660B (en) | Flip-chip molded package having non-array bumps | |
| JP2009177061A (en) | Semiconductor apparatus and method of manufacturing the same | |
| JP2006100385A (en) | Semiconductor device | |
| KR101778395B1 (en) | Semiconductor package using 3D printing | |
| JP2005085931A (en) | Semiconductor chip and circuit board for its mounting | |
| TWI613776B (en) | Heat sink and chip package having the same | |
| CN114823573B (en) | Heat dissipation type packaging structure and forming method thereof | |
| KR100963151B1 (en) | Mold for manufacturing semiconductor package and method for molding using the same | |
| US20210366798A1 (en) | Packaged structure and forming method thereof | |
| KR20120032764A (en) | Substrate for flip chip package and method of manufacturing flip chip package using the same | |
| KR20220063837A (en) | Semiconductor package | |
| KR102494595B1 (en) | Semiconductor package | |
| JP2007220740A (en) | Semiconductor device and manufacturing method thereof | |
| TWI713167B (en) | Flip-chip semiconductor package and packaging method thereof | |
| TWI567910B (en) | Chip on film package and film packaging substrate | |
| JP4828997B2 (en) | SEMICONDUCTOR PACKAGE AND ITS MOUNTING METHOD, AND INSULATED WIRING BOARD USED FOR THE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD | |
| CN108133924B (en) | Semiconductor chip packaging structure and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |