CN109524457A - 半导体装置 - Google Patents
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- CN109524457A CN109524457A CN201710854658.2A CN201710854658A CN109524457A CN 109524457 A CN109524457 A CN 109524457A CN 201710854658 A CN201710854658 A CN 201710854658A CN 109524457 A CN109524457 A CN 109524457A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 241000270295 Serpentes Species 0.000 claims abstract description 7
- 238000005452 bending Methods 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 description 23
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000012212 insulator Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Abstract
本发明公开一种半导体装置,包括一基板、一主动层、一接触区以及一栅极结构。主动层配置于基板之上,且主动层具有一源极区及一漏极区。接触区配置于基板之上。栅极结构配置于主动层之上,其中栅极结构包括一中间部分及一侧边部分,侧边部分连接于中间部分,且侧边部分是蛇型。
Description
技术领域
本发明涉及一种半导体装置,且特别是涉及一种硅晶绝缘体(SOI)的半导体装置。
背景技术
近年来,由于硅晶绝缘体(Silicon On Insulator,SOI)的半导体装置具备低功耗及高效能的优点,需求更是日益增加。在半导体装置的制造过程中,会将掺杂物施加于此硅晶绝缘体的半导体装置的栅极中。然而,当过多的掺杂物扩散至半导体装置的栅极工作部分(垂直部分)时,此半导体装置的效能会变差。
发明内容
本发明是有关于一种半导体装置,其栅极结构的侧边部分为蛇型(上下各一),具有多个弯折部分,因此在对半导体装置进行掺杂的过程中,同等尺寸要求下,能够延长掺杂物扩散进入栅极结构的路径,防止高浓度的掺杂物快速扩散至栅极结构的工作部分,降低掺杂物对于栅极的工作区的干扰,进而提升半导体装置的效能。
根据本发明,提出一种半导体装置。此半导体装置包括一基板、一主动层、一接触区以及一栅极结构。主动层配置于基板之上,且主动层具有一源极区及一漏极区。接触区配置于基板之上。栅极结构配置于主动层之上,其中栅极结构包括一中间部分及一侧边部分,侧边部分连接于中间部分,且侧边部分是蛇型。
为了对本发明的上述及其他方面有更佳的了解,下文特举实施例,并配合附图详细说明如下:
附图说明
图1为本发明一实施例的半导体装置上视图;
图2A为沿着图1的半导体装置的A-A连线的剖视图;
图2B为沿着图1的半导体装置的B-B连线的剖视图;
图2C为沿着图1的半导体装置的C-C连线的剖视图。
具体实施方式
本发明提供一种半导体装置,其栅极结构的侧边部分为蛇型,具有多个弯折部分,因此在对半导体装置进行掺杂以形成工作器件的过程中,能够延长掺杂物扩散进入栅极结构的中间部分的路径,防止高浓度的掺杂物由于退火处理而快速扩散至栅极结构的中间部分,降低掺杂物对于栅极的工作区的干扰,进而提升半导体装置的效能。
图1绘示根据本发明一实施例的半导体装置100上视图。本发明的半导体装置100可应用于P型金属氧化物半导体(PMOS)或N型金属氧化物半导体(NMOS)。
图2A绘示沿着图1的半导体装置的A-A连线的剖视图。
请同时参照图1及图2A,在基板110上形成由绝缘层120及主动层142所构成的硅晶绝缘体(Silicon On Insulator,SOI)层之后,可在硅晶绝缘体层上形成栅极结构160。形成栅极结构160之后,可在硅晶绝缘体层上形成接触区146。
基板110可以是P型硅基板。绝缘层120可以是氧化硅层,内埋于基板110与主动层142之间。主动层146配置于基板110之上,可具有源极区142S及漏极区142D。源极区142S及漏极区142D分别掺杂有第一导电型的掺杂物,例如是P型。接触区146配置于基板110之上,可掺杂有第二导电型的掺杂物,例如是N型。源极区142S及漏极区142D的导电型是不同于接触区146的导电型。栅极结构160配置于主动层142上,可由多晶硅所形成,且厚度在50nm~250nm的范围中。其中,栅极结构160与主动层142之间可具有一氧化层(未绘示),亦即是氧化层可配置于主动层142上,栅极结构160可配置于氧化层上。
在形成接触区的过程中,是对于主动层进行高浓度的离子掺杂,若此高浓度掺杂物的接触区过于接近栅极结构的中间区域,恐造成过多掺杂物扩散至栅极结构的工作区域而影响半导体元件的效能;若此高浓度掺杂物的接触区完全与栅极结构隔开(亦即是接触区远离于栅极结构),恐造成基板的电阻上升。
请参照图1,栅极结构160包括一侧边部分161及一中间部分162。中间部分162对应于源极区142S及漏极区142D之间的通道区域。中间部分162为长条状,侧边部分161指的是连接于中间部分的部分。中间部分162是形成在2个侧边部分161之间。中间部分162沿X方向上具有一宽度W1,沿Y方向上具有一长度L1。宽度W1的范围是40nm~500nm,长度L1的范围是0.5μm~50μm。栅极结构160的侧边部分161为蛇型,例如是具有蜿蜒(zigzag)的图案。进一步而言,栅极结构160的侧边部分161与中间部分162并不会共同形成H型或T型,栅极结构160的侧边部分161具有至少一弯折部分于主动层142上,接触区146的掺杂物并不会直线扩散至中间部分162,而是要经过弯折部才能扩散至中间部分162(如图1的扩散路径P所示),故相较于栅极结构的侧边部分与中间部分共同形成H型或T型的比较例而言,本发明的半导体装置中,不但栅极结构160与接触区146的扩散边界(margin)减少,掺杂物扩散的路径也增长,故扩散至栅极结构160的中间部分162的掺杂物(其导电型例如是相反于源极区142S及漏极区142D的导电型)的浓度会大幅降低。
在本实施例中,栅极结构160的侧边部分161包括一第一部分1611、连接于第一部分1611的一第二部分1612、连接于第二部分1612的一第三部分1613、连接于第三部分1613的一第四部分1614以及连接于第四部分1614的一第五部分1615。其中第三部分1613连接于中间部分162,第一部分1611、第三部分1613及第五部分1615是分别朝一第一方向延伸,第二部分1612及第四部分1614是分别朝一第二方向延伸,第一方向不同于第二方向。在本实施例中,第一方向例如是X方向,第二方向例如是Y方向,第一方向与第二方向彼此垂直。然而本发明并不以此为限,第一方向与第二方向可以不相互垂直。在图1的上视图中,半导体装置100具有一中心线Lc,半导体装置100可沿着中心线Lc形成上下对称的结构。在本实施例中,中心线Lc是沿着X方向(例如是水平方向)延伸。其中,第一部分1611与半导体装置100的中心线Lc之间具有一第一距离D1,第三部分1613与半导体装置100的中心线Lc之间具有一第二距离D2,第一距离D1不同于第二距离D2。更确切地说,第一距离D1是大于第二距离D2。由于第一距离D1不同于第二距离D2,栅极结构160不为H型或T型,扩散至栅极结构160的中间部分162的掺杂物浓度能够减少。
在本实施例中,栅极结构160具有四个弯折部分,第一弯折部分1601是由第一部分1611与第二部分1612所形成,第二弯折部分1602是由第二部分1612与第三部分1613所形成,第三弯折部分1603是由第三部分1613与第四部分1614所形成,第四弯折部分1604是由第四部分1614与第五部分1615所形成。四个弯折部分所形成的角度可分别为90°,然而本发明并不以此为限。
请同时参照图1及图2A,接触区146理论上应与栅极结构相当靠近但会彼此错开,然而在形成接触区146的过程中,一部分的掺杂物也可能施加于栅极结构160上,而产生一角落区域166,故角落区域166可具有相同于接触区146的导电型,例如都为N型掺杂。接触区146的宽度W2的范围是0.15μm~1μm。接触区146与栅极结构160的中间区域162的距离D3的范围是0.2μm~1.5μm。由于本发明的接触区146与栅极结构160之间的距离相当小,并不会增加基板110的电阻。
图2B绘示沿着图1的半导体装置的B-B连线的剖视图。
请同时参照图1及图2B,隔离区144(例如是浅沟槽隔离区(STI))可配置于基板110之上,且隔离区144可由主动层142的内部向外延伸。栅极结构160的第二部分1612、第三部分1613及第四部分1614分别对应于隔离区144与主动层142之间所形成的三个交界面。在图1的上视图中,由于主动层142内部的区域中形成有隔离区144,主动层142并非是矩形,而是为H型。相较于主动层为矩形的比较例而言,本发明中H型的主动层142能够与接触区146具有较少的接面(junction),故能降低接触区146的掺杂物往栅极结构扩散的机会。
图2C绘示沿着图1的半导体装置的C-C连线的剖视图。
请同时参照图1及图2C,栅极结构160的弯折部分1601、1602、1603、1604是分别配置于主动层142与基板110上的隔离区144之间的交界面144a上。栅极结构160覆盖一部分的隔离区144及一部分的主动层142。
本发明的半导体结构中,栅极结构的侧边部分为蛇型,亦即栅极结构的侧边部分与中间部分并不会共同形成H型、I型或T型,栅极结构的侧边部分具有至少一弯折部分于主动层上。因此,本发明的接触区的掺杂物并不会直线扩散至中间部分,而是要经过弯折部才能扩散至中间部分,故相较于栅极结构的侧边部分与中间部分共同形成H型、I型或T型的比较例而言,本发明的半导体装置中,不但栅极结构与接触区的扩散边界减少,掺杂物扩散的路径也增长,故扩散至栅极结构的中间部分的掺杂物的浓度会大幅降低。此外,本发明的栅极结构即使增长掺杂物扩散的路径,并没有增加原本电路布局的面积。本发明的半导体装置能够在相同或相似的电路布局的面积之下,避免基板的电阻的增加,降低掺杂物扩散至栅极结构的中间区域的浓度,使得半导体装置的效能得以获得提升。
虽然结合以上实施例公开了本发明,然而其并非用以限定本发明。本发明所属技术领域中的技术人员,在不脱离本发明的精神和范围内,可作各种的更动与润饰。因此,本发明的保护范围应当以附上的权利要求所界定的为准。
Claims (10)
1.一种半导体装置,包括:
基板;
主动层,配置于该基板之上,且该主动层具有源极区及漏极区;
接触区,配置于该基板之上;以及
栅极结构,配置于该主动层之上,其中该栅极结构包括中间部分及侧边部分,该侧边部分连接于该中间部分,且该侧边部分是蛇型。
2.如权利要求1所述的半导体装置,其中该栅极结构的该侧边部分具有四个弯折部分。
3.如权利要求1所述的半导体装置,其中该主动层是H型。
4.如权利要求1所述的半导体装置,还包括隔离区,该隔离区是配置于该基板之上且由该主动层的内部向外延伸。
5.如权利要求2所述的半导体装置,其中该栅极结构的各该弯折部分是配置于该主动层与该基板上的一浅沟槽隔离区之间的交界面上。
6.如权利要求1所述的半导体装置,其中该栅极结构的该侧边部分具有角落区域,该角落区域具有相同于该接触区的导电型。
7.如权利要求1所述的半导体装置,其中该源极区域具有第一导电型,该漏极区域具有该第一导电型,且该接触区域具有第二导电型。
8.如权利要求1所述的半导体装置,其中该栅极结构的该侧边部分具有第一部分、第二部分及第三部分,该第二部分位于该第一部分与该第三部分之间,且该第二部分连接于该第一部分与该第三部分,该第一部分与该半导体装置的一中心线之间具有一第一距离,该第三部分与该半导体装置的该中心线之间具有一第二距离,该第一距离不同于该第二距离。
9.如权利要求1所述的半导体装置,其中该栅极结构的该侧边部分具有第一部分、连接于该第一部分的第二部分、连接于该第二部分的第三部分、连接于该第三部分的第四部分以及连接于该第四部分的第五部分,其中该第三部分连接于该中间部分,该第一部分、该第三部分及该第五部分是分别朝一第一方向延伸,该第二部分及该第四部分是分别朝一第二方向延伸,该第一方向不同于该第二方向。
10.如权利要求1所述的半导体装置,其中该栅极结构是由多晶硅所形成,且厚度在50nm~250nm的范围中。
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