CN109522265A - A kind of DEU data exchange unit and method - Google Patents
A kind of DEU data exchange unit and method Download PDFInfo
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- CN109522265A CN109522265A CN201910043878.6A CN201910043878A CN109522265A CN 109522265 A CN109522265 A CN 109522265A CN 201910043878 A CN201910043878 A CN 201910043878A CN 109522265 A CN109522265 A CN 109522265A
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The embodiment of the invention discloses a kind of DEU data exchange unit and method, which includes: embedded controller, field programmable gate array fpga chip, flash chip and ethernet module；Embedded controller is connect with ethernet module, for receiving the Ethernet data of third party's transmission by ethernet module or Ethernet data being sent to third party；Fpga chip and flash chip pass through serial peripheral interface bus respectively and connect with embedded controller, for exchanging data with ethernet module by embedded controller.The communication mode of parallel bus in the prior art is revised as serial peripheral interface bus by the embodiment of the present invention, avoids occupying a large amount of input/output interface, and the design difficulty of printed circuit board is reduced, and then saved a large amount of resource, is reduced costs.
Description
Technical field
The present embodiments relate to electronic technology field more particularly to a kind of DEU data exchange unit and methods.
Background technique
With the development of science and technology with the raising of electronic hardware technology, more and more electronic products are used in the life of people
In living and work.
In the electronic product diagnosed in vitro, control system generally includes to run on the software of general purpose computer and instrument
On embedded controller, communicated using Ethernet.Due to needing to control a large amount of motor and detecting a large amount of signal, institute
It is designed, FPGA with commonly using field programmable gate array (Field Programmable Gate Array, FPGA) in instrument
With powerful parallel processing capability, embedded controller can be helped to share control task, improve the stability of system.But
Communicate by parallel bus between embedded controller and FPGA and other devices in the prior art, this communication mode
It needs to occupy a large amount of input/output (Input/Output, I/O) interface, and makes printed circuit board (Printed
Circuit Board, PCB) design difficulty and cost greatly increase.
Summary of the invention
The embodiment of the invention provides a kind of DEU data exchange unit and method, skill at high cost in the prior art can solve
Art problem.
In a first aspect, the embodiment of the invention provides a kind of DEU data exchange units characterized by comprising embedded control
Device, field programmable gate array fpga chip, flash chip and ethernet module processed；
The embedded controller is connect with the ethernet module, for receiving third party by the ethernet module
Ethernet data is sent to the third party by the Ethernet data of transmission；
The fpga chip and the flash chip pass through serial peripheral interface bus and the embedded controller respectively
Connection, for exchanging data with the ethernet module by the embedded controller.
Further, the ethernet module includes ethernet port phy controller, network transformer and standard 8
Modular interface.
Further, the serial peripheral interface bus is the bus of 4 lines.
Further, described device further includes power supply, and the power supply is connect with the embedded controller, for being described
Embedded controller power supply.
Further, described device further includes crystal resonator, and the crystal resonator and the embedded controller connect
It connects, for providing clock signal for the embedded controller.
Further, described device further includes restorer, and the restorer is connect with the embedded controller, for controlling
It makes the embedded controller and is in reset state.
Second aspect, the embodiment of the invention also provides a kind of method for interchanging data, this method comprises:
Embedded controller obtains the received Ethernet data of ethernet module；
The embedded controller carries out data conversion to the Ethernet data, and by described in after data conversion with
Too network data is sent to fpga chip and/or flash chip by serial peripheral interface bus.
Further, the method also includes:
The embedded controller obtains the fpga chip and/or the flash chip by serial peripheral interface bus
In data, and to the data carry out data conversion；
The data after data conversion are sent to the ethernet module by the embedded controller.
Further, the data conversion includes that Ethernet data is converted to suitable serial peripheral interface bus interface
Data, and/or, the data of suitable serial peripheral interface bus interface are converted into Ethernet data.
Further, the serial peripheral interface bus is the bus of 4 lines.
The embodiment of the present invention by be arranged serial peripheral interface bus make embedded controller respectively with fpga chip and sudden strain of a muscle
Chip connection is deposited, realizes that fpga chip and flash chip exchange data with ethernet module by embedded controller.The present invention
The communication mode of parallel bus in the prior art is revised as serial peripheral interface bus by embodiment, avoids occupying a large amount of defeated
Enter/output interface, and the design difficulty of printed circuit board is reduced, and then saved a large amount of resource, reduces costs.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the DEU data exchange unit in the embodiment of the present invention one；
Fig. 2 is the structural schematic diagram of the DEU data exchange unit in the embodiment of the present invention two；
Fig. 3 is the flow chart of the method for interchanging data in the embodiment of the present invention three.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment one
Fig. 1 is the structural schematic diagram of the DEU data exchange unit in the embodiment of the present invention one, and the present embodiment is applicable to electronics
Data exchange in product, the device specifically include: embedded controller 11, field programmable gate array fpga chip 12, flash memory
Chip 13 and ethernet module 14；
Embedded controller 11 is connect with ethernet module 14, for receiving what third party sent by ethernet module 14
Ethernet data is sent to third party by Ethernet data；
Fpga chip 12 and flash chip 13 are connect by serial peripheral interface bus with embedded controller 11 respectively, are used
Data are exchanged with ethernet module 14 in passing through embedded controller 11.
Wherein, Serial Peripheral Interface (SPI) (Serial Peripheral Interface, SPI) bus system is a kind of synchronization
Serial Peripheral Interface (SPI), it can be such that controller is communicated in a serial fashion with various peripheral equipments to exchange information.Spi bus
Can directly it be connected with the peripheral components of multiple standards, such as flash memory (FLASHRAM), network controller, LCD (Liquid
Crystal Display) display driver, modulus (A/D) converter and micro-control unit (Microcontroller Unit,
MCU) etc..
Serial peripheral interface bus is the bus of 4 lines, comprising: serial time clock line (Serial Clock, SCLK), host
Input/slave output data line MISO, host output/slave input data line MOSI and the effective slave selection line of low level
NSS.In current electronic technology field, there are IC bus (Inter-Integrated Circuit, IIC), controller
Local area network (Controller Area Network, CAN) bus, industry ethernet, spi bus, RS232 bus, RS485
The communication bus such as bus.Communication only can be realized by four lines using spi bus in the present embodiment, improve communication efficiency,
The mode of parallel bus in compared with the existing technology, has saved vast resources.
Ethernet (Ethernet) is a kind of Computer LAN Technology.802.3 standard formulation of IEEE of IEEE tissue
The technical standard of Ethernet, Ethernet protocol define a series of software and hardware standard.The advantage of Ethernet interface is into
This is low, flexible, becomes a kind of inevitable trend using Ethernet interface in network communication field.
Embedded controller 11 in the present embodiment can use the STM32F407 of ST company, can also use other classes
As controller.The third party that Ethernet protocol obtains ethernet module 14 can be run on embedded controller 11 to send out
The Ethernet data sent extracts, and wherein Ethernet protocol can be LWIP (Light Weight IP), and LWIP is one
ICP/IP protocol stack.Further, embedded controller 11 can convert Ethernet data to the data of suitable SPI interface,
And fpga chip 12 and flash chip 13 are sent to by spi bus.Also, embedded controller 11 can also be total by SPI
Line obtains the data in fpga chip 12 and flash chip 13, and converts data to Ethernet data and be sent to Ethernet later
Module 14, realizes data exchange.
Fpga chip 12 can use the EP4CE75 of altera corp, can also use other similar chips, fpga chip
12 are connected with embedded controller 11, and realization SPI interface can be programmed on fpga chip 12, to send and receive number
According to the communication of realization and embedded controller 11.SPI interface general at present, can be by the way of 8 or 16 data
It is communicated, since fpga chip 12 belongs to programming device, the data communication such as 24 or 32 also may be implemented, be embedded in
Formula control 11 can also be conducive to the efficiency for improving communication with the communication of the corresponding digit of simulated implementation.Flash chip 13, also known as
Flash chip can store data, and data can also be saved when system is powered down.Fpga chip 12 and flash chip 13 pass through 4 lines
Spi bus processed is connect with embedded controller 11.
Further, ethernet module 14 includes ethernet port phy controller (ethernet PHY controller), network
8 modular interfaces of transformer and standard (RJ45 interface).Wherein ethernet PHY controller is connect with embedded controller 11,
One end of network transformer connects RJ45 interface, and the other end connects ethernet PHY controller.Ethernet PHY controller can be adopted
It, can also be using similar chip with the DP83848 of TI company.
Further, which can also include restorer 15, and restorer 15 is connect with embedded controller 11, for controlling
Embedded controller 11 processed is in reset state.It wherein, include reset circuit, reset circuit and embedded Control in restorer 15
The reset pin of device 11 connects, and powered on moment reset circuit exports low level to embedded controller 11, forces embedded Control
Device 11 is in reset state.Further, high level is exported after preset time, embedded controller 11 is made to start normal work
Make.Preset time, which can according to need, to be configured.
Further, which can also include crystal resonator 16, and crystal resonator 16 and embedded controller 11 connect
It connects, for providing clock signal for embedded controller 11.Wherein, crystal resonator 16, also known as crystal oscillator, can be in the present embodiment
25M is used to have source crystal oscillator to provide clock signal for embedded controller 11.
Further, which can also include power supply 17, and power supply 17 is connect with embedded controller 11, for being insertion
Formula controller 11 is powered.Wherein the voltage of power supply 17 can be 3.3V.
The technical solution of the present embodiment, by be arranged serial peripheral interface bus make embedded controller respectively with FPGA core
Piece is connected with flash chip, realizes that fpga chip and flash chip exchange data with ethernet module by embedded controller.
The communication mode of parallel bus in the prior art is revised as serial peripheral interface bus by the present embodiment, avoids occupying a large amount of
Input/output interface, and the design difficulty of printed circuit board is reduced, and then saved a large amount of resource, it reduces into
This.
Embodiment two
Fig. 2 is the structural schematic diagram of the DEU data exchange unit in the embodiment of the present invention two, and the present embodiment is in above-described embodiment
On the basis of DEU data exchange unit is specifically described.Referring to fig. 2, which specifically includes: embedded Control
Device 11, field programmable gate array fpga chip 12, flash chip 13 and ethernet module 14.
Wherein, pass through Serial Peripheral Interface (SPI) (Serial Peripheral between embedded controller 11 and fpga chip 12
Interface, SPI) bus communicated, and embedded controller 11 is arranged 4 input/output (Input/Output, I/O) and draws
Foot, embedded controller 11 are host, and fpga chip 12 is slave.Spi bus is the bus of 4 lines, embedded controller 11
Spi bus between fpga chip 12 may include: SPI2-CS, SPI2-CLK, SPI2-MOSI and SPI2-MISO, wherein
Chip selection signal of the SPI2-CS as SPI after embedded controller 11 makes its low level, enables the SPI function of fpga chip 12
Energy；SPI2-CLK is as SPI clock signal；SPI2-MOSI is exported as the host of SPI, slave input；SPI2-MISO conduct
The host of SPI inputs, slave output.Embedded controller 11 can be used the STM32F407 of ST company, and fpga chip 12 can be with
Use the EP4CE75F29C8N of Intel Company.
Also by Serial Peripheral Interface (SPI) (Serial Peripheral between embedded controller 11 and flash chip 13
Interface, SPI) bus communicated, and embedded controller 11 is arranged 4 input/output (Input/Output, I/O) and draws
Foot, embedded controller 11 are host, and flash chip 13 is slave.Spi bus is the bus of 4 lines, embedded controller 11
Spi bus between flash chip 13 may include: SPI3-CS, SPI3-CLK, SPI3-MOSI and SPI3-MISO, wherein
Chip selection signal of the SPI3-CS as SPI after embedded controller 11 makes its low level, enables the SPI function of flash chip 13
Energy；SPI3-CLK is as SPI clock signal；SPI3-MOSI is exported as the host of SPI, slave input；SPI3-MISO conduct
The host of SPI inputs, slave output.It is not construed as limiting in concrete model the present embodiment of flash memory (Flash) chip 13, it can basis
It needs to be configured.
Further, ethernet module 14 includes ethernet port phy controller (ethernet PHY controller), network
8 modular interfaces of transformer and standard (RJ45 interface).Wherein ethernet PHY controller is connect with embedded controller 11,
One end of network transformer connects RJ45 interface, and the other end connects ethernet PHY controller.Embedded controller in the present embodiment
11 have been internally integrated ethernet mac (Media Access Control) control, but need to be subject to too net PHY control in outside
The DP83848C of TI company can be used in device, ethernet PHY controller.Embedded controller 11 and ethernet PHY controller it
Between use standalone media interface RMII (Reduced Media Independent Interface), RMII specification reduce 10/
Number of pins under 100Mbit/s between embedded controller 11 and ethernet PHY controller.According to IEEE 802.3u standard,
MII includes the pin of 16 data and control signal, and number of pins is reduced to 7 (number of pins reduces 62.5%) by RMII specification.
RMII data-interface needs 10 signals in total, wherein serial management interface (Serial Management
Interface, SMI) two signals: a clock signal MDC are used, the other is data-signal MDIO；Remaining 8 signal
For bidirectional data transfers, the wide 2bit of transmitted data bits.Referring to fig. 2, between embedded controller 11 and ethernet PHY controller
Connection signal include: ENET-TX-EN, ENET-TXD0, ENET-TXD1, ENET-TX-EN, ENET-RXD0, ENET-RXD1,
ENET-RX-ER, ENET-CRS-DV, ENET-MDC and ENET-MDIO, wherein ENET_TX_EN: enable signal is sent；ENET-
TXD0 and ENET-TXD1: data send signal, which is 2 one group of data-signal, are driven by ethernet mac sublayer is synchronous
It is dynamic, in the effective Shi Caiwei useful signal (valid data) of ENET-TX-EN signal；ENET-TXD0 is low order, ENET-TXD1
For high significance bit, when forbidding ENET-TX-EN, any influence will not be generated to ethernet PHY controller by sending data；ENET-
RXD0 and ENET-RXD1: within the clock cycle, when ENET-CRS-DV is effective, and ethernet mac detects and receives number in data
The data being considered as on RXD when intersecting lead code " 01 " bit according to frame are the starting of valid data frame, are acquired to data, no
Then it is considered invalid data, does not acquire；ENET-RX-ER: data transmission errors id signal, if sending data ENET-RXD has
Mistake then effectively has ethernet PHY output；ENET-CRS-DV: carrier wave and data valid signal, it is asynchronous with clock signal；ENET-
MDC:SMI interface with Lu Shizhong；The transmitting-receiving of ENET-MDIO:SMI bi-directional data is realized to configure ethernet PHY controller and be deposited
Device access.Also, ethernet PHY controller is connect by ENET-CLK with a 50M crystal resonator 18, for generating transmitting-receiving
The reference clock of data sharing.
Further, it is connected between ethernet PHY controller and network transformer by 4 signals, the network used
Transformer and RJ45 interface be it is integrated, it is the implementation separated that network transformer and RJ45 interface, which also can be used,.Ether
The signal netted between PHY controller and network transformer includes: TD+, TD-, RD+ and RD-, wherein TD+ and TD-: ether netting index
According to transmission signal, differential signal；RD+ and RD-: ethernet data acceptance signal, differential signal.
Further, which can also include restorer 15, and restorer 15 is connect with embedded controller 11, for controlling
Embedded controller 11 processed is in reset state.It wherein, include reset circuit, reset circuit and embedded Control in restorer 15
The reset pin of device 11 connects, and powered on moment reset circuit exports low level to embedded controller 11, forces embedded Control
Device 11 is in reset state.Further, high level is exported after preset time, embedded controller 11 is made to start normal work
Make.Preset time, which can according to need, to be configured.
Further, which can also include crystal resonator 16, and crystal resonator 16 and embedded controller 11 connect
It connects, for providing clock signal for embedded controller 11.Wherein, crystal resonator 16, also known as crystal oscillator, can be in the present embodiment
25M is used to have source crystal oscillator to provide clock signal for embedded controller 11.
Further, which can also include power supply 17, and power supply 17 is connect with embedded controller 11, for being insertion
Formula controller 11 is powered.Wherein the voltage of power supply 17 can be 3.3V.
The technical solution of the present embodiment, by be arranged serial peripheral interface bus make embedded controller respectively with FPGA core
Piece is connected with flash chip, realizes that fpga chip and flash chip exchange data with ethernet module by embedded controller.
The communication mode of parallel bus in the prior art is revised as serial peripheral interface bus by the present embodiment, avoids occupying a large amount of
Input/output interface, and the design difficulty of printed circuit board is reduced, and then saved a large amount of resource, it reduces into
This.
Embodiment three
Fig. 3 is the flow chart of the method for interchanging data in the embodiment of the present invention three, and the present embodiment is applicable to realize data
The case where exchange, this method can be executed by the DEU data exchange unit in above-described embodiment.This method can specifically include:
S110, embedded controller obtain the received Ethernet data of ethernet module.
Wherein, Ethernet data can come from external third party's device or equipment, in specific source the present embodiment
It is not construed as limiting.Ethernet data is controlled by the RJ45 interface (including network transformer) in ethernet module to ethernet PHY
Device, embedded controller can be extracted Ethernet data from the ethernet PHY controller by Ethernet protocol.
S120, embedded controller carry out data conversion to Ethernet data, and by the ether netting index after data conversion
Fpga chip and/or flash chip are sent to according to by serial peripheral interface bus.
Wherein, data conversion may include the number that Ethernet data is converted to suitable serial peripheral interface bus interface
According to, and/or, the data of suitable serial peripheral interface bus interface are converted into Ethernet data.Serial peripheral interface bus is 4
The bus of line.
Specifically, after embedded controller gets the received Ethernet data of ethernet module, by Ethernet data
The data of suitable serial peripheral interface bus interface are converted to, and the suitable serial peripheral interface bus after data conversion is connect
The data of mouth are sent to fpga chip and/or flash chip by serial peripheral interface bus.
It further, can also include S130-S140 (not shown) after S120, specific:
S130, embedded controller obtain the number in fpga chip and/or flash chip by serial peripheral interface bus
According to, and data conversion is carried out to data.
Specifically, fpga chip and flash chip are serial since embedded controller is the host of Serial Peripheral Interface (SPI)
The slave of Peripheral Interface, embedded controller actively obtain fpga chip and/or flash chip by serial peripheral interface bus
In data, and the data of suitable serial peripheral interface bus interface are converted into Ethernet data.
Data after data conversion are sent to ethernet module by S140, embedded controller.
Ethernet data after data conversion can be passed through Ethernet protocol for Ethernet data by embedded controller
Be sent on the ethernet PHY controller of ethernet module, then by ethernet PHY controller by Ethernet data from RJ45 interface
(including network transformer) is sent to external third party's device or equipment.
The technical solution of the present embodiment obtains the received Ethernet data of ethernet module by embedded controller, embedding
Enter formula controller and data conversion is carried out to Ethernet data, and the Ethernet data after data conversion is connect by serial peripheral
Mouth bus is sent to fpga chip and/or flash chip；Embedded controller carries out data conversion to Ethernet data, and will count
Fpga chip and/or flash chip are sent to by serial peripheral interface bus according to the Ethernet data after conversion, it is embedded
Data after data conversion are sent to ethernet module by controller.The present embodiment leads to parallel bus in the prior art
Letter mode is revised as serial peripheral interface bus, and by serial peripheral interface bus realize fpga chip and ethernet module,
Data exchange between flash chip and ethernet module avoids occupying a large amount of input/output interface, and makes printing electricity
The design difficulty of road plate reduces, and then has saved a large amount of resource, reduces costs.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of DEU data exchange unit characterized by comprising embedded controller, dodges field programmable gate array fpga chip
Deposit chip and ethernet module；
The embedded controller is connect with the ethernet module, is sent for receiving third party by the ethernet module
Ethernet data or Ethernet data is sent to the third party；
The fpga chip and the flash chip pass through serial peripheral interface bus respectively and connect with the embedded controller,
For exchanging data with the ethernet module by the embedded controller.
2. the apparatus according to claim 1, which is characterized in that
The ethernet module includes 8 ethernet port phy controller, network transformer and standard modular interfaces.
3. the apparatus according to claim 1, which is characterized in that the serial peripheral interface bus is the bus of 4 lines.
4. the apparatus according to claim 1, which is characterized in that it further include power supply, the power supply and the embedded Control
Device connection, for powering for the embedded controller.
5. the apparatus according to claim 1, which is characterized in that it further include crystal resonator, the crystal resonator and institute
Embedded controller connection is stated, for providing clock signal for the embedded controller.
6. the apparatus according to claim 1, which is characterized in that further include restorer, the restorer with it is described embedded
Controller connection, is in reset state for controlling the embedded controller.
7. a kind of method for interchanging data characterized by comprising
Embedded controller obtains the received Ethernet data of ethernet module；
The embedded controller carries out data conversion to the Ethernet data, and by the Ethernet after data conversion
Data are sent to fpga chip and/or flash chip by serial peripheral interface bus.
8. the method according to the description of claim 7 is characterized in that further include:
The embedded controller is obtained in the fpga chip and/or the flash chip by serial peripheral interface bus
Data, and data conversion is carried out to the data；
The data after data conversion are sent to the ethernet module by the embedded controller.
9. the method according to the description of claim 7 is characterized in that the data conversion include Ethernet data is converted to it is suitable
The data of serial peripheral interface bus interface are closed, and/or, the data of suitable serial peripheral interface bus interface are converted into ether
Network data.
10. the method according to the description of claim 7 is characterized in that the serial peripheral interface bus is the bus of 4 lines.
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| CN113030256A (en) * | 2021-02-26 | 2021-06-25 | 陕西科技大学 | Multipurpose detection method based on ultrasonic backscattering |
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| CN104901877A (en) * | 2015-06-17 | 2015-09-09 | 燕山大学 | Multi-interface self-adaptive wireless heterogeneous network protocol conversion method and communication device |
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| CN207780536U (en) * | 2017-06-09 | 2018-08-28 | 贵州电网有限责任公司电力科学研究院 | A kind of intelligent substation embedded system merging unit control device based on IEC61850 standards |
| CN207503218U (en) * | 2017-10-30 | 2018-06-15 | 湖南跨线桥航天科技有限公司 | A kind of FPGA holotype SPI loaded circuits for supporting dynamic configuration |
| CN207926824U (en) * | 2018-03-01 | 2018-09-28 | 柳州达迪通信技术股份有限公司 | A kind of cross channel device for Digital Distribution Frame |
| CN209132754U (en) * | 2019-01-17 | 2019-07-19 | 蓝怡科技集团股份有限公司 | A kind of DEU data exchange unit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113030256A (en) * | 2021-02-26 | 2021-06-25 | 陕西科技大学 | Multipurpose detection method based on ultrasonic backscattering |
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