CN203278864U - IEC61850 message acquisition board card based on CRIO (Core-Router Integrated Overlay) platform - Google Patents

Abstract

The utility model discloses an IEC61850 message acquisition board card based on a CRIO (Core-Router Integrated Overlay) platform. The board card comprises an optical network port, an Ethernet PHY (Physical Layer) module, a power conversion module, an FPGA (Field Programmable Gate Array) module and an crystal oscillator, wherein the optical network port is connected with the Ethernet PHY module; the Ethernet PHY module is connected with the FPGA module through an FPGA bus; an output terminal of the crystal oscillator is connected with the FPGA module; a power terminal of the crystal oscillator is connected with a 3.3V of power supply; a grounding terminal of the crystal oscillator is grounded; the power conversion module is connected with the FPGA module so as to supply the power for the whole board card; and the FPGA module is externally connected with the CRIO platform through an SPI (Serial Peripheral Interface) bus. As the board card is used, the hardware blank of the CRIO platform for an intelligent substation in measurement and control aspects is compensated effectively; and the acquisition and the transmission of IEC61850 message data of the intelligent substation are realized on the CRIO platform.

Description

IEC61850 message analog input card based on the CRIO platform

Technical field

The utility model relates to a kind of IEC61850 message analog input card based on American National instrument (NI) CRIO of company platform, the collection and the precise time that are used for intelligent substation and process layer of digitalization transformer substation SV and GOOSE data message are demarcated, and belong to intelligent substation of electric power system and digital transformer substation detection/calibration technology field.

Background technology

Fast development along with technology such as the automation of transformation substations, communication and microelectronics, intelligent electronic devices based on microprocessor/controller have appearred in the electric substation automation system field in a large number, the level of the automation of transformation substations is improving constantly, and the system integration becomes trend.In this evolution, interoperability is poor has begun to become " bottleneck " problem, network and communication protocol that to be different vendor or same manufacturer adopt at the intelligent electronic device of different times may be not identical, making needs protocol conversion just can be integrated into a transformer substation system between intelligent electronic device, thereby increased cost and the complexity of system, affected real-time and the reliability of system.In order to address this problem and adapt to computer and the communication technology of quick renewal in the future, the international standard IEC61850 that International Electrotechnical Commission promulgated about automation of transformation substations network service in 2005.IEC61850 is substation communication network and the system standard that a cover is complete, face the future, and wherein of paramount importance two class models are sampling value message mode and general substation event transmission model.Communicate existing application widely in intelligent substation based on the IEC61850 standard.

The CRIO of NI company is a reconfigurable embedded Control and acquisition system, and it has firm hardware structure, and in addition, it accepts programming by NI LabVIEW graphic programming instrument, and is used for all kinds of embedded Control and monitoring facilities.Exactly because good antijamming capability, firm structure and stable performance, the CRIO platform is widely used in the engineering measurement and control area.The characteristics such as the ease for use of CRIO platform, versatility, extensibility, reliability are the platforms that is mainly used at present prototype test, yet, owing to lacking intelligent substation message acquisition module, therefore also there is no the application about intelligent substation observing and controlling aspect on this platform.

Summary of the invention

The purpose of this invention is to provide a kind of IEC61850 message analog input card based on the CRIO platform, it can effectively receive and send the IEC61850 message in the intelligent substation secondary circuit, and can receive pulse per second (PPS), synchronize with external clock, the message that receives is carried out the correct time demarcation in realization and accurate timing sends message, and the message data after parsing and time of reception send to the CRIO platform to use by the DB15 interface.

be the transmission rate that satisfies the IEC61850 sampling value message and the uniformly-spaced property between message, requirement is (4kHz within the sampling interval, 12.8kHz etc. sample frequency) complete the parsing of data message, framing, storage, the work such as packet filtering, need observe simultaneously NI company to the dimensional requirement of integrated circuit board exploitation on the CRIO platform, therefore, the present invention adopts fpga chip, the light network interface, the ethernet PHY chip, message of the common formation of RAM chip and Flash chip gathers embedded system, by DB15 interface and CRIO communication, complete the transmission of data according to the SPI communications protocol.Use the untapped pin of SPI communication in the DB15 interface, to analog input card, can realize the time synchronized of CRIO and message analog input card by CRIO transmitting time synchronizing signal, with realization, the message time of reception is accurately demarcated.Concrete scheme is as follows:

IEC61850 message analog input card based on the CRIO platform comprises light network interface, ethernet PHY module, power transfer module, FPGA module and crystal oscillator; Wherein said smooth network interface is connected with the ethernet PHY module, the ethernet PHY module is connected with the FPGA module by the FPGA bus, the output of crystal oscillator connects FPGA module input end of clock mouth, the power end of crystal oscillator connects 3.3V power supply (by obtaining after the power transfer module step-down), the earth terminal ground connection of crystal oscillator, the power input that power transfer module connects the FPGA module is whole integrated circuit board power supply, and the FPGA module is by the external CRIO platform of spi bus.Also comprise the reset circuit that is connected with described FPGA module, draw together indicator light and LED drive circuit, LED drive circuit is connected with the FPGA module with indicator light respectively.

The FPGA module comprise CPU, SPI driver module and to the time module, CPU is connected with SPI driver module module when being connected respectively, CPU receives the IEC61850 message that the ethernet PHY module sends, then by the SPI driver module with the IEC61850 message transmissions to the CRIO platform, to the time module receive the synchronizing clock signals that the CRIO platform sends.CPU completes application layer address filtration, parsing, calculating, the Interruption of data message and manages the function of resource on integrated circuit board.

The FPGA module connects the RAM memory by the FPGA bus.The RAM memory uses RAM and Flash Memory respectively as data space and program's memory space, the storage resources that is used for spread F PGA module, satisfy the memory requirement of Large Volume Data message and program, thereby can complete the function of complicated packet parsing, framing, storage

The FPGA module is provided with the JTAG configuration interface.

The utility model can be completed functions such as collection, analysis and transmission to the IEC61850 message easily by the embedded system take fpga chip as core.The message analog input card can be stamped the precise time stamp to the data message by the maintenance to internal clocking, carries out autgmentability for the CRIO platform and uses.

Description of drawings

Fig. 1 is the hardware configuration schematic diagram of the utility model message analog input card;

Fig. 2 is the outline dimensional drawing of the utility model message analog input card;

Fig. 3 is the SPI communication modes sequential chart that the utility model uses.

Embodiment

Face is described with reference to the accompanying drawings details and the working condition of the concrete device that proposes according to the present invention.The working principle of hardware of EC61850 message analog input card is as follows: by the opto-electronic conversion of AFBR5803 light network interface 1 realization to light signal, the filtration that ethernet PHY module 2 realizes message, required message is inputed in FPGA module 5, by parsing, conversion and the framing of FPGA module 5 realizations to the IEC61850 message, then the data of useful passage in message are sent to the CRIO platform by the DB15 interface.Specific descriptions referring to Fig. 1 modules are as follows:

(1) size designIEC61850 message analog input card is applied to the NI CRIO of company platform, and its overall dimension meets the standard-required of this platform integrated circuit board exploitation.The integrated circuit board profile as shown in Figure 2, long 79.98mm, wide 73.38mm, element height needs less than 2.64mm in the shadow region, wiring is outwards forbidden in the shadow region, less than 13.46mm, back side element height is less than 2.64mm with interior element height in the shadow region.

(2) power transfer module designProvide a power line to be used for the integrated circuit board power supply in CRIO platform communication standard on the DB15 interface, but because its output power is 1 watt to the maximum, can't satisfy the power demands of integrated circuit board, therefore, the utility model uses outside 12V independent direct current Switching Power Supply supply power mode, use TPS54325 and MAX1951 chip to consist of power transfer module 3, convert the 12V power supply to 3.3V, 1.2V for other chips and kernel.Connect therefore the interchannel isolation of consideration power supply owing to being light current.

(3) fiber optic Ethernet transceiver module designBecause present intelligent substation extensively adopts the ST multimode fiber as data transmission media, therefore the utility model uses one group of AFBR5803 ethernet transceiver (being light network interface 1) as front end transmitting-receiving medium, its major function is the opto-electronic conversion that realizes light signal, its transmission rate is 100Mbit/s, full-duplex mode is used for the transmitting-receiving of SV, GOOSE light numeral message.Be connected with simultaneously ethernet PHY module 2, be used for the configuration of fiber optic Ethernet and the address filtering of MAC layer.

(4) reset circuit 4 designsBe mainly used in the hard reset of analog input card, adopt watchdog reset circuit commonly used at present.Utilize CPU when normal operation timer conter that resets, do not produce reset pulse; And the undesired hour counter of CPU work surpasses limit value, thereby reality is to cpu reset.Can realize the active homing of CPU is managed by watchdog reset circuit.

(5) High Precision Crystal Oscillator and to the time modular designFor satisfy high-precision to the time synchronous requirement, the utility model uses high-precision temperature compensating crystal oscillator TCXO to be connected with phase-locked loop circuit (PLL) in FPGA module 5 clock signal is provided, the accuracy class of this crystal oscillator is less than 1PPM, and the precision of temperature compensating crystal oscillator can not change along with the variation of working temperature, it makes corresponding compensation to the perception of real time temperature to crystal oscillator by thermistor, therefore the application of this temperature compensating crystal oscillator can for high accuracy to the time integrated circuit board good work clock is provided, make integrated circuit board can stablize, work fast.High accuracy to the time module function mainly completed by FPGA, its major function is that the synchronizing clock signals of sending according to CRIO uses adaptive compensation algorithm to safeguard the clock of integrated circuit board self, thus reach high accuracy to the time purpose.

(6) design of memory systemsThe utility model adopts three layers of design Storage, that is: register (RAM that is connected with CPU in Fig. 1), RAM(power down volatile memory on the FPGA sheet), Flash Memory(power down freeze mode memory).Wherein, on the FPGA sheet, register is little but access speed is fast due to capacity, is mainly used in the access of intermediate variable, array; The RAM configuration capacity is the memory of 64MB, and after, power down large due to its memory capacity, data can be lost, and is used for therefore being mainly used in storing that front end receives and data message, rear end to be sent receives from the data of CRIO and the data that need send to CRIO; Flash Memory uses configuration capacity to be the Flash chip of 16MB, and after, power down large due to its memory capacity, data can not lost, and therefore, are mainly used in the working procedure of storage of collected integrated circuit board.

(7) FPGA main control chip designThe FPGA of the utility model employing ALTERA company is as embedded system main control chip (FPGA module 5).Programmable chip system (SOPC) in ALTERA company fpga chip supporting pieces can use the IP kernel of recommendation, also can programme voluntarily by VHDL language.Based on the programmable chip system, logical circuit in FPGA can be divided into two parts, a part is the gate drive circuit that uses VHDL language to write, this partial logic circuit comprise PHY chip drives module, to the time module, SPI driver module, another part is to adopt the IP kernel of recommending, as cpu circuit module and phase-locked loop circuit (PLL).

The FPGA main control chip is mainly completed the control to ethernet PHY module 2, with analysis, conversion and the framing to the IEC61850 message, receive the synchronizing clock signals that the CRIO platform sends and complete maintenance to internal clocking, and with the functions such as exchanges data of RAM memory 6.Wherein, to the time module adopt adaptive compensation algorithm by the correction to the pps pulse per second signal of external clock, realize the high accuracy of inner synchronised clock is safeguarded, and stamp precise time to message and stab when message arrives; PHY chip drives module mainly is correlated with to ethernet PHY module 2 and is arranged so that ethernet PHY module 2 can complete screening, the reception to the IEC61850 message, and is stored in reception buffer zone in RAM memory 6; The SPI driver module is mainly realized the communication between IEC61850 message analog input card and CRIO platform, and communication process adopts the sequential of standard SPI pattern 0 usually, and employing and the multiple verification form such as verification, CRC check are carried out verification to data; The CPU core module that builds in FPGA module 5 is completed the main logic function of integrated circuit board, comprise screening and the conversion of decoding to message, data and send to the CRIO platform with data framing again and by the DB15 interface, the modification of the kernel program configuration information that can send according to the CRIO platform to configuration parameter in program simultaneously.

(8) interface and the driving with the CRIO platform designsAccording to the platform integrated circuit board designing requirement of CRIO platform, the utility model integrated circuit board uses DB15 interface and CRIO platform to carry out physical connection.The concrete pinout of DB15 is as shown in table 1 below, for concrete application, the design uses SPI_CS, SPI_CLK, MOSI and MISO pin as SPI communication pin, and can be used as other holding wires for idle pin, as being the pps pulse per second signal line with the ID_Select pinout, be used for integrated circuit board receive the CRIO platform send to the time pulse.

Table 1 DB15 pinout

The SPI driver module is mainly completed by FPGA, and it is 10M that the physical layer of the utility model SPI communication mainly adopts the sequential of SPI pattern 0, baud rate.In the SPI sequential, packet load mode of 8 bit changed 18 bits in the past, and front dibit is used for representing whether this packet is effective.Be provided with and verification in every segment data message, to guarantee the correctness of transfer of data.Accompanying drawing 3 has provided the sequential of SPI pattern 0, when needs transmit and receive data, the SPI_CS signal is dragged down, drag down rear transmission SPI_CLK clock signal, and according to this signal step-by-step frame that transmits and receive data, the SPI_MISO holding wire is that main frame is received data wires, the SPI_MOSI holding wire is that main frame is sent out data wire, after sending or finishing receiving, the SPI_CS signal is drawn high, and stopped sending the SPI_CLK clock signal, until again need to send or receive data.

(9) debugging interface designIntegrated circuit board mainly adopts JTAG configuration interface 9 to download and the FPGA Debugging program, and JTAG configuration interface 9 adopts 14 needle interfaces of standard, and 14 pinouts are as shown in table 2, have higher versatility.And reserved the RJ11 interface, facilitate debugging and test to the FPGA program.

Table 2 JTAG pinout

Claims (6)

1. based on the IEC61850 message analog input card of CRIO platform, it is characterized in that: comprise light network interface (1), ethernet PHY module (2), power transfer module (3), FPGA module (5) and crystal oscillator (10); Wherein said smooth network interface (1) is connected with ethernet PHY module (2), ethernet PHY module (2) is connected with FPGA module (5) by the FPGA bus, the output of crystal oscillator (10) connects FPGA module (5) input end of clock mouth, the power end of crystal oscillator (10) connects the 3.3V power supply, the earth terminal ground connection of crystal oscillator (10), the power input that power transfer module (3) connects FPGA module (5) is whole integrated circuit board power supply, and FPGA module (5) is by the external CRIO platform of spi bus.

2. according to claim 1 based on the IEC61850 message analog input card of CRIO platform, it is characterized in that: described FPGA module (5) comprise CPU, SPI driver module and to the time module, CPU is connected with SPI driver module module when being connected respectively, CPU receives the IEC61850 message that ethernet PHY module (2) sends, then by the SPI driver module with the IEC61850 message transmissions to the CRIO platform, to the time module receive the synchronizing clock signals that the CRIO platform sends.

3. according to claim 1 based on the IEC61850 message analog input card of CRIO platform, it is characterized in that: described FPGA module (5) connects RAM memory (6) by the FPGA bus.

4. according to claim 1 or 3 described IEC61850 message analog input cards based on the CRIO platform, is characterized in that: also comprise the reset circuit (4) that is connected with described FPGA module (5).

5. according to claim 4 based on the IEC61850 message analog input card of CRIO platform, it is characterized in that: described FPGA module (5) is provided with JTAG configuration interface (9).

6. according to claim 1 based on the IEC61850 message analog input card of CRIO platform, it is characterized in that: also comprise indicator light (7) and LED drive circuit (8), LED drive circuit (8) is connected 5 with indicator light (7) with the FPGA module respectively) be connected.

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