CN109491439A - A kind of reference voltage source and its working method - Google Patents

Abstract

The invention discloses a reference voltage source, comprising: a start-up circuit, a first-order compensation circuit, a high-order compensation circuit for reducing the temperature coefficient of the reference voltage, and an ICTAT for reducing the power supply voltage regulation rate of the reference voltage, which are connected in sequence Current generator circuit; by using the second N-type field effect transistor MN2, the third N-type field effect transistor MN3, the fourth N-type field effect transistor MN4, the fourth P-type field effect transistor MP4, the fifth The negative feedback loop formed by the P-type field effect transistor MP5 replaces the operational amplifier of the traditional reference voltage source to stabilize the node voltage, which simplifies the circuit design and the complexity of implementation, and reduces the area of the circuit.

Description

A reference voltage source and its working method

technical field

The invention relates to the technical field of analog integrated circuits, in particular to a reference voltage source and a working method thereof.

Background technique

The reference voltage source is the basic component of the analog integrated circuit, and its accuracy and stability directly affect the operation of the entire circuit system. At present, reference voltage sources have been widely used in digital, analog and digital-analog mixed signal systems. For example, systems such as A/D, D/A converters, memories, and phase-locked loops need to use reference voltage sources to determine their input. range of the output signal, and consider the effects of the reference on the gain and presence of noise in these systems. With the development of ultra-large-scale integrated circuits, tens of millions of transistors, operators and controllers are integrated on a chip of several square microns, so the demand for small-area, high-precision and high-stability reference voltage sources is also increasing. .

The reference voltage source measures its accuracy and stability by the temperature coefficient and the power supply voltage regulation rate. Therefore, to achieve a small area, high precision and high stability reference voltage source, the temperature coefficient and power supply voltage should be reduced as much as possible. adjustment rate. The traditional reference voltage source maintains the voltage value of a specific node through the op amp, and generates a voltage difference with a positive temperature coefficient through the bipolar transistor, but due to the generally large area of the op amp and the bipolar transistor, it is difficult to achieve Reduced chip area requirements. In addition, the traditional reference voltage source is to add a voltage proportional to the absolute temperature and a voltage inversely proportional to the absolute temperature to achieve a reference voltage with zero temperature characteristics. However, the temperature coefficient of the reference voltage generated by this method is high, usually between 20 and 100 ppm/°C. Figure 1 is a schematic diagram of the structure of the reference voltage source in the traditional technology. The working principle of the traditional reference voltage source is to use the operational amplifier A1 to stabilize the voltage values of points a and b. The voltage difference between the bipolar transistors Q1 and Q2 is on the resistor R3. A current proportional to the temperature is generated, and this current is mirrored to the resistor R4 through the M3 tube to form a voltage VPTAT proportional to the temperature. Since the base-emitter voltage of a bipolar transistor is inversely proportional to temperature, a temperature-independent output reference voltage can be obtained by superimposing this voltage with VPTAT. The traditional voltage reference source is widely used due to the mature technology, but because only the first-order temperature term is canceled in the design, the bipolar transistor base-emitter voltage V _BE still contains high-order terms. Therefore, the temperature coefficient of this traditional first-order reference voltage source is relatively high, usually above 20ppm/°C; and because multiple bipolar transistors are used in the traditional reference voltage source, the chip area is increased and the cost is reduced. becomes difficult. In order to solve the problem of too high temperature coefficient, some compensation methods have been proposed, such as exponential compensation technique, piecewise linear compensation method, these techniques can well compensate the temperature coefficient of the reference voltage source, but it is unavoidable that the circuit needs The use of operational amplifiers results in an increase in the chip area. In recent years, in order to solve the problem of excessive chip area, design methods of reference voltage sources without operational amplifiers have begun to be proposed. However, in these circuit designs using reference voltage sources without operational amplifiers, the key factors such as temperature coefficient and power supply voltage regulation rate are The parameters also increase accordingly, resulting in the deterioration of the accuracy and stability of the circuit; at the same time, due to the integration of a large number of bipolar transistors in the circuit, the area of these reference voltage source modules without operational amplifiers is also large, so it is still impossible to Meet the requirements of the reference voltage source design for the development of modern ultra-large-scale integrated circuits.

Therefore, there is an urgent need in the industry to develop a reference voltage source that improves the accuracy and stability of the reference voltage source and reduces the area of the reference voltage source chip on the basis of reducing the complexity of the circuit design and implementation of the traditional reference voltage source. .

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a reference voltage source in order to overcome the above shortcomings of the prior art.

Another object of the present invention is to provide a working method with a low reference voltage source in order to overcome the above shortcomings of the prior art.

The object of the present invention is achieved through the following technical solutions:

A reference voltage source, comprising: a start-up circuit, a first-order compensation circuit, a high-order compensation circuit for reducing the temperature coefficient of the reference voltage, and an ICTAT current generator circuit for reducing the power supply voltage regulation rate of the reference voltage, which are connected in sequence ; The first-order compensation circuit includes the third P-type FET MP3, the fourth P-type FET MP4, the fifth P-type FET MP5, the sixth P-type FET MP6, and the seventh P-type FET Tube MP7, eighth P-type FET MP8, ninth P-type FET MP9, second N-type FET MN2, third N-type FET MN3, fourth N-type FET MN4, resistor R1 , resistor R2 and bipolar transistor Q1; the gate of the third P-type field effect transistor MP3, the gate of the fourth P-type field effect transistor MP4, the gate and drain of the fifth P-type field effect transistor MP5, the first The gates of the six P-type field effect transistors MP6 are all connected to the high-order compensation circuit, the gate of the third P-type field effect transistor MP3 is also connected to the start-up circuit, the source of the third P-type field effect transistor MP3, and the fourth P-type field effect transistor. The source of the type FET MP4, the source of the fifth P-type FET MP5, and the source of the sixth P-type FET MP6 are all connected to the input voltage VDD, and the drain of the fifth P-type FET MP5 It is connected to the drain of the second N-type field effect transistor MN2; the source of the second N-type field effect transistor MN2 is connected to the source of the seventh P-type field effect transistor MP7, and the gate of the second N-type field effect transistor MN2 and The drain of the third N-type field effect transistor MN3 and the drain of the third P-type field effect transistor MP3 are connected; the drain and gate of the seventh P-type field effect transistor MP7 are both grounded; the third N-type field effect transistor The source of MN3 is connected to the source of the eighth P-type field effect transistor MP8, the gate of the third N-type field effect transistor MN3 and the gate of the fourth N-type field effect transistor MN4, the fourth N-type field effect transistor MN4 The drain of the fourth P-type field effect transistor MP4 is connected; the source of the fourth N-type field effect transistor MN4 is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the ninth P-type field effect transistor MP9. source; the gate and drain of the eighth P-type field effect transistor MP8 and the gate and drain of the ninth P-type field effect transistor MP9 are grounded; the drain of the sixth P-type field effect transistor MP6 and the resistance of the resistor R2 One end is connected; the other end of the resistor R2 is connected to the emitter of the bipolar transistor Q1, and both the base and the collector of the bipolar transistor Q1 are grounded.

Preferably, the startup circuit includes: a first P-type field effect transistor MP1, a second P-type field effect transistor MP2 and a first N-type field effect transistor MN1; the source and input voltage of the first P-type field effect transistor MP1 VDD is connected, the gate of the first P-type field effect transistor MP1 is connected to the gate of the third P-type field effect transistor MP3, the gate of the fourth P-type field effect transistor MP4, and the drain of the fifth P-type field effect transistor MP5 , the gate of the fifth P-type field effect transistor MP5, the gate of the sixth P-type field effect transistor MP6 are all connected, the drain of the first P-type field effect transistor MP1 and the gate of the second P-type field effect transistor MP2 , the gates of the first N-type field effect transistor MN1 are connected to the ground; the source and drain of the first N-type field effect transistor MN1 are connected to the ground, and the drain of the second P-type field effect transistor MP2 is connected to the second N-type field effect transistor. The gate of the FET MN2 is connected.

Preferably, the high-order compensation circuit includes: a tenth P-type field effect transistor MP10, an eleventh P-type field effect transistor MP11, a fifth N-type field effect transistor MN5, and a sixth N-type field effect transistor MN6; The gate of the P-type field effect transistor MP10 is connected to the gate of the sixth P-type field effect transistor MP6, the source of the tenth P-type field effect transistor MP10 and the source of the eleventh P-type field effect transistor MP11 are connected to the input voltage VDD is connected, the drain of the tenth P-type field effect transistor MP10 is connected to the drain of the fifth N-type field effect transistor MN5 and the drain of the eleventh P-type field effect transistor MP11; the eleventh P-type field effect transistor MP11 The gate is connected to the ICTAT current generator circuit; the drain of the fifth N-type field effect transistor MN5 is also connected to the gate of the fifth N-type field effect transistor MN5 and the gate of the sixth N-type field effect transistor MN6. The source of the fifth N-type field effect transistor MN5 is grounded; the drain of the sixth N-type field effect transistor MN6 is connected to the drain of the sixth P-type field effect transistor MP6, and the source of the sixth N-type field effect transistor MN6 is grounded.

Preferably, the ICTAT current generator circuit includes: a twelfth P-type field effect transistor MP12, a thirteenth P-type field effect transistor MP13, a fourteenth P-type field effect transistor MP14, and a seventh N-type field effect transistor MN7 , the eighth N-type field effect transistor MN8 and the resistor R3; the gate of the twelfth P-type field effect transistor MP12, the gate of the thirteenth P-type field effect transistor MP13 and the gate of the fourteenth P-type field effect transistor MP14 The electrode is connected to the gate of the eleventh P-type field effect transistor MP11, the source of the twelfth P-type field effect transistor MP12, the source of the thirteenth P-type field effect transistor MP13 and the fourteenth P-type field effect transistor The source of MP14 is connected to the input voltage VDD, the drain of the twelfth P-type field effect transistor MP12 is connected to the gate of the seventh N-type field effect transistor MN7 and one end of the resistor R3; the other end of the resistor R3 is grounded; the thirteenth The drain of the P-type field effect transistor MP13 is connected to the drain of the seventh N-type field effect transistor MN7; the source of the seventh N-type field effect transistor MN7 is grounded; the drain of the fourteenth P-type field effect transistor MP14 is connected to the drain of the seventh N-type field effect transistor MN7. The gate of the fourteenth P-type field effect transistor MP14 is connected to the drain of the eighth N-type field effect transistor MN8; the gate of the eighth N-type field effect transistor MN8 is connected to the drain of the seventh N-type field effect transistor MN7; The sources of the eight N-type field effect transistors MN8 are grounded.

Another object of the present invention is achieved through the following technical solutions:

A working method of a reference voltage source, comprising:

S1, when the power supply is powered on, the startup circuit starts normally, and the reference voltage source enters the normal working state;

S2, the second N-type FET MN2, the third N-type FET MN3, the fourth N-type FET MN4, the fourth P-type FET MP4, and the fifth P-type FET of the first-order compensation circuit MP5 forms a negative feedback loop to maintain the same voltage at the preset node. The seventh P-type field effect transistor MP7, the eighth P-type field effect transistor MP8 and the ninth P-type field effect transistor MP9 work in the sub-threshold region, and pass the PMOS transistor. The voltage difference between them produces a current IPTAT with a positive temperature coefficient, which is copied to the output of the reference voltage source through a current mirror;

S3, the ICTAT current generator circuit generates a negative temperature coefficient current ICTAT that does not vary with the supply voltage.

S4, the high-order compensation circuit copies the current ICTAT to the output terminal of the reference voltage source, and the current combined with the current IPTAT forms a high-order compensation voltage in the resistor R2 to compensate the first-order reference voltage (output voltage, Vref).

Preferably, step S1 includes: when the power supply is powered on, the gate of the first N-type field effect transistor MN1 is at a low potential, the second P-type field effect transistor MP2 is turned on, and the gate of the second N-type field effect transistor MN2 becomes High level, the second N-type field effect transistor MN2 is turned on, the current flows through the fifth P-type field effect transistor MP5, the second N-type field effect transistor MN2 and the seventh P-type field effect transistor MP7 to the ground, and the fifth The gate potential of the P-type field effect transistor MP5 is pulled down, and the startup circuit starts to start; the current passes through the first P-type field effect transistor MP1 to charge the second P-type field effect transistor MP2, and the gate of the second P-type field effect transistor MP2 The potential increases gradually, and when it increases to a preset threshold voltage value lower than the power supply, the second P-type field effect transistor MP2 is turned off, the start-up circuit completes the start-up, and the reference voltage source enters the normal working state.

Preferably, step S2 includes: when the voltage of point c of the first-order compensation circuit is raised for some reason, the voltage of node d will be pulled down, the voltage of node e will be raised, and the voltage of node c will decrease accordingly, The voltage of node c is stabilized; set the third N-type field effect transistor (MN3), the fourth N-type field effect transistor (MN4), the third P-type field effect transistor (MP3) and the fourth P-type field effect transistor ( MP4) are equal in width to length ratio, so that the drain-source currents of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4) are equal, thereby ensuring that the voltage values of node a and node b are equal; according to the structure of the first-order compensation circuit, the following relationship is obtained:

V _SG(MP8) +V _GS(MN3) =V _SG(MP9) +I ₁ R ₁ +V _SG(MN4) (1)

Among them, V _SG(MP8) , V _GS(MN3) , V _SG(MP9) and V _SG(MN4) are the eighth P-type field effect transistor MP8, the third N-type field effect transistor MN3, and the ninth P-type field effect transistor, respectively. The gate-source voltage of the effect transistor MP9 and the fourth N-type field effect transistor MN4, _I1 is the current flowing through R1. Because the width to length ratios of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4) and their drain-source currents are equal, the gate-source voltages of the MN3 and MN4 transistors are equal. According to formula (1), the expression of current I ₁ is obtained:

Wherein, M=[I _MP8 (W/L) _MP9 ]/[I _MP9 (W/L) _MP8 ], by setting the width to length ratio of the fourth P-type field effect transistor MP4 and the sixth P-type field effect transistor MP6 to be equal , to ensure that the currents flowing through R1 and R2 are equal, and then the expression for the first-order reference voltage is:

V _EBQ1 is the base-emitter voltage of the bipolar transistor Q1, wherein the seventh P-type field effect transistor MP7, the eighth P-type field effect transistor MP8 and the ninth P-type field effect transistor MP9 work in the sub-threshold region, Other MOS tubes work in the saturation region, and the first-order temperature compensation curve is obtained by setting the values of resistors R1 and R2.

Compared with the prior art, the present invention has the following advantages:

By using the second N-type field effect transistor MN2, the third N-type field effect transistor MN3, the fourth N-type field effect transistor MN4, the fourth P-type field effect transistor MP4, and the fifth P-type field effect transistor using the first-order compensation circuit The negative feedback loop formed by MP5 replaces the operational amplifier of the traditional reference voltage source to stabilize the node voltage, which simplifies the circuit design and implementation complexity, and reduces the area of the circuit at the same time; the seventh P-type working in a specific state is used The field effect transistor MP7, the eighth P-type field effect transistor MP8 and the ninth P-type field effect transistor MP9 replace the bipolar transistors of the traditional reference voltage source to generate a voltage difference with a positive temperature coefficient, reducing the mismatch between different processes At the same time, the area of the circuit is further reduced; the high-order term of the temperature coefficient is compensated by a specific circuit, so that the accuracy and stability of the reference voltage source are effectively improved. Only one bipolar transistor is used in the entire voltage reference circuit, which can reduce the mismatch problem between different process methods and save the area of the chip circuit; simulation proves that the output reference voltage (Vref) is lower than 1V, which is relatively The traditional bandgap reference voltage source with an output voltage of about 1.25V can provide a more stable voltage reference value for low-voltage circuits;

Description of drawings

FIG. 1 is a circuit diagram of a conventional reference voltage source.

FIG. 2 is a structural block diagram of the reference voltage source of the present invention.

FIG. 3 is a circuit diagram of a start-up circuit and a first-order compensation circuit of the present invention.

4 is a circuit diagram of the higher order compensation circuit and ICTAT current generator circuit of the present invention.

FIG. 5 is a working method of the reference voltage source of the present invention.

FIG. 6 is a schematic diagram of the principle of the high-order compensation reference voltage of the present invention.

Figure 7 is a schematic diagram of the output voltage versus temperature at the TT process corner.

Figure 8 is a schematic diagram of the output voltage versus temperature at the FF process corner.

Figure 9 is a schematic diagram of the output voltage versus temperature at the SS process corner.

FIG. 10 is a simulation schematic diagram of the linear regulation ratio of the output voltage as a function of the power supply voltage.

Fig. 11 The simulation schematic diagram of the power supply rejection ratio PSRR of the output voltage under different supply voltages.

Figure 12 is a simulation schematic diagram of the power supply rejection ratio PSRR of the output voltage at the TT, FF, and SS process corners.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings and embodiments.

Referring to Figures 2-4, a reference voltage source includes a start-up circuit, a first-order compensation circuit, a high-order compensation circuit for reducing the temperature coefficient of the reference voltage (output voltage, Vref), and a reference for reducing the reference voltage. The ICTAT current generator circuit of the power supply voltage regulation rate of the voltage; the first-order compensation circuit includes the third P-type field effect transistor MP3, the fourth P-type field effect transistor MP4, the fifth P-type field effect transistor MP5, the sixth P-type field effect transistor MP5, and the sixth P-type field effect transistor. Type FET MP6, the seventh P-type FET MP7, the eighth P-type FET MP8, the ninth P-type FET MP9, the second N-type FET MN2, the third N-type FET MN3 , the fourth N-type field effect transistor MN4, the resistor R1, the resistor R2 and the bipolar transistor Q1; the gate of the third P-type field effect transistor MP3, the gate of the fourth P-type field effect transistor MP4, the fifth P-type field effect transistor The gate and drain of the field effect transistor MP5 and the gate of the sixth P-type field effect transistor MP6 are all connected to the high-order compensation circuit, the gate of the third P-type field effect transistor MP3 is also connected to the start-up circuit, and the third P-type field effect transistor MP3 is also connected to the start-up circuit. The source of the type FET MP3, the source of the fourth P-type FET MP4, the source of the fifth P-type FET MP5, and the source of the sixth P-type FET MP6 are all connected to the input voltage VDD , the drain of the fifth P-type field effect transistor MP5 is connected to the drain of the second N-type field effect transistor MN2; the source of the second N-type field effect transistor MN2 is connected to the source of the seventh P-type field effect transistor MP7, The gate of the second N-type field effect transistor MN2 is connected to the drain of the third N-type field effect transistor MN3 and the drain of the third P-type field effect transistor MP3; the drain of the seventh P-type field effect transistor MP7 and The gates are all grounded; the source of the third N-type field effect transistor MN3 is connected to the source of the eighth P-type field effect transistor MP8, the gate of the third N-type field effect transistor MN3 and the fourth N-type field effect transistor MN4 The gate, the drain of the fourth N-type field effect transistor MN4, and the drain of the fourth P-type field effect transistor MP4 are connected; the source of the fourth N-type field effect transistor MN4 is connected to one end of the resistor R1; The other end is connected to the source of the ninth P-type field effect transistor MP9; the gate and drain of the eighth P-type field effect transistor MP8, and the gate and drain of the ninth P-type field effect transistor MP9 are grounded; The drain of the FET MP6 is connected to one end of the resistor R2; the other end of the resistor R2 is connected to the emitter of the bipolar transistor Q1, and the base and the collector of the bipolar transistor Q1 are both grounded.

In this embodiment, the startup circuit includes: a first P-type field effect transistor MP1, a second P-type field effect transistor MP2 and a first N-type field effect transistor MN1; the source of the first P-type field effect transistor MP1 and the The input voltage VDD is connected, and the gate of the first P-type field effect transistor MP1 is connected to the gate of the third P-type field effect transistor MP3, the gate of the fourth P-type field effect transistor MP4, and the gate of the fifth P-type field effect transistor MP5. The drain, the gate of the fifth P-type field effect transistor MP5, and the gate of the sixth P-type field effect transistor MP6 are all connected, and the drain of the first P-type field effect transistor MP1 is connected to the drain of the second P-type field effect transistor MP2. The gate and the gate of the first N-type field effect transistor MN1 are both connected; the source and drain of the first N-type field effect transistor MN1 are connected to the ground, and the drain of the second P-type field effect transistor MP2 is connected to the second The gate of the N-type field effect transistor MN2 is connected.

In this embodiment, the high-order compensation circuit includes: a tenth P-type field effect transistor MP10, an eleventh P-type field effect transistor MP11, a fifth N-type field effect transistor MN5, and a sixth N-type field effect transistor MN6; The gate of the tenth P-type field effect transistor MP10 is connected to the gate of the sixth P-type field effect transistor MP6, and the source of the tenth P-type field effect transistor MP10 and the source of the eleventh P-type field effect transistor MP11 are connected to The input voltage VDD is connected, and the drain of the tenth P-type field effect transistor MP10 is connected to the drain of the fifth N-type field effect transistor MN5 and the drain of the eleventh P-type field effect transistor MP11; the eleventh P-type field effect transistor The gate of the transistor MP11 is connected to the ICTAT current generator circuit; the drain of the fifth N-type field effect transistor MN5 is also connected to the gate of the fifth N-type field effect transistor MN5 and the gate of the sixth N-type field effect transistor MN6 , the source of the fifth N-type field effect transistor MN5 is grounded; the drain of the sixth N-type field effect transistor MN6 is connected to the drain of the sixth P-type field effect transistor MP6, and the source of the sixth N-type field effect transistor MN6 ground. As shown in FIG. 6 , the working principle of the high-order compensation reference voltage provided by the embodiment of the present invention is that the base-emitter voltage V _BE of the bipolar transistor constitutes a negative temperature coefficient voltage inversely proportional to temperature, and the eighth The gate-drain voltage difference of the P-type field effect transistor MP8 and the ninth P-type field effect transistor MP9, which work in the sub-threshold region PMOS transistor, constitutes a positive temperature coefficient voltage proportional to the temperature, and the negative temperature coefficient voltage is proportional to the temperature. The positive temperature coefficient voltages are added to obtain a first-order reference voltage value Vref1. Then, the output voltage Vref of the high-order curvature compensation reference is obtained by subtracting the curve Vcompensate and Vref1, which has a similar temperature characteristic to the first-order reference voltage. The temperature characteristic curve of Vref is a sinusoidal function, so the temperature coefficient of the reference voltage can be effectively reduced.

In this embodiment, the ICTAT current generator circuit includes: a twelfth P-type field effect transistor MP12, a thirteenth P-type field effect transistor MP13, a fourteenth P-type field effect transistor MP14, and a seventh N-type field effect transistor tube MN7, eighth N-type field effect transistor MN8 and resistor R3; the gate of the twelfth P-type field effect transistor MP12, the gate of the thirteenth P-type field effect transistor MP13 and the fourteenth P-type field effect transistor MP14 The gate is connected to the gate of the eleventh P-type field effect transistor MP11, the source of the twelfth P-type field effect transistor MP12, the source of the thirteenth P-type field effect transistor MP13 and the fourteenth P-type field effect transistor The source of the effect transistor MP14 is connected to the input voltage VDD, the drain of the twelfth P-type field effect transistor MP12 is connected to the gate of the seventh N-type field effect transistor MN7 and one end of the resistor R3; the other end of the resistor R3 is grounded; The drain of the thirteenth P-type field effect transistor MP13 is connected to the drain of the seventh N-type field effect transistor MN7; the source of the seventh N-type field effect transistor MN7 is grounded; the drain of the fourteenth P-type field effect transistor MP14 It is connected to the gate of the fourteenth P-type field effect transistor MP14 and the drain of the eighth N-type field effect transistor MN8; the gate of the eighth N-type field effect transistor MN8 is connected to the drain of the seventh N-type field effect transistor MN7 ; The source of the eighth N-type field effect transistor MN8 is grounded.

Referring to Fig. 5, the working method of the reference voltage source applicable to the above reference voltage source is low, including:

S1, when the power supply is powered on, the startup circuit starts normally, and the reference voltage source enters the normal working state;

S2, the second N-type FET MN2, the third N-type FET MN3, the fourth N-type FET MN4, the fourth P-type FET MP4, and the fifth P-type FET of the first-order compensation circuit MP5 forms a negative feedback loop to maintain the same voltage at the preset node. The seventh P-type field effect transistor MP7, the eighth P-type field effect transistor MP8 and the ninth P-type field effect transistor MP9 work in the sub-threshold region, and pass the PMOS transistor. The voltage difference between them produces a current IPTAT with a positive temperature coefficient, which is copied to the output of the reference voltage source through a current mirror;

S3, the ICTAT current generator circuit generates a negative temperature coefficient current ICTAT that does not vary with the supply voltage.

S4, the high-order compensation circuit copies the current ICTAT to the output terminal of the reference voltage source, and the current combined with the current IPTAT forms a high-order compensation voltage in the resistor R2 to compensate the first-order reference voltage.

In this embodiment, step S1 includes: when the power supply is powered on, the gate of the first N-type field effect transistor MN1 is at a low potential, the second P-type field effect transistor MP2 is turned on, and the gate of the second N-type field effect transistor MN2 is turned on. It becomes a high level, the second N-type field effect transistor MN2 is turned on, and the current flows through the fifth P-type field effect transistor MP5, the second N-type field effect transistor MN2 and the seventh P-type field effect transistor MP7 to the ground, and the The gate potential of the fifth P-type field effect transistor MP5 is pulled down, and the start-up circuit starts to start; at the same time, the current passes through the first P-type field effect transistor MP1 to charge the second P-type field effect transistor MP2, and the second P-type field effect transistor MP2 The gate potential gradually increases, and when it increases to a preset threshold voltage value lower than the power supply, the second P-type field effect transistor MP2 is turned off, the start-up circuit completes the start-up, and the reference voltage source enters the normal working state.

In this embodiment, step S2 includes:

In the first-order compensation circuit, the seventh P-type field effect transistor MP7, the eighth P-type field effect transistor MP8 and the ninth P-type field effect transistor MP9 operating in the sub-threshold region are used to replace the bipolar transistors in the conventional reference voltage source. When the CMOS tube works in the sub-threshold region and satisfies V _ds ≥ 4V _T , V _ds is the drain-source voltage, and V _T is the thermal voltage. The relationship between the MOS tube source-drain current I _ds and the temperature T is as follows:

Among them, the mobility μ is μT=μ ₀ ·T/T ₀ ^-m , C _ox is the gate oxide capacitance per unit area, η is the subthreshold slope factor, W/L is the aspect ratio of the MOS transistor, and the threshold voltage V _TH is V _TH =V _TH T ₀ -k ₁ T, V _TH T ₀ is the threshold voltage when the temperature is 0K, k ₁ is a constant, approximately equal to 2mV/°C, m is also a constant, and the value is between 1.5 and 2. It can be derived from formula (4) that:

It can be seen from equation (5) that the MOS transistors working in the sub-threshold region and the bipolar transistors have similar temperature characteristics, so the MOS transistors operating in the sub-threshold region can be used instead of bipolar transistors to design a first-order reference circuit.

The present invention uses the second N-type field effect transistor MN2, the third N-type field effect transistor MN3, the fourth N-type field effect transistor MN4, the fourth P-type field effect transistor MP4, and the fifth P-type field effect transistor MP5 to form negative feedback The loop is used to stabilize the voltage values of node a and node b. The specific feedback process is that when the voltage of point c of the first-order compensation circuit is raised for some reason, the voltage of node d will be pulled down and raised. The voltage of node e, the voltage of node c drops accordingly, and the voltage of node c is stabilized;

Set the width to length ratio of the third N-type field effect transistor (MN3), the fourth N-type field effect transistor (MN4), the third P-type field effect transistor (MP3) and the fourth P-type field effect transistor (MP4) to be equal , so that the drain-source currents of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4) are equal, thereby ensuring that the voltage values of node a and node b are equal; according to the first-order compensation circuit structure , the following relationship is obtained:

V _SG(MP8) +V _GS(MN3) =V _SG(MP9) +I ₁ R ₁ +V _SG(MN4) (1)

Among them, V _SG(MP8) , V _GS(MN3) , V _SG(MP9) and V _SG(MN4) are the eighth P-type field effect transistor MP8, the third N-type field effect transistor MN3, and the ninth P-type field effect transistor, respectively. The gate-source voltage of the effect transistor MP9 and the fourth N-type field effect transistor MN4, _I1 is the current flowing through R1. Because the width to length ratios of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4) and their drain-source currents are equal, the gate-source voltages of the MN3 and MN4 transistors are equal. According to formula (1), the expression of current I ₁ is obtained:

Wherein, M=[I _MP8 (W/L) _MP9 ]/[I _MP9 (W/L) _MP8 ], by setting the width to length ratio of the fourth P-type field effect transistor MP4 and the sixth P-type field effect transistor MP6 to be equal , to ensure that the currents flowing through R1 and R2 are equal, and then the expression for the first-order reference voltage is:

V _EBQ1 is the base-emitter voltage of the bipolar transistor Q1, wherein the seventh P-type field effect transistor MP7, the eighth P-type field effect transistor MP8 and the ninth P-type field effect transistor MP9 work in the sub-threshold region, Other MOS tubes work in the saturation region. By setting the values of resistors R1 and R2, a first-order temperature compensation curve is obtained. This temperature curve is a parabola with an upward opening.

All MOS transistors in the high-order compensation circuit work in the saturation region, and the gate-source voltage of the corresponding MOS transistor can be expressed as:

where V _thn7 is the threshold voltage of the MN7 tube, μ _n is the mobility of electrons, and the current flowing through the resistor R ₃ is:

Substituting equation (6) into equation (7), we get:

By arranging equation (8), a quadratic equation of one variable about I _ds is obtained. Therefore, the current flowing through resistor _R3 is:

At the same time, the high-order curvature compensation current I ₅ satisfies:

Substituting the current _I3 in Equation (9) into Equation 10, the expression of the high-order curvature compensation current can be obtained as:

in,

The current I ₅ is converted into the high-order compensation voltage V _comp through the resistor R ₂ , and this voltage can be used to compensate the first-order reference voltage V _ref1 . By properly setting the parameters of the MOS transistor, the high-order compensation output voltage reference value V _ref can be obtained.

Taking the first derivative of the current I ₅ in equation (11) with respect to the temperature T, we can get:

in,

C=[BηKL _n M(W/L) _MP10 ]/[R ₁ (W/L) _MP4 ]-Ak ₁ /R ₃

E=2R ₃ C _ox (W/L) _MN7

Here C, D, and E are all constants. Let the left side of the equal sign of equation (12) be zero, and solve the equation on the right side of the equal sign, we can get:

The temperature value T ₁ is the extreme point of the second-order compensation current I _5. Since it is necessary to verify the change trend of the second-order compensation current, the second-order derivative of the second-order compensation current I ₅ is obtained:

The value on the left side of the equal sign in equation (14) is greater than zero, which can be obtained by calculation:

In the entire normal working temperature range, the formula (15) can be satisfied by setting the value of parameter E reasonably. In this case, the value of equation (14) remains positive, so the opening of the temperature change curve of current _I5 is upward, which is the same as the change trend of the temperature of the first-order reference voltage, so this current can be used to compensate the first-order voltage reference.

The high-order compensation current I ₅ generates a high-order compensation voltage on the resistor R ₂ , and this voltage is subtracted from the first-order reference voltage V _ref1 , and the output expression of the reference voltage is obtained as:

V _ref =V _EB1 +(I _PTAT -I ₅ )R ₂ (16)

Substituting equations (2) and (11) into equation (16), the output voltage of the voltage reference is obtained as:

7-9 are schematic diagrams illustrating the variation of output voltage with temperature under three main process angles of TT, FF, and SS provided by an embodiment of the present invention. As shown in Figures 7 and 8, when the process angles are TT and FF, the output voltage shows a temperature characteristic with good consistency, and the output curve is an ideal sinusoidal curve; as shown in Figure 9, when the process angle is SS, In the temperature curve of the output voltage, the pole position changes, but the sinusoidal trend of temperature does not change; when the process angle is TT, the lowest temperature coefficient value can be obtained as 3.6ppm/℃; when the process angle is FF, the temperature characteristics The worst, the temperature coefficient value is 7.4ppm/°C, which is lower than 10ppm/°C. At different process corners, due to process deviations, the average deviation value of the reference output voltage V _ref between every two process corners is 40mV, so it meets the design requirements for process deviations.

10 is a schematic diagram illustrating the simulation of the linear adjustment ratio of the output voltage with the change of the power supply voltage according to the embodiment of the present invention. When the power supply voltage reaches 1.7V, the reference voltage _Vref can output a normal voltage value; when the power supply voltage increases from 1.7V When it reaches 3.5V, the output voltage changes from 902.122mV to 902.112mV, the change range is 10μV, the linear adjustment rate is only 5μV/V, and the change of the power supply voltage has little influence on the reference output voltage value.

11 is a schematic diagram of the simulation of the power supply rejection ratio PSRR of the output voltage provided by the embodiment of the present invention under different power supply voltages. The present invention analyzes four sets of data when the power supply voltage is 1.7V, 2.5V, 3V and 3.5V respectively. Compared with the simulation, the results show that the power supply rejection ratio of the reference voltage increases gradually with the increase of the power supply voltage. Since the system startup voltage is 1.7V and the power supply voltage is 1.7V, the simulation results show that the low-frequency PSRR value is -67.1dB, and the power supply rejection ratio is still close to -50dB when the frequency is 1MHz; when the power supply voltage rises to 3.5V, the The power supply rejection ratio of the circuit is close to -90dB. Therefore, the reference voltage source provided by the embodiment of the present invention has good power supply suppression, and can effectively suppress the variation of the reference output voltage caused by the fluctuation of the power supply voltage.

12 is a schematic diagram of the simulation of the power supply rejection ratio PSRR of the output voltage at the TT, FF and SS process corners when the power supply voltage is 2.5V according to an embodiment of the present invention. The results show that the worst case of PSRR occurs at the FF process corner. The PSRR value at 1KHz is -79.7dB; the best case occurs at the SS process corner, where the PSRR value is -81.6dB at 1KHz; the PSRR value at the TT process corner is between the two. For different process angles, the difference between the best and worst case PSRR values is only 1.9dB. Therefore, the PSRR curve parameters show a high degree of consistency under different process angles, and the average power supply rejection ratio is maintained at about -80dB, which plays a good role in power supply rejection.

The above-mentioned specific embodiments are the preferred embodiments of the present invention, and do not limit the present invention. Any other changes or other equivalent replacement methods that do not deviate from the technical solutions of the present invention are included in the protection scope of the present invention. within.

Claims (7)

1. A reference voltage source, characterized in that it comprises: a start-up circuit, a first-order compensation circuit, a high-order compensation circuit for reducing the temperature coefficient of the reference voltage, and a power supply voltage regulation rate for reducing the reference voltage, which are connected in sequence. The ICTAT current generator circuit; The first-order compensation circuit includes a third P-type field effect transistor (MP3), a fourth P-type field effect transistor (MP4), a fifth P-type field effect transistor (MP5), and a sixth P-type field effect transistor (MP6) , the seventh P-type field effect transistor (MP7), the eighth P-type field effect transistor (MP8), the ninth P-type field effect transistor (MP9), the second N-type field effect transistor (MN2), the third N-type field effect transistor Effect transistor (MN3), fourth N-type field effect transistor (MN4), resistor R1, resistor R2 and bipolar transistor Q1; The gate of the third P-type field effect transistor (MP3), the gate of the fourth P-type field effect transistor (MP4), the gate and drain of the fifth P-type field effect transistor (MP5), the sixth P-type field effect transistor The gates of the effect transistors (MP6) are connected to the high-order compensation circuit, the gates of the third P-type field effect transistors (MP3) are also connected to the start-up circuit, the source and the third P-type field effect transistors (MP3) are connected to the start-up circuit. The source of the four P-type field effect transistors (MP4), the source of the fifth P-type field effect transistor (MP5), and the source of the sixth P-type field effect transistor (MP6) are all connected to the input voltage (VDD). The drain of the five P-type field effect transistors (MP5) is connected to the drain of the second N-type field effect transistor (MN2); the source of the second N-type field effect transistor (MN2) is connected to the seventh P-type field effect transistor ( MP7) is connected to the source, and the gate of the second N-type field effect transistor (MN2) is connected to the drain of the third N-type field effect transistor (MN3) and the drain of the third P-type field effect transistor (MP3); The drain and gate of the seventh P-type field effect transistor (MP7) are grounded; the source of the third N-type field effect transistor (MN3) is connected to the source of the eighth P-type field effect transistor (MP8), and the third The gate of the N-type field effect transistor (MN3) and the gate of the fourth N-type field effect transistor (MN4), the drain of the fourth N-type field effect transistor (MN4), the fourth P-type field effect transistor (MP4) The drain of the fourth N-type field effect transistor (MN4) is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the source of the ninth P-type field effect transistor (MP9); the eighth P-type field effect transistor (MP9) The gate and drain of the effect transistor (MP8) and the gate and drain of the ninth P-type field effect transistor (MP9) are grounded; the drain of the sixth P-type field effect transistor (MP6) is connected to one end of the resistor R2 ; The other end of the resistor R2 is connected to the emitter of the bipolar transistor Q1, and the base and the collector of the bipolar transistor Q1 are both grounded. 2. The reference voltage source according to claim 1, wherein the start-up circuit comprises: a first P-type field effect transistor (MP1), a second P-type field effect transistor (MP2) and a first N-type field effect transistor Effect tube (MN1); The source of the first P-type field effect transistor (MP1) is connected to the input voltage (VDD), the gate of the first P-type field effect transistor (MP1) is connected to the gate of the third P-type field effect transistor (MP3), the The gate of the four P-type field effect transistors (MP4), the drain of the fifth P-type field effect transistor (MP5), the gate of the fifth P-type field effect transistor (MP5), the sixth P-type field effect transistor (MP6) ) are connected to the gates, and the drain of the first P-type field effect transistor (MP1) is connected to the gate of the second P-type field effect transistor (MP2) and the gate of the first N-type field effect transistor (MN1). ; The source and drain of the first N-type field effect transistor (MN1) are connected to ground, and the drain of the second P-type field effect transistor (MP2) and the gate of the second N-type field effect transistor (MN2) are connected . 3. The reference voltage source according to claim 1, wherein the high-order compensation circuit comprises: a tenth P-type field effect transistor (MP10), an eleventh P-type field effect transistor (MP11), a fifth N-type FET (MN5) and the sixth N-type FET (MN6); The gate of the tenth P-type field effect transistor (MP10) is connected to the gate of the sixth P-type field effect transistor (MP6), the source of the tenth P-type field effect transistor (MP10), the eleventh P-type field effect transistor The source of the transistor (MP11) is connected to the input voltage (VDD), the drain of the tenth P-type field effect transistor (MP10) is connected to the drain of the fifth N-type field effect transistor (MN5), and the eleventh P-type field effect transistor The drain of the transistor (MP11) is connected to the drain; the gate of the eleventh P-type field effect transistor (MP11) is connected to the ICTAT current generator circuit; the drain of the fifth N-type field effect transistor (MN5) is also connected to the fifth N-type The gate of the field effect transistor (MN5) is connected to the gate of the sixth N-type field effect transistor (MN6), and the source of the fifth N-type field effect transistor (MN5) is grounded; the sixth N-type field effect transistor (MN6) The drain is connected to the drain of the sixth P-type field effect transistor (MP6), and the source of the sixth N-type field effect transistor (MN6) is grounded. 4. The reference voltage source according to claim 1, wherein the ICTAT current generator circuit comprises: a twelfth P-type field effect transistor (MP12), a thirteenth P-type field effect transistor (MP13), The fourteenth P-type field effect transistor (MP14), the seventh N-type field effect transistor (MN7), the eighth N-type field effect transistor (MN8) and the resistor R3; the gate of the twelfth P-type field effect transistor (MP12) pole, the gate of the thirteenth P-type field effect transistor (MP13) and the gate of the fourteenth P-type field effect transistor (MP14) are connected to the gate of the eleventh P-type field effect transistor (MP11). The source of the two P-type field effect transistors (MP12), the source of the thirteenth P-type field effect transistor (MP13) and the source of the fourteenth P-type field effect transistor (MP14) are connected to the input voltage (VDD), The drain of the twelfth P-type field effect transistor (MP12) is connected to the gate of the seventh N-type field effect transistor (MN7) and one end of the resistor R3; the other end of the resistor R3 is grounded; the thirteenth P-type field effect transistor ( The drain of MP13) is connected to the drain of the seventh N-type field effect transistor (MN7); the source of the seventh N-type field effect transistor (MN7) is grounded; the drain of the fourteenth P-type field effect transistor (MP14) It is connected to the gate of the fourteenth P-type field effect transistor (MP14) and the drain of the eighth N-type field effect transistor (MN8); the gate of the eighth N-type field effect transistor (MN8) is connected to the seventh N-type field The drain of the effect transistor (MN7); the source of the eighth N-type field effect transistor (MN8) is grounded. 5. A working method for a reference voltage source, comprising: S1, when the power supply is powered on, the startup circuit starts normally, and the reference voltage source enters the normal working state; S2, the second N-type FET (MN2), the third N-type FET (MN3), the fourth N-type FET (MN4), and the fourth P-type FET (MP4) of the first-order compensation circuit , the fifth P-type field effect transistor (MP5) forms a negative feedback loop to maintain the voltage of the preset node equal, the seventh P-type field effect transistor (MP7), the eighth P-type field effect transistor (MP8) and the ninth P-type field effect transistor (MP8) The field effect transistor (MP9) works in the sub-threshold region, and generates a current IPTAT with a positive temperature coefficient through the voltage difference between the PMOS transistors, and the current IPTAT is copied to the output end of the reference voltage source through the current mirror; S3, the ICTAT current generator circuit generates a negative temperature coefficient current ICTAT that does not vary with the power supply voltage; S4, the high-order compensation circuit copies the current ICTAT to the output terminal of the reference voltage source, and the current combined with the current IPTAT forms a high-order compensation voltage in the resistor R2 to compensate the first-order reference voltage. 6. The working method of the reference voltage source according to claim 5, wherein step S1 comprises: When the power supply is powered on, the gate of the first N-type field effect transistor (MN1) is low potential, the second P-type field effect transistor (MP2) is turned on, and the gate of the second N-type field effect transistor (MN2) becomes high level, the second N-type field effect transistor (MN2) is turned on, and the current flows through the fifth P-type field effect transistor (MP5), the second N-type field effect transistor (MN2) and the seventh P-type field effect transistor (MP7) ) to the ground, the gate potential of the fifth P-type field effect transistor (MP5) is pulled down, and the start-up circuit starts to start; The current charges the second P-type field effect transistor (MP2) through the first P-type field effect transistor (MP1), and the gate potential of the second P-type field effect transistor (MP2) gradually increases. When the threshold voltage value is set, the second P-type field effect transistor (MP2) is turned off, the start-up circuit completes the start-up, and the reference voltage source enters the normal working state. 7. The working method of the reference voltage according to claim 5, wherein step S2 comprises: When the voltage of point c of the first-order compensation circuit is raised for some reason, the voltage of node d will be pulled down, the voltage of node e will be raised, the voltage of node c will decrease, and the voltage of node c will be stabilized; Set the width to length ratio of the third N-type field effect transistor (MN3), the fourth N-type field effect transistor (MN4), the third P-type field effect transistor (MP3) and the fourth P-type field effect transistor (MP4) to be equal , so that the drain-source currents of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4) are equal, thereby ensuring that the voltage values of node a and node b are equal; according to the first-order compensation circuit structure , the following relationship is obtained: V _SG(MP8) +V _GS(MN3) =V _SG(MP9) +I ₁ R ₁ +V _SG(MN4) (1) Among them, V _{SG (MP8)} , V _{GS (MN3)} , V _{SG (MP9)} and V _{SG (MN4)} are the eighth P-type field effect transistor (MP8), the third N-type field effect transistor (MN3), the third The gate-source voltage of the nine P-type field effect transistors (MP9) and the fourth N-type field effect transistor (MN4), I ₁ is the current flowing through R1; because the third N-type field effect transistor (MN3), the fourth The width-length ratio of the N-type field effect transistor (MN4) and its drain-source current are equal, so the gate-source terminals of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4) are made equal. The voltages are equal; according to the formula (1), the expression of the current I ₁ is obtained: Among them, M=[I _MP8 (W/L) _MP9 ]/[I _MP9 (W/L) _MP8 ], by setting the fourth P-type field effect transistor (MP4) and the sixth P-type field effect transistor (MP6) The width to length ratio is equal to ensure that the currents flowing through R1 and R2 are equal, and then the expression for the first-order reference voltage is: V _{EB (Q1)} is the base-emitter voltage of the bipolar transistor Q1, wherein the seventh P-type field effect transistor (MP7), the eighth P-type field effect transistor (MP8) and the ninth P-type field effect transistor (MP9) works in the sub-threshold region, and other MOS tubes work in the saturation region. By setting the values of the resistors R1 and R2, the first-order temperature compensation curve is obtained.