CN109491439A - A kind of reference voltage source and its working method - Google Patents
A kind of reference voltage source and its working method Download PDFInfo
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- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention discloses a kind of reference voltage sources, comprising: the start-up circuit that is sequentially connected, first compensation phase circuit, the high order compensation circuit of temperature coefficient for reducing reference voltage and the line-voltage regulation for reducing reference voltage ICTAT current generator circuit；The operational amplifier of traditional benchmark voltage source is replaced to realize the stabilization of node voltage by the feedback loop formed using the second N-type field-effect tube MN2 of first compensation phase circuit, third N-type field-effect tube MN3, the 4th N-type field-effect tube MN4, the 4th p-type field-effect tube MP4, the 5th p-type field-effect tube MP5, the complexity in circuit design and realization simplified, while reducing the area of circuit.
Description
Technical Field
The invention relates to the technical field of analog integrated circuits, in particular to a reference voltage source and a working method thereof.
Background
The reference voltage source is a basic component unit of an analog integrated circuit, and the precision and the stability of the reference voltage source directly influence the operation of the whole circuit system. Reference voltage sources are widely used in digital, analog and digital-analog mixed signal systems, for example, a/D, D/a converters, memories, phase-locked loops, etc. systems need to use the reference voltage source to determine the range of their input and output signals and take into account the influence of the reference voltage source on the gain and noise of these systems. With the development of very large scale integrated circuits, tens of millions of transistors, operators and controllers are integrated on a chip with a few square microns, so that the demand for a reference voltage source with small area, high precision and high stability is increasing.
The precision and stability of the reference voltage source are measured by two indexes, namely a temperature coefficient and a power supply voltage regulation rate, so that the temperature coefficient and the power supply voltage regulation rate should be reduced as much as possible to realize the reference voltage source with small area, high precision and high stability. The traditional reference voltage source maintains the voltage value of a specific node through an operational amplifier and generates a voltage difference with a positive temperature coefficient through a bipolar transistor, but the requirements for reducing the area of a chip are difficult to achieve due to the fact that the areas of the operational amplifier and the bipolar transistor are generally large. In addition, the conventional reference voltage source adds a voltage proportional to an absolute temperature and a voltage inversely proportional to the absolute temperature to realize a reference voltage having a zero temperature characteristic. However, the temperature coefficient of the reference voltage generated by this method is high, and is usually between 20 and 100 ppm/DEG C. Fig. 1 is a schematic diagram of a reference voltage source in the conventional technology, in which an operational principle of the conventional reference voltage source is to utilize an operational amplifier a1 to stabilize voltage values at points a and b, a voltage difference between bipolar transistors Q1 and Q2 generates a temperature-proportional current on a resistor R3, and the current is mirrored on a resistor R4 through an M3 transistor to form a temperature-proportional voltage VPTAT. Since the base-emitter voltage of the bipolar transistor is inversely proportional to the temperature, an output reference voltage independent of the temperature can be obtained by superposing the voltage and VPTAT. The traditional reference voltage source is widely applied due to mature technical method, but the design only considers the cancellation of a first-order temperature term, so that the base electrode-emitter voltage V of the bipolar transistor is causedBEStill contains high-order terms. Therefore, the temperature coefficient of such a conventional first-order reference voltage source is high, typically above 20 ppm/deg.C; and because a plurality of bipolar transistors are used in the traditional reference voltage sourceThe tube, thereby increasing the area of the chip, making cost reduction difficult. In order to solve the problem of too high temperature coefficient, some compensation methods are proposed, such as exponential compensation technology, and piecewise linear compensation method, which can compensate the temperature coefficient of the reference voltage source well, but inevitably needs to be implemented by using an operational amplifier in the circuit, resulting in an increase in chip area. In recent years, in order to solve the problem of the excessive chip area, a design method of a reference voltage source without an operational amplifier has been proposed, but in these circuit designs using the reference voltage source without the operational amplifier, key parameters such as a temperature coefficient and a power supply voltage adjustment rate are increased accordingly, which results in deterioration of the precision and stability of the circuit; meanwhile, because a large number of bipolar transistors are integrated in the circuit, the area of the reference voltage source module without the operational amplifier is large, and therefore the requirement of the development of the modern super-large-scale integrated circuit on the design of the reference voltage source still cannot be met.
Therefore, there is a need in the industry to develop a reference voltage source that improves the accuracy and stability of the reference voltage source and reduces the area of the reference voltage source chip on the basis of reducing the complexity of the conventional reference voltage source in circuit design and implementation.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a reference voltage source.
It is another object of the present invention to overcome the above disadvantages of the prior art by providing a low reference voltage operating method.
The purpose of the invention is realized by the following technical scheme:
a reference voltage source comprising: the circuit comprises a starting circuit, a first-order compensation circuit, a high-order compensation circuit for reducing the temperature coefficient of reference voltage and an ICTAT current generator circuit for reducing the power supply voltage regulation rate of the reference voltage, which are connected in sequence; the first-order compensation circuit comprises a third P-type field effect transistor MP3, a fourth P-type field effect transistor MP4, a fifth P-type field effect transistor MP5, a sixth P-type field effect transistor MP6, a seventh P-type field effect transistor MP7, an eighth P-type field effect transistor MP8, a ninth P-type field effect transistor MP9, a second N-type field effect transistor MN2, a third N-type field effect transistor MN3, a fourth N-type field effect transistor MN4, a resistor R1, a resistor R2 and a bipolar transistor Q1; the grid electrode of the third P-type field effect transistor MP3, the grid electrode of the fourth P-type field effect transistor MP4, the grid electrode and the drain electrode of the fifth P-type field effect transistor MP5 and the grid electrode of the sixth P-type field effect transistor MP6 are all connected with a high-order compensation circuit, the grid electrode of the third P-type field effect transistor MP3 is also connected with a starting circuit, the source electrode of the third P-type field effect transistor MP3, the source electrode of the fourth P-type field effect transistor MP4, the source electrode of the fifth P-type field effect transistor MP5 and the source electrode of the sixth P-type field effect transistor MP6 are all connected with an input voltage VDD, and the drain electrode of the fifth P-type field effect transistor MP5 is connected with the drain electrode of the second N-type field effect transistor; the source electrode of the second N-type field effect transistor MN2 is connected with the source electrode of the seventh P-type field effect transistor MP7, and the grid electrode of the second N-type field effect transistor MN2 is connected with the drain electrode of the third N-type field effect transistor MN3 and the drain electrode of the third P-type field effect transistor MP 3; the drain and the gate of the seventh P-type field effect transistor MP7 are both grounded; the source electrode of the third N-type field effect transistor MN3 is connected with the source electrode of the eighth P-type field effect transistor MP8, and the grid electrode of the third N-type field effect transistor MN3 is connected with the grid electrode of the fourth N-type field effect transistor MN4, the drain electrode of the fourth N-type field effect transistor MN4 and the drain electrode of the fourth P-type field effect transistor MP 4; the source electrode of the fourth N-type field effect transistor MN4 is connected with one end of a resistor R1; the other end of the resistor R1 is connected with the source electrode of the ninth P-type field effect transistor MP 9; the grid and the drain of the eighth P-type field effect transistor MP8 and the grid and the drain of the ninth P-type field effect transistor MP9 are both grounded; the drain electrode of the sixth P-type field effect transistor MP6 is connected with one end of the resistor R2; the other end of the resistor R2 is connected with the emitter of the bipolar transistor Q1, and the base and the collector of the bipolar transistor Q1 are both grounded.
Preferably, the start-up circuit includes: the first P-type field effect transistor MP1, the second P-type field effect transistor MP2 and the first N-type field effect transistor MN 1; the source electrode of the first P-type field effect transistor MP1 is connected with an input voltage VDD, the grid electrode of the first P-type field effect transistor MP1 is connected with the grid electrode of the third P-type field effect transistor MP3, the grid electrode of the fourth P-type field effect transistor MP4, the drain electrode of the fifth P-type field effect transistor MP5, the grid electrode of the fifth P-type field effect transistor MP5 and the grid electrode of the sixth P-type field effect transistor MP6, and the drain electrode of the first P-type field effect transistor MP1 is connected with the grid electrode of the second P-type field effect transistor MP2 and the grid electrode of the first N-type field effect transistor MN 1; the source and the drain of the first N-type fet MN1 are both connected to ground, and the drain of the second P-type fet MP2 is connected to the gate of the second N-type fet MN 2.
Preferably, the higher order compensation circuit includes: a tenth P-type fet MP10, an eleventh P-type fet MP11, a fifth N-type fet MN5, and a sixth N-type fet MN 6; the grid electrode of the tenth P-type field effect transistor MP10 is connected to the grid electrode of the sixth P-type field effect transistor MP6, the source electrode of the tenth P-type field effect transistor MP10 and the source electrode of the eleventh P-type field effect transistor MP11 are connected to the input voltage VDD, and the drain electrode of the tenth P-type field effect transistor MP10 is connected to the drain electrode of the fifth N-type field effect transistor MN5 and the drain electrode of the eleventh P-type field effect transistor MP 11; the grid electrode of the eleventh P-type field effect transistor MP11 is connected with an ICTAT current generator circuit; the drain electrode of the fifth N-type field effect transistor MN5 is also connected with the grid electrode of the fifth N-type field effect transistor MN5 and the grid electrode of the sixth N-type field effect transistor MN6, and the source electrode of the fifth N-type field effect transistor MN5 is grounded; the drain of the sixth N-type fet MN6 is connected to the drain of the sixth P-type fet MP6, and the source of the sixth N-type fet MN6 is grounded.
Preferably, the ICTAT current generator circuit comprises: a twelfth P-type field effect transistor MP12, a thirteenth P-type field effect transistor MP13, a fourteenth P-type field effect transistor MP14, a seventh N-type field effect transistor MN7, an eighth N-type field effect transistor MN8 and a resistor R3; the grid electrode of the twelfth P-type field effect transistor MP12, the grid electrode of the thirteenth P-type field effect transistor MP13 and the grid electrode of the fourteenth P-type field effect transistor MP14 are connected with the grid electrode of the eleventh P-type field effect transistor MP11, the source electrode of the twelfth P-type field effect transistor MP12, the source electrode of the thirteenth P-type field effect transistor MP13 and the source electrode of the fourteenth P-type field effect transistor MP14 are connected with an input voltage VDD, and the drain electrode of the twelfth P-type field effect transistor MP12 is connected with the grid electrode of the seventh N-type field effect transistor MN7 and one end of a resistor R3; the other end of the resistor R3 is grounded; the drain electrode of the thirteenth P-type field effect transistor MP13 is connected with the drain electrode of the seventh N-type field effect transistor MN 7; the source electrode of the seventh N-type field effect transistor MN7 is grounded; the drain electrode of the fourteenth P-type field effect transistor MP14 is connected with the grid electrode of the fourteenth P-type field effect transistor MP14 and the drain electrode of the eighth N-type field effect transistor MN 8; the grid electrode of the eighth N-type field effect transistor MN8 is connected with the drain electrode of the seventh N-type field effect transistor MN 7; the source of the eighth N-type fet MN8 is grounded.
The other purpose of the invention is realized by the following technical scheme:
a method of operating a reference voltage source, comprising:
s1, when the power supply is electrified, the normal start of the circuit is started, and the reference voltage source enters a normal working state;
s2, a second N-type field effect tube MN2, a third N-type field effect tube MN3, a fourth N-type field effect tube MN4, a fourth P-type field effect tube MP4 and a fifth P-type field effect tube MP5 of the first-order compensation circuit form a negative feedback loop to maintain the voltages of preset nodes to be equal, a seventh P-type field effect tube MP7, an eighth P-type field effect tube MP8 and a ninth P-type field effect tube MP9 work in a subthreshold region, a current IPTAT with a positive temperature coefficient is generated through the pressure difference between PMOS tubes, and the current IPTAT is copied to the output end of a reference voltage source through a current mirror;
s3, the ICTAT current generator circuit generates a negative temperature coefficient current ICTAT which does not change along with the supply voltage.
S4, the high-order compensation circuit copies the current ICTAT to the output end of the reference voltage source, and the current combined with the current IPTAT forms high-order compensation voltage in the resistor R2 to compensate the first-order reference voltage (output voltage, Vref).
Preferably, step S1 includes: when the power supply is powered on, the grid electrode of the first N-type field effect transistor MN1 is at a low potential, the second P-type field effect transistor MP2 is conducted, the grid electrode of the second N-type field effect transistor MN2 becomes at a high level, the second N-type field effect transistor MN2 is conducted, current flows to the ground through the fifth P-type field effect transistor MP5, the second N-type field effect transistor MN2 and the seventh P-type field effect transistor MP7, the grid potential of the fifth P-type field effect transistor MP5 is pulled down, and the starting circuit starts to be started; the current charges the second P-type field effect transistor MP2 through the first P-type field effect transistor MP1, the grid potential of the second P-type field effect transistor MP2 gradually rises, when the grid potential is lower than the preset threshold voltage value of the power supply, the second P-type field effect transistor MP2 is turned off, the starting circuit is started, and the reference voltage source enters a normal working state.
Preferably, step S2 includes: when the voltage of the point c of the first-order compensation circuit is increased for some reason, the voltage of the node d is pulled down, the voltage of the node e is increased, the voltage of the node c is decreased, and the voltage of the node c is stabilized; setting the width-to-length ratios of the third N-type field effect transistor (MN3), the fourth N-type field effect transistor (MN4), the third P-type field effect transistor (MP3) and the fourth P-type field effect transistor (MP4) to be equal, so that the drain-source end currents of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4) are equal, and the voltage values of a node a and a node b are ensured to be equal; according to the first-order compensation circuit structure, the following relation is obtained:
VSG(MP8)+VGS(MN3)＝VSG(MP9)+I1R1+VSG(MN4)(1)
wherein, VSG(MP8)、VGS(MN3)、VSG(MP9)And VSG(MN4)Gate-source end voltages I of the eighth P-type FET MP8, the third N-type FET MN3, the ninth P-type FET MP9 and the fourth N-type FET MN4 respectively1Is the current flowing through R1. Because the width-to-length ratio of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4) and the drain-source end currents thereof are equal, the gate-source end voltages of the MN3 and the MN4 are equal. According to formula (1), obtaining a current I1Expression (c):
wherein, M ═ IMP8(W/L)MP9]/[IMP9(W/L)MP8]Is passed through and is provided withThe width-to-length ratio of the fourth P-type field effect transistor MP4 to the sixth P-type field effect transistor MP6 is set to be equal, so as to ensure that the currents flowing through R1 and R2 are equal, and further obtain an expression of a first-order reference voltage as:
VEBQ1the base electrode-emitter voltage of the bipolar transistor Q1 is obtained, wherein the seventh P-type field effect transistor MP7, the eighth P-type field effect transistor MP8 and the ninth P-type field effect transistor MP9 work in a subthreshold region, other MOS transistors work in a saturation region, and a first-order temperature compensation curve is obtained by setting the values of the resistors R1 and R2.
Compared with the prior art, the invention has the following advantages:
the negative feedback loop formed by the second N-type field effect transistor MN2, the third N-type field effect transistor MN3, the fourth N-type field effect transistor MN4, the fourth P-type field effect transistor MP4 and the fifth P-type field effect transistor MP5 of the first-order compensation circuit is used for replacing an operational amplifier of a traditional reference voltage source to realize the stability of the node voltage, the complexity of circuit design and realization is simplified, and the area of the circuit is reduced; the seventh P-type field effect transistor MP7, the eighth P-type field effect transistor MP8 and the ninth P-type field effect transistor MP9 which work in a specific state are used for replacing a bipolar transistor of a traditional reference voltage source to generate a differential pressure with a positive temperature coefficient, mismatch among different processes is reduced, and meanwhile the area of a circuit is further reduced; the high-order term of the temperature coefficient is compensated through a specific circuit, so that the precision and the stability of the reference voltage source are effectively improved. Only one bipolar transistor is used in the whole voltage reference circuit, so that the mismatch problem among different process methods can be reduced, and the area of a chip circuit is saved; simulation proves that: the output reference voltage (Vref) is lower than 1V, and a more stable voltage reference value can be provided for a low-voltage circuit relative to a traditional band-gap reference voltage source with the output voltage of about 1.25V;
drawings
Fig. 1 is a circuit diagram of a conventional reference voltage source.
Fig. 2 is a block diagram of the reference voltage source of the present invention.
Fig. 3 is a circuit diagram of the start-up circuit and the first-order compensation circuit of the present invention.
Fig. 4 is a circuit diagram of the high order compensation circuit and ICTAT current generator circuit of the present invention.
Fig. 5 illustrates the operation of the reference voltage source of the present invention.
FIG. 6 is a schematic diagram of the high order compensated reference voltage of the present invention.
Fig. 7 is a graph of output voltage versus temperature at the TT process corner.
Fig. 8 is a schematic of output voltage versus temperature for FF process corner.
Fig. 9 is a schematic of output voltage versus temperature at SS process corner.
FIG. 10 is a simulation of the linear adjustment rate of output voltage as a function of supply voltage.
Fig. 11 is a simulation diagram of the power supply rejection ratio PSRR of the output voltage at different power supply voltages.
FIG. 12 is a simulation diagram of power supply rejection ratio PSRR of output voltage under TT, FF and SS process corners.
Detailed Description
The invention is further illustrated by the following figures and examples.
Referring to fig. 2-4, a reference voltage source includes: the circuit comprises a starting circuit, a first-order compensation circuit, a high-order compensation circuit for reducing the temperature coefficient of reference voltage (output voltage and Vref) and an ICTAT current generator circuit for reducing the power supply voltage regulation rate of the reference voltage, which are sequentially connected; the first-order compensation circuit comprises a third P-type field effect transistor MP3, a fourth P-type field effect transistor MP4, a fifth P-type field effect transistor MP5, a sixth P-type field effect transistor MP6, a seventh P-type field effect transistor MP7, an eighth P-type field effect transistor MP8, a ninth P-type field effect transistor MP9, a second N-type field effect transistor MN2, a third N-type field effect transistor MN3, a fourth N-type field effect transistor MN4, a resistor R1, a resistor R2 and a bipolar transistor Q1; the grid electrode of the third P-type field effect transistor MP3, the grid electrode of the fourth P-type field effect transistor MP4, the grid electrode and the drain electrode of the fifth P-type field effect transistor MP5 and the grid electrode of the sixth P-type field effect transistor MP6 are all connected with a high-order compensation circuit, the grid electrode of the third P-type field effect transistor MP3 is also connected with a starting circuit, the source electrode of the third P-type field effect transistor MP3, the source electrode of the fourth P-type field effect transistor MP4, the source electrode of the fifth P-type field effect transistor MP5 and the source electrode of the sixth P-type field effect transistor MP6 are all connected with an input voltage VDD, and the drain electrode of the fifth P-type field effect transistor MP5 is connected with the drain electrode of the second N-type field effect transistor; the source electrode of the second N-type field effect transistor MN2 is connected with the source electrode of the seventh P-type field effect transistor MP7, and the grid electrode of the second N-type field effect transistor MN2 is connected with the drain electrode of the third N-type field effect transistor MN3 and the drain electrode of the third P-type field effect transistor MP 3; the drain and the gate of the seventh P-type field effect transistor MP7 are both grounded; the source electrode of the third N-type field effect transistor MN3 is connected with the source electrode of the eighth P-type field effect transistor MP8, and the grid electrode of the third N-type field effect transistor MN3 is connected with the grid electrode of the fourth N-type field effect transistor MN4, the drain electrode of the fourth N-type field effect transistor MN4 and the drain electrode of the fourth P-type field effect transistor MP 4; the source electrode of the fourth N-type field effect transistor MN4 is connected with one end of a resistor R1; the other end of the resistor R1 is connected with the source electrode of the ninth P-type field effect transistor MP 9; the grid and the drain of the eighth P-type field effect transistor MP8 and the grid and the drain of the ninth P-type field effect transistor MP9 are both grounded; the drain electrode of the sixth P-type field effect transistor MP6 is connected with one end of the resistor R2; the other end of the resistor R2 is connected with the emitter of the bipolar transistor Q1, and the base and the collector of the bipolar transistor Q1 are both grounded.
In this embodiment, the start-up circuit includes: the first P-type field effect transistor MP1, the second P-type field effect transistor MP2 and the first N-type field effect transistor MN 1; the source electrode of the first P-type field effect transistor MP1 is connected with an input voltage VDD, the grid electrode of the first P-type field effect transistor MP1 is connected with the grid electrode of the third P-type field effect transistor MP3, the grid electrode of the fourth P-type field effect transistor MP4, the drain electrode of the fifth P-type field effect transistor MP5, the grid electrode of the fifth P-type field effect transistor MP5 and the grid electrode of the sixth P-type field effect transistor MP6, and the drain electrode of the first P-type field effect transistor MP1 is connected with the grid electrode of the second P-type field effect transistor MP2 and the grid electrode of the first N-type field effect transistor MN 1; the source and the drain of the first N-type fet MN1 are both connected to ground, and the drain of the second P-type fet MP2 is connected to the gate of the second N-type fet MN 2.
In this embodiment, the high-order compensation circuit includes: a tenth P-type fet MP10, an eleventh P-type fet MP11, a fifth N-type fet MN5, and a sixth N-type fet MN 6; the grid electrode of the tenth P-type field effect transistor MP10 is connected to the grid electrode of the sixth P-type field effect transistor MP6, the source electrode of the tenth P-type field effect transistor MP10 and the source electrode of the eleventh P-type field effect transistor MP11 are connected to the input voltage VDD, and the drain electrode of the tenth P-type field effect transistor MP10 is connected to the drain electrode of the fifth N-type field effect transistor MN5 and the drain electrode of the eleventh P-type field effect transistor MP 11; the grid electrode of the eleventh P-type field effect transistor MP11 is connected with an ICTAT current generator circuit; the drain electrode of the fifth N-type field effect transistor MN5 is also connected with the grid electrode of the fifth N-type field effect transistor MN5 and the grid electrode of the sixth N-type field effect transistor MN6, and the source electrode of the fifth N-type field effect transistor MN5 is grounded; the drain of the sixth N-type fet MN6 is connected to the drain of the sixth P-type fet MP6, and the source of the sixth N-type fet MN6 is grounded. As shown in FIG. 6, the working principle of the high-order compensation reference voltage provided by the embodiment of the invention is that the base-emitter voltage V of the bipolar transistorBEAnd a negative temperature coefficient voltage inversely proportional to the temperature is formed, a positive temperature coefficient voltage proportional to the temperature is formed by the voltage difference of the gate and the drain of the PMOS tube working in the subthreshold region by the eighth P-type field effect tube MP8 and the ninth P-type field effect tube MP9, and the negative temperature coefficient voltage and the positive temperature coefficient voltage are added to obtain a first-order reference voltage value Vref 1. Then, the curve Vcompensate with similar temperature characteristic with the first-order reference voltage is subtracted from Vref1 to obtain the output voltage Vref of the high-order curvature compensation reference, and the temperature characteristic curve of Vref is a sine function, soThe temperature coefficient of the reference voltage can be effectively reduced.
In this embodiment, the ICTAT current generator circuit includes: a twelfth P-type field effect transistor MP12, a thirteenth P-type field effect transistor MP13, a fourteenth P-type field effect transistor MP14, a seventh N-type field effect transistor MN7, an eighth N-type field effect transistor MN8 and a resistor R3; the grid electrode of the twelfth P-type field effect transistor MP12, the grid electrode of the thirteenth P-type field effect transistor MP13 and the grid electrode of the fourteenth P-type field effect transistor MP14 are connected with the grid electrode of the eleventh P-type field effect transistor MP11, the source electrode of the twelfth P-type field effect transistor MP12, the source electrode of the thirteenth P-type field effect transistor MP13 and the source electrode of the fourteenth P-type field effect transistor MP14 are connected with an input voltage VDD, and the drain electrode of the twelfth P-type field effect transistor MP12 is connected with the grid electrode of the seventh N-type field effect transistor MN7 and one end of a resistor R3; the other end of the resistor R3 is grounded; the drain electrode of the thirteenth P-type field effect transistor MP13 is connected with the drain electrode of the seventh N-type field effect transistor MN 7; the source electrode of the seventh N-type field effect transistor MN7 is grounded; the drain electrode of the fourteenth P-type field effect transistor MP14 is connected with the grid electrode of the fourteenth P-type field effect transistor MP14 and the drain electrode of the eighth N-type field effect transistor MN 8; the grid electrode of the eighth N-type field effect transistor MN8 is connected with the drain electrode of the seventh N-type field effect transistor MN 7; the source of the eighth N-type fet MN8 is grounded.
Referring to fig. 5, the method for operating a low reference voltage source suitable for the reference voltage source includes:
s1, when the power supply is electrified, the normal start of the circuit is started, and the reference voltage source enters a normal working state;
s2, a second N-type field effect tube MN2, a third N-type field effect tube MN3, a fourth N-type field effect tube MN4, a fourth P-type field effect tube MP4 and a fifth P-type field effect tube MP5 of the first-order compensation circuit form a negative feedback loop to maintain the voltages of preset nodes to be equal, a seventh P-type field effect tube MP7, an eighth P-type field effect tube MP8 and a ninth P-type field effect tube MP9 work in a subthreshold region, a current IPTAT with a positive temperature coefficient is generated through the pressure difference between PMOS tubes, and the current IPTAT is copied to the output end of a reference voltage source through a current mirror;
s3, the ICTAT current generator circuit generates a negative temperature coefficient current ICTAT which does not change along with the supply voltage.
S4, the high-order compensation circuit copies the current ICTAT to the output end of the reference voltage source, and the current combined with the current IPTAT forms high-order compensation voltage in the resistor R2 to compensate the first-order reference voltage.
In the present embodiment, step S1 includes: when the power supply is powered on, the grid electrode of the first N-type field effect transistor MN1 is at a low potential, the second P-type field effect transistor MP2 is conducted, the grid electrode of the second N-type field effect transistor MN2 becomes at a high level, the second N-type field effect transistor MN2 is conducted, current flows to the ground through the fifth P-type field effect transistor MP5, the second N-type field effect transistor MN2 and the seventh P-type field effect transistor MP7, the grid potential of the fifth P-type field effect transistor MP5 is pulled down, and the starting circuit starts to be started; meanwhile, the current charges the second P-type field effect transistor MP2 through the first P-type field effect transistor MP1, the grid potential of the second P-type field effect transistor MP2 gradually rises, when the grid potential is lower than the preset threshold voltage value of the power supply, the second P-type field effect transistor MP2 is turned off, the starting circuit is started, and the reference voltage source enters a normal working state.
In the present embodiment, step S2 includes:
the first-order compensation circuit adopts a seventh P-type field effect transistor MP7, an eighth P-type field effect transistor MP8 and a ninth P-type field effect transistor MP9 which work in a sub-threshold region to replace bipolar transistors in a traditional reference voltage source. When the CMOS tube works in the sub-threshold region and satisfies Vds≥4VTTime VdsIs the drain-source voltage, VTFor thermal voltage, source-drain current I of MOS transistordsThe relationship with temperature T is as follows:
wherein the mobility μ is μ T ═ μ0·T/T0 -m，CoxIs the gate oxide capacitance per unit area, η is the sub-threshold slope factor, W/L is the width-to-length ratio of MOS transistor, and the threshold voltage VTHIs a VTH＝VTHT0-k1T，VTHT0Is the threshold voltage at 0K, K1Is constant and is equal to about 2 mV/deg.C, and m is also constant and has a value between 1.5 and 2. Derived from equation (4):
as can be seen from equation (5), the MOS transistor operating in the sub-threshold region has similar temperature characteristics to the bipolar transistor, so that the first-order reference circuit can be designed by using the MOS transistor operating in the sub-threshold region instead of the bipolar transistor.
According to the invention, a negative feedback loop is formed by a second N-type field effect transistor MN2, a third N-type field effect transistor MN3, a fourth N-type field effect transistor MN4, a fourth P-type field effect transistor MP4 and a fifth P-type field effect transistor MP5 to stabilize the voltage values of two points of a node a and a node b, and the specific feedback process is that when the voltage of a point c of a first-order compensation circuit is increased due to some reason, the voltage of a node d is pulled down to increase the voltage of a node e, the voltage of a node c is decreased, and the voltage of the node c is stabilized;
setting the width-to-length ratios of the third N-type field effect transistor (MN3), the fourth N-type field effect transistor (MN4), the third P-type field effect transistor (MP3) and the fourth P-type field effect transistor (MP4) to be equal, so that the drain-source end currents of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4) are equal, and the voltage values of a node a and a node b are ensured to be equal; according to the first-order compensation circuit structure, the following relation is obtained:
VSG(MP8)+VGS(MN3)＝VSG(MP9)+I1R1+VSG(MN4)(1)
wherein, VSG(MP8)、VGS(MN3)、VSG(MP9)And VSG(MN4)Gate-source end voltages I of the eighth P-type FET MP8, the third N-type FET MN3, the ninth P-type FET MP9 and the fourth N-type FET MN4 respectively1Is the current flowing through R1. Because the width-to-length ratio of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4) and the drain-source end currents thereof are equal, the gate-source end voltages of the MN3 and the MN4 are equal. According to formula (1), obtaining a current I1Expression (c):
wherein, M ═ IMP8(W/L)MP9]/[IMP9(W/L)MP8]By setting the width-to-length ratio of the fourth P-type fet MP4 to the sixth P-type fet MP6 to be equal, the currents flowing through R1 and R2 are ensured to be equal, and the expression of the first-order reference voltage is obtained as follows:
VEBQ1the base-emitter voltage of the bipolar transistor Q1 is shown, wherein the seventh P-type field effect transistor MP7, the eighth P-type field effect transistor MP8 and the ninth P-type field effect transistor MP9 work in a subthreshold region, other MOS transistors work in a saturation region, and a first-order temperature compensation curve is obtained by setting the values of the resistors R1 and R2, and the temperature curve is a parabola with an upward opening.
All the MOS tubes in the high-order compensation circuit work in a saturation region, and the gate-source end voltage of the corresponding MOS tube can be expressed as:
wherein, Vthn7Is the threshold voltage, μ, of the MN7 tubenIs the mobility of electrons flowing through the resistor R3The current of (a) is:
substituting formula (6) for formula (7) yields:
by working up formula (8) to obtain a compound of formula IdsA quadratic equation of one unit of (c). Therefore, flows through the resistor R3The current of (a) is:
at the same time, a high-order curvature compensation current I5Satisfies the following conditions:
the current I in the formula (9)3In equation 10, the expression for obtaining the high-order curvature compensation current is:
wherein,
current I5Through a resistance R2Conversion to a higher order compensation voltage VcompThis voltage can be used to compensate a first order reference voltage Vref1. By reasonably setting parameters of the MOS tube, a high-order compensation output voltage reference value V can be obtainedref。
The current I in the formula (11)5The first derivative of the temperature T is obtained as follows:
wherein,
C＝[BηKLnM(W/L)MP10]/[R1(W/L)MP4]-Ak1/R3
E＝2R3Cox(W/L)MN7
where C, D and E are both constants, let equation (12) be zero on the left of the equal sign, and solving the equation on the right of the equal sign, we can obtain:
temperature value T1Is a second order compensation current I5For the second-order compensation current I, the variation trend of the second-order compensation current needs to be verified5And (3) solving a second derivative:
let the value to the left of the equal sign in equation (14) be greater than zero, which can be calculated as:
in the whole temperature range of normal operation, the value of the parameter E is reasonably set, so that the formula (15) can be satisfied. In this caseThe value of equation (14) remains positive, so the current I5The temperature change curve of (2) is opened upwards, and has the same change trend with the temperature of the first-order reference voltage, so that the first-order voltage reference can be compensated by the current.
High order compensation current I5At the resistance R2Generating a high-order compensation voltage, and comparing the high-order compensation voltage with a first-order reference voltage Vref1Subtracting to obtain an output expression of the reference voltage as follows:
Vref＝VEB1+(IPTAT-I5)R2(16)
substituting equations (2) and (11) into equation (16) yields an output voltage value of the voltage reference:
fig. 7-9 are schematic diagrams of output voltage versus temperature for three main process corners TT, FF, and SS provided by embodiments of the present invention. As shown in fig. 7 and 8, when the process angles are TT and FF, the output voltage shows a temperature characteristic with good uniformity, and the output curve is an ideal sinusoidal curve; as shown in fig. 9, when the process angle is SS, the pole position changes in the temperature curve of the output voltage, but the sinusoidal variation trend of the temperature does not change; when the process angle is TT, the lowest temperature coefficient value is 3.6 ppm/DEG C; when the process angle is FF, the temperature characteristic is the worst, and the temperature coefficient value is 7.4 ppm/DEG C and is lower than 10 ppm/DEG C. Under different process angles, due to process deviation, the reference output voltage V exists between every two process anglesrefIs 40mV, thus meeting the design requirements of process variation.
FIG. 10 is a simulation diagram of the linear adjustment rate of the output voltage varying with the power supply voltage according to the embodiment of the present invention, wherein when the power supply voltage reaches 1.7V, the reference voltage V is setrefA normal voltage value can be output; when the power supply voltage rises from 1.7V to 3.5V, the output voltage changes from 902.122mV902.112mV, 10 μ V of change amplitude, 5 μ V/V of linear regulation rate, and minimal influence of the change of the power supply voltage on the reference output voltage value.
Fig. 11 is a simulation diagram of the power supply rejection ratio PSRR of the output voltage under different power supply voltages according to the embodiment of the present invention, and the present invention analyzes and simulates four sets of data when the power supply voltages are 1.7V, 2.5V, 3V, and 3.5V, respectively, and the result shows that the power supply rejection ratio of the reference voltage gradually increases with the increase of the power supply voltage. As the system starting voltage is 1.7V, and the simulation result when the power supply voltage is 1.7V shows that the low-frequency PSRR value is-67.1 dB, and the power supply rejection ratio close to-50 dB is still obtained when the frequency is 1 MHz; when the power supply voltage rises to 3.5V, the power supply rejection ratio of the circuit approaches-90 dB. Therefore, the reference voltage source provided by the embodiment of the invention has good power supply inhibition performance, and can effectively inhibit the reference output voltage change caused by power supply voltage fluctuation.
FIG. 12 is a simulation diagram of the PSRR of power supply rejection ratio at TT, FF and SS process corners for output voltage when the power supply voltage is 2.5V, the result shows that the worst case of PSRR occurs at FF process corner, and the PSRR value is-79.7 dB at 1KHz frequency; the best situation occurs at the SS process corner, and the PSRR value is-81.6 dB at the frequency of 1 KHz; the PSRR value at the TT process angle is between the two. For different process angles, the PSRR value preferably differs from the worst case by only 1.9 dB. Therefore, the PSRR curve parameters show high consistency under different process angles, the average power supply rejection ratio is kept about-80 dB, and a good power supply rejection effect is achieved.
The above-mentioned embodiments are preferred embodiments of the present invention, and the present invention is not limited thereto, and any other modifications or equivalent substitutions that do not depart from the technical spirit of the present invention are included in the scope of the present invention.
Claims (7)
1. A reference voltage source, comprising: the circuit comprises a starting circuit, a first-order compensation circuit, a high-order compensation circuit for reducing the temperature coefficient of reference voltage and an ICTAT current generator circuit for reducing the power supply voltage regulation rate of the reference voltage, which are connected in sequence;
the first-order compensation circuit comprises a third P-type field effect transistor (MP3), a fourth P-type field effect transistor (MP4), a fifth P-type field effect transistor (MP5), a sixth P-type field effect transistor (MP6), a seventh P-type field effect transistor (MP7), an eighth P-type field effect transistor (MP8), a ninth P-type field effect transistor (MP9), a second N-type field effect transistor (MN2), a third N-type field effect transistor (MN3), a fourth N-type field effect transistor (MN4), a resistor R1, a resistor R2 and a bipolar transistor Q1;
the grid electrode of the third P-type field effect transistor (MP3), the grid electrode of the fourth P-type field effect transistor (MP4), the grid electrode and the drain electrode of the fifth P-type field effect transistor (MP5) and the grid electrode of the sixth P-type field effect transistor (MP6) are all connected with a high-order compensation circuit, the grid electrode of the third P-type field effect transistor (MP3) is also connected with a starting circuit, the source electrode of the third P-type field effect transistor (MP3), the source electrode of the fourth P-type field effect transistor (MP4), the source electrode of the fifth P-type field effect transistor (MP5) and the source electrode of the sixth P-type field effect transistor (MP6) are all connected with an input Voltage (VDD), and the drain electrode of the fifth P-type field effect transistor (MP5) is connected with the drain electrode of the second N-type field effect transistor (MN 2); the source electrode of the second N-type field effect transistor (MN2) is connected with the source electrode of the seventh P-type field effect transistor (MP7), and the grid electrode of the second N-type field effect transistor (MN2) is connected with the drain electrode of the third N-type field effect transistor (MN3) and the drain electrode of the third P-type field effect transistor (MP 3); the drain electrode and the grid electrode of the seventh P-type field effect transistor (MP7) are grounded; the source electrode of the third N-type field effect transistor (MN3) is connected with the source electrode of the eighth P-type field effect transistor (MP8), the grid electrode of the third N-type field effect transistor (MN3) is connected with the grid electrode of the fourth N-type field effect transistor (MN4), the drain electrode of the fourth N-type field effect transistor (MN4) and the drain electrode of the fourth P-type field effect transistor (MP 4); the source of the fourth N-type field effect transistor (MN4) is connected with one end of a resistor R1; the other end of the resistor R1 is connected with the source electrode of a ninth P-type field effect transistor (MP 9); the grid and the drain of the eighth P-type field effect transistor (MP8) and the grid and the drain of the ninth P-type field effect transistor (MP9) are both grounded; the drain electrode of the sixth P-type field effect transistor (MP6) is connected with one end of the resistor R2; the other end of the resistor R2 is connected with the emitter of the bipolar transistor Q1, and the base and the collector of the bipolar transistor Q1 are both grounded.
2. The reference voltage source of claim 1, wherein the start-up circuit comprises: a first P-type field effect transistor (MP1), a second P-type field effect transistor (MP2) and a first N-type field effect transistor (MN 1);
the source electrode of the first P-type field effect transistor (MP1) is connected with the input Voltage (VDD), the grid electrode of the first P-type field effect transistor (MP1) is connected with the grid electrode of the third P-type field effect transistor (MP3), the grid electrode of the fourth P-type field effect transistor (MP4), the drain electrode of the fifth P-type field effect transistor (MP5), the grid electrode of the fifth P-type field effect transistor (MP5) and the grid electrode of the sixth P-type field effect transistor (MP6), and the drain electrode of the first P-type field effect transistor (MP1) is connected with the grid electrode of the second P-type field effect transistor (MP2) and the grid electrode of the first N-type field effect transistor (MN 1); the source and the drain of the first N-type field effect transistor (MN1) are both connected to the ground, and the drain of the second P-type field effect transistor (MP2) is connected with the gate of the second N-type field effect transistor (MN 2).
3. The reference voltage source of claim 1, wherein the higher order compensation circuit comprises: a tenth P-type field effect transistor (MP10), an eleventh P-type field effect transistor (MP11), a fifth N-type field effect transistor (MN5), and a sixth N-type field effect transistor (MN 6);
the grid electrode of the tenth P-type field effect transistor (MP10) is connected with the grid electrode of the sixth P-type field effect transistor (MP6), the source electrode of the tenth P-type field effect transistor (MP10) and the source electrode of the eleventh P-type field effect transistor (MP11) are connected with the input Voltage (VDD), and the drain electrode of the tenth P-type field effect transistor (MP10) is connected with the drain electrode of the fifth N-type field effect transistor (MN5) and the drain electrode of the eleventh P-type field effect transistor (MP 11); the grid electrode of the eleventh P-type field effect transistor (MP11) is connected with the ICTAT current generator circuit; the drain electrode of the fifth N-type field effect transistor (MN5) is also connected with the gate electrode of the fifth N-type field effect transistor (MN5) and the gate electrode of the sixth N-type field effect transistor (MN6), and the source electrode of the fifth N-type field effect transistor (MN5) is grounded; the drain electrode of the sixth N-type field effect transistor (MN6) is connected with the drain electrode of the sixth P-type field effect transistor (MP6), and the source electrode of the sixth N-type field effect transistor (MN6) is grounded.
4. The reference voltage source of claim 1, wherein the ICTAT current generator circuit comprises: a twelfth P-type field effect transistor (MP12), a thirteenth P-type field effect transistor (MP13), a fourteenth P-type field effect transistor (MP14), a seventh N-type field effect transistor (MN7), an eighth N-type field effect transistor (MN8) and a resistor R3; the grid electrode of the twelfth P-type field effect transistor (MP12), the grid electrode of the thirteenth P-type field effect transistor (MP13) and the grid electrode of the fourteenth P-type field effect transistor (MP14) are connected with the grid electrode of the eleventh P-type field effect transistor (MP11), the source electrode of the twelfth P-type field effect transistor (MP12), the source electrode of the thirteenth P-type field effect transistor (MP13) and the source electrode of the fourteenth P-type field effect transistor (MP14) are connected with an input Voltage (VDD), and the drain electrode of the twelfth P-type field effect transistor (MP12) is connected with the grid electrode of the seventh N-type field effect transistor (MN7) and one end of the resistor R3; the other end of the resistor R3 is grounded; the drain electrode of the thirteenth P type field effect transistor (MP13) is connected with the drain electrode of the seventh N type field effect transistor (MN 7); the source electrode of the seventh N-type field effect transistor (MN7) is grounded; the drain electrode of the fourteenth P-type field effect transistor (MP14) is connected with the grid electrode of the fourteenth P-type field effect transistor (MP14) and the drain electrode of the eighth N-type field effect transistor (MN 8); the grid electrode of the eighth N-type field effect transistor (MN8) is connected with the drain electrode of the seventh N-type field effect transistor (MN 7); the source of the eighth N-type field effect transistor (MN8) is grounded.
5. A method of operating a reference voltage source, comprising:
s1, when the power supply is electrified, the normal start of the circuit is started, and the reference voltage source enters a normal working state;
s2, a second N-type field effect transistor (MN2), a third N-type field effect transistor (MN3), a fourth N-type field effect transistor (MN4), a fourth P-type field effect transistor (MP4) and a fifth P-type field effect transistor (MP5) of the first-order compensation circuit form a negative feedback loop to maintain the voltages of preset nodes to be equal, a seventh P-type field effect transistor (MP7), an eighth P-type field effect transistor (MP8) and a ninth P-type field effect transistor (MP9) work in a subthreshold region, a current IPTAT with a positive temperature coefficient is generated through the pressure difference between the PMOS transistors, and the current IPTAT is copied to the output end of a reference voltage source through a current mirror;
s3, generating a negative temperature coefficient current ICTAT which does not change along with the supply voltage by an ICTAT current generator circuit;
s4, the high-order compensation circuit copies the current ICTAT to the output end of the reference voltage source, and the current combined with the current IPTAT forms high-order compensation voltage in the resistor R2 to compensate the first-order reference voltage.
6. The operating method of a reference voltage source according to claim 5, wherein step S1 includes:
when the power supply is powered on, the grid electrode of the first N-type field effect transistor (MN1) is at a low potential, the second P-type field effect transistor (MP2) is conducted, the grid electrode of the second N-type field effect transistor (MN2) becomes a high level, the second N-type field effect transistor (MN2) is conducted, the current flows through the fifth P-type field effect transistor (MP5), the second N-type field effect transistor (MN2) and the seventh P-type field effect transistor (MP7) to the ground, the grid potential of the fifth P-type field effect transistor (MP5) is pulled down, and the starting circuit starts to start;
the current charges the second P-type field effect transistor (MP2) through the first P-type field effect transistor (MP1), the grid potential of the second P-type field effect transistor (MP2) is gradually increased, when the grid potential is increased to be lower than the power supply by a preset threshold voltage value, the second P-type field effect transistor (MP2) is turned off, the starting circuit is started, and the reference voltage source enters a normal working state.
7. The method of claim 5, wherein step S2 includes:
when the voltage of the point c of the first-order compensation circuit is increased for some reason, the voltage of the node d is pulled down, the voltage of the node e is increased, the voltage of the node c is decreased, and the voltage of the node c is stabilized;
setting the width-to-length ratios of the third N-type field effect transistor (MN3), the fourth N-type field effect transistor (MN4), the third P-type field effect transistor (MP3) and the fourth P-type field effect transistor (MP4) to be equal, so that the drain-source end currents of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4) are equal, and the voltage values of a node a and a node b are ensured to be equal; according to the first-order compensation circuit structure, the following relation is obtained:
VSG(MP8)+VGS(MN3)＝VSG(MP9)+I1R1+VSG(MN4)(1)
wherein, VSG(MP8)、VGS(MN3)、VSG(MP9)And VSG(MN4)The gate-source end voltages of the eighth P-type field effect transistor (MP8), the third N-type field effect transistor (MN3), the ninth P-type field effect transistor (MP9) and the fourth N-type field effect transistor (MN4), I1Is the current flowing through R1; because of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4)The width-to-length ratio and the drain-source end currents are equal, so that the grid end-source end voltages of the third N-type field effect transistor (MN3) and the fourth N-type field effect transistor (MN4) are equal; according to formula (1), obtaining a current I1Expression (c):
wherein, M ═ IMP8(W/L)MP9]/[IMP9(W/L)MP8]By setting the width-to-length ratio of the fourth P-type field effect transistor (MP4) to the sixth P-type field effect transistor (MP6) to be equal, the currents flowing through R1 and R2 are ensured to be equal, and the expression of the first-order reference voltage is obtained as follows:
VEB(Q1)the base-emitter voltage of the bipolar transistor Q1 is obtained, wherein the seventh P-type field effect transistor (MP7), the eighth P-type field effect transistor (MP8) and the ninth P-type field effect transistor (MP9) work in a subthreshold region, other MOS transistors work in a saturation region, and a first-order temperature compensation curve is obtained by setting the values of the resistors R1 and R2.
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