CN111966159A - Low-voltage and low-power-consumption reference circuit and calibration method thereof - Google Patents
Low-voltage and low-power-consumption reference circuit and calibration method thereof Download PDFInfo
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- CN111966159A CN111966159A CN202010890384.4A CN202010890384A CN111966159A CN 111966159 A CN111966159 A CN 111966159A CN 202010890384 A CN202010890384 A CN 202010890384A CN 111966159 A CN111966159 A CN 111966159A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention discloses a low-voltage and low-power-consumption reference circuit and a calibration method thereof, belonging to the technical field of reference circuits, comprising a PTAT generating circuit connected with VCC, a PTAT generating circuit connected with MP2, one end of MP2 connected with VCC, the other end connected with VREF, a resistor R2 and a resistor R3 in parallel, a resistor R2 connected with the base and collector of a grounded BJT transistor Q1, and a resistor R3 grounded, wherein the structure can output a zero-temperature coefficient reference voltage smaller than 1V, and can work at a lower power supply voltage, the lowest working power supply voltage can be close to a Vbe and about 0.6V, so that the limitation of the zero-temperature reference voltage to the lowest working power supply voltage is eliminated, and a calibration method and a corresponding flow for the temperature coefficient and the voltage absolute value of the output voltage are provided.
Description
Technical Field
The invention relates to the technical field of reference circuits, in particular to a low-voltage and low-power-consumption reference circuit and a calibration method thereof.
Background
The reference voltage and current, which are modules essential to almost all chips, are critical to their function. The circuit always operates based on some reference (voltage reference, i.e. reference voltage; current reference, i.e. reference current; clock reference, usually a crystal oscillator). In some battery-powered devices, low power consumption, small area, and as low an operating voltage as possible are always desired, and therefore high demands are placed on the design of each module. The particularity of the reference voltage and reference current generating module is generally designed to work when being powered on and cannot be turned off, so that the requirements on low power consumption and low voltage are more strict. In the design of these low power consumption chips, a reference circuit implemented by using MOS transistors operating in a sub-threshold region is widely used.
As shown in fig. 1 and 2, as shown in fig. 1. In the prior art, a low-power reference circuit implemented based on a sub-threshold region MOS transistor generally generates a current proportional to absolute temperature, which is called a PTAT current, and then copies the PTAT current and flows through a resistor R2 and a BJT Q1 connected in series to generate a zero temperature coefficient reference voltage VREF.
The principle of generating VREF can be explained by the following equation:
where N is the scaling factor (usually 4) of the NMOS current mirror (not shown) in the circuit, assuming that MP1 and MP2 are mirrored at a ratio of 1: 1.
In this expression, the first term Vbe, which is the Vbe voltage of the BJT transistor, can be written as:
Vbe＝Vg0-αT
where Vg0 is referred to as the forbidden band voltage, is a physical constant associated with silicon materials, approximately 1.2V, independent of PVT. α is the temperature coefficient of Vbe, which is approximately-2 mV/deg.C.
Second item
Is a positive temperature coefficient term, proportional to absolute temperature, called PTAT term. By adjusting the ratio
The size of the positive temperature coefficient can be adjusted; in particular when
The positive temperature coefficient of the second term is approximately +2 mV/deg.C, just canceling the negative temperature coefficient of Vbe. After temperature compensation, the expression of VREF is:
VREF＝Vg0-αT+αT≈1.2V
if a zero temperature coefficient reference voltage is generated, the reference voltage must be around 1.2V, otherwise it is not a zero temperature coefficient. If the reference output is 1.2V, the minimum supply voltage is increased by at least one overdrive voltage Vod (about 0.2V), i.e. 1.4V, of the PMOS transistor. The existing architecture is certainly not feasible if we want to achieve a minimum operating supply voltage below 1V, while at the same time want to be able to output an arbitrary zero temperature coefficient reference voltage of less than 1V.
Disclosure of Invention
The invention aims to provide a low-voltage and low-power-consumption reference circuit and a calibration method thereof, which eliminate the limitation of the lowest working power supply voltage by zero-temperature reference voltage, can output zero-temperature coefficient reference voltage smaller than 1V, can work at lower power supply voltage, and simultaneously output a calibration method and a corresponding flow of the temperature coefficient and the voltage absolute value of the voltage so as to solve the problems in the background technology.
In order to achieve the purpose, the invention provides the following technical scheme: a low-voltage and low-power consumption reference circuit comprises a PTAT generating circuit connected with VCC, a MP2, a MP2 with one end connected with VCC and the other end connected with VREF, a resistor R2 and a resistor R3 in parallel, a resistor R2 connected with the base and collector of a BJT Q1 which is grounded, and a resistor R3 grounded.
Further, the PTAT generation circuit includes a resistor R1 and a current mirror, and the following equation is applied to the output node column current conservation:
solving to obtain:
VREF expression is multiplied by a resistance voltage division ratio
Thus, it is possible to achieve arbitrary scaling of the voltage, by design, by selection
The ratio, the expression in brackets is designed as zero temperature coefficient, which is about 1.2V according to the previous theory; if the 0.8V reference needs to be output, the reference can be taken
R3 is 2R2, and a plurality of reference voltages can be output by selecting different taps using R3 resistors.
The other technology provided by the invention comprises a calibration method of a low-voltage and low-power consumption reference circuit, which comprises the following steps:
s1: randomly selecting 20 chips in the same batch, numbering and testing;
s2: selecting a 1 st chip and placing the chip into a high-low temperature box for testing;
s3: the temperature is gradually increased from minus 40 ℃ to plus 85 ℃, each 5 ℃ is a temperature point, the value of traversing R2 is set as R2_ SEL [ N:0] at each temperature point, the corresponding VREF voltage value is recorded, the final data forms a large table, the column coordinate is the temperature point, the row coordinate is the value of R2_ SEL, and the intersection point of the row/column coordinate is the VREF test value;
s4: drawing the data table to form a cluster of VREF curves relative to the temperature T, wherein the reference variable is the value of R2_ SEL, the curve with the temperature coefficient being the minimum and close to 0 is found out, and the corresponding value of R2_ SEL is recorded;
s5: repeating the steps S3 and S4, measuring 20 chips, and recording the R2_ SEL value of each chip, wherein theoretically, the dispersion of the R2_ SEL values should be small and is presented as a fixed deviation amount;
s6: for the R2_ SEL values of the 20 chips, an average R2_ SEL value is obtained by a method of removing the maximum value, removing the minimum value and averaging the intermediate value, and the average R2_ SEL value is used as a uniform R2_ SEL configuration value of the chip and is fixed;
s7: the determination of the value of R2_ SEL is completed, denoted as R2_ SEL _ OPT, followed by the determination of the value of R3_ SEL;
s8: for the 20 chips, uniformly configuring R2_ SEL as R2_ SEL _ OPT, then traversing the value of R3 to set as R3_ SEL [ M:0] according to a dichotomy mode for each chip, and adjusting the VREF value to an expected value, wherein in principle, the temperature coefficient cannot be influenced in the process of adjusting R3;
s9: after the calibration is finished, the R3_ SEL of each chip may be different, and the R3_ SEL calibration value of each chip is stored in the NVM nonvolatile memory of the chip;
s10: to this end, the determination of the R3_ SEL value is completed;
s11: an optional link: the 20 chips are written with the configuration values of R2_ SEL and R3_ SEL which are calibrated according to the previous process, high and low temperature experiments are repeated, the temperature is gradually increased to +85 ℃ from-40 ℃, each 5 ℃ is a temperature point, corresponding VREF voltage values are recorded, whether the VREF curves relative to the temperature T are all close to zero temperature coefficients or not is checked, and the central value is an expected value.
Compared with the prior art, the invention has the beneficial effects that: the invention provides a low-voltage and low-power-consumption reference circuit and a calibration method thereof, the structure can output zero-temperature coefficient reference voltage less than 1V, meanwhile, the structure can work under lower power supply voltage, the lowest zero-temperature coefficient reference voltage can be close to Vbe and about 0.6V, the limitation that the lowest working power supply voltage is limited by the zero-temperature reference voltage is eliminated, the structure can output the zero-temperature coefficient reference voltage less than 1V, and the structure can work under the lower power supply voltage, and simultaneously output the calibration method and the corresponding flow of the temperature coefficient and the voltage absolute value of the voltage.
Drawings
FIG. 1 is a prior art reference voltage with zero temperature coefficient generated by a PTAT current;
FIG. 2 is a schematic of a prior art PTAT current generating a zero temperature coefficient reference voltage;
FIG. 3 is a low voltage low power reference circuit configuration of the present invention;
FIG. 4 illustrates a method of outputting one or more lower reference voltages in accordance with the present invention;
FIG. 5 is a detailed block diagram of a first embodiment of the present invention;
FIG. 6 is a block diagram of a second embodiment of the present invention;
FIG. 7 is a graph of VREF according to the present invention over temperature T;
fig. 8 is a detailed structural diagram of the second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
referring to fig. 3, a low voltage and low power consumption reference circuit includes a PTAT generating circuit connected to VCC, a PTAT generating circuit connected to MP2, a MP2 having one end connected to VCC and the other end connected in parallel to VREF, a resistor R2 and a resistor R3, a resistor R2 connected to the drain and gate of a BJT Q1, and a resistor R3 connected to ground.
Referring to fig. 4, the PTAT generation circuit includes a resistor R1 and a current mirror, and the conservation equation for the output node column current is:
solving to obtain:
VREF expression is multiplied by a resistance voltage division ratio
Thus enabling arbitrary scaling of the voltage. In design, by selection
The ratio, the expression in brackets is designed as zero temperature coefficient, which is about 1.2V according to the previous theory; if the 0.8V reference needs to be output, the reference can be taken
If a lower reference voltage or a plurality of reference voltages are to be output, the R3 is 2R2, and only voltages need to be taken from different taps of the R3 resistor. For example, as shown in fig. 4, if R3 is split into 3 resistors of R3/3 resistance value connected in series and tap voltages V1 and V2 are taken out from the middle, V1 is 1/3VREF and V2 is 2/3 VREF; if VREF is 0.9V, V1 is 0.3V, and V2 is 0.6V. Any other voltage may be generated by appropriate division of R3.
Referring to fig. 5, a low voltage, low power consumption reference voltage generation circuit is provided by adding R3.
MN0 and MN1 are NMOS current mirrors with a typical ratio of 4:1, and need to be designed to operate in the subthreshold region (W/L is large enough, e.g., MN0 is 20u/1u, MN1 is 20u/1u x4, and the current is 500 nA).
The lowest working power voltage of the PTAT current generation part is extremely low, and the PTAT current generation part can normally work (about 0.6V) just under the threshold voltage of one MOS tube, so the PTAT current generation part is not a bottleneck. The lowest operating supply voltage is limited to the output, i.e., the generating branch of VREF. If VREF is 0.8V and Vod of MP2 is 0.2V, the lowest operating power voltage is 0.8+0.2 is 1.0V, which is greatly reduced compared to the prior art.
Referring to fig. 7, generally, the deviation of the temperature coefficient is mainly caused by fixed factors such as Model misalignment, chip stress, material characteristics, etc., and is not greatly affected by process deviation and device mismatch. Therefore, the deviation of the temperature coefficient usually appears as one integral deviation, and the dispersion is small. This means that if the correct temperature coefficient can be found, this temperature coefficient can be approximated for all chips (at least for this batch of chips)
In order to better show the calibration method of the low-voltage and low-power consumption reference circuit, the calibration method comprises the following steps:
the method comprises the following steps: randomly selecting 20 chips in the same batch, numbering and testing;
step two: selecting a 1 st chip and placing the chip into a high-low temperature box for testing;
step three: the temperature is gradually increased from minus 40 ℃ to plus 85 ℃, each 5 ℃ is a temperature point, the value of traversing R2 is set as R2_ SEL [ N:0] at each temperature point, the corresponding VREF voltage value is recorded, the final data forms a large table, the column coordinate is the temperature point, the row coordinate is the value of R2_ SEL, and the intersection point of the row/column coordinate is the VREF test value;
step four: drawing the data table to form a cluster of VREF curves relative to the temperature T, wherein the reference variable is the value of R2_ SEL, the curve with the temperature coefficient being the minimum and close to 0 is found out, and the corresponding value of R2_ SEL is recorded;
step five: repeating the steps S3 and S4, measuring 20 chips, and recording the R2_ SEL value of each chip, wherein theoretically, the dispersion of the R2_ SEL values should be small and is presented as a fixed deviation amount;
step six: for the R2_ SEL values of the 20 chips, an average R2_ SEL value is obtained by a method of removing the maximum value, removing the minimum value and averaging the intermediate value, and the average R2_ SEL value is used as a uniform R2_ SEL configuration value of the chip and is fixed;
step seven: the determination of the value of R2_ SEL is completed, denoted as R2_ SEL _ OPT, followed by the determination of the value of R3_ SEL;
step eight: for the 20 chips, uniformly configuring R2_ SEL as R2_ SEL _ OPT, then traversing the value of R3 to set as R3_ SEL [ M:0] according to a dichotomy mode for each chip, and adjusting the VREF value to an expected value, wherein in principle, the temperature coefficient cannot be influenced in the process of adjusting R3;
step ten: after the calibration is finished, the R3_ SEL of each chip may be different, and the R3_ SEL calibration value of each chip is stored in the NVM nonvolatile memory of the chip;
step eleven: to this end, the determination of the R3_ SEL value is completed;
step twelve: an optional link: the 20 chips are written with the configuration values of R2_ SEL and R3_ SEL which are calibrated according to the previous process, high and low temperature experiments are repeated, the temperature is gradually increased to +85 ℃ from-40 ℃, each 5 ℃ is a temperature point, corresponding VREF voltage values are recorded, whether the VREF curves relative to the temperature T are all close to zero temperature coefficients or not is checked, and the central value is an expected value.
In the actual mass production link, the R2_ SEL does not need to be calibrated at high and low temperatures, and the value of R2_ SEL _ OPT may be used in a unified manner. Only a binary calibration of R3_ SEL is required. Because the link of heating up/cooling down is not involved, the calibration of R3_ SEL can be carried out very fast, can cooperate the board to accomplish automatic calibration.
Example two:
the reference voltage generating circuit is a low-voltage and low-power consumption reference voltage generating circuit which adopts the novel technology provided by the invention and adds the adjustable resistor R3.
Referring to FIG. 8, MN0 and MN1 are NMOS current mirrors with a typical ratio of 4:1, designed to operate in the subthreshold region (W/L is large enough, e.g., MN0 is 20u/1u, MN1 is 20u/1u x4, current is 500 nA).
The lowest working power voltage of the PTAT current generation part is extremely low, and the PTAT current generation part can normally work (about 0.6V) just under the threshold voltage of one MOS tube, so the PTAT current generation part is not a bottleneck. The lowest operating supply voltage is limited to the output, i.e., the generating branch of VREF. If VREF is 0.8V and Vod of MP2 is 0.2V, the lowest operating power voltage is 0.8+0.2 is 1.0V, which is greatly reduced compared to the prior art.
Wherein R2 and R3 have a digital programming interface. By adopting the calibration method provided by the invention, the output reference voltage can be calibrated to be any voltage with zero temperature coefficient and an absolute value of a preset value which is less than 1.2V.
In summary, the following steps: the invention relates to a low-voltage and low-power consumption reference circuit and a calibration method thereof, wherein the structure can output a zero temperature coefficient reference voltage smaller than 1V, can work at a lower power supply voltage, can be at least close to a Vbe and is about 0.6V, the limitation of the minimum working power supply voltage by the zero temperature reference voltage is eliminated, the structure can output the zero temperature coefficient reference voltage smaller than 1V, and can work at the lower power supply voltage, and the calibration method and the corresponding flow of the temperature coefficient and the voltage absolute value of the voltage are output simultaneously.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be able to cover the technical solutions and the inventive concepts of the present invention within the technical scope of the present invention.
Claims (3)
1. A low-voltage and low-power consumption reference circuit is characterized by comprising a PTAT generating circuit connected with VCC, a MP2, an MP2 with one end connected with VCC and the other end connected with VREF, a resistor R2 and a resistor R3 in parallel, a resistor R2 connected with the base and collector of a BJT Q1 which is grounded, and a resistor R3 grounded.
2. A low voltage, low power consumption reference circuit as claimed in claim 1 wherein the PTAT generation circuit comprises a resistor R1 and a current mirror, the conservation of current equation for the output node column current:
solving to obtain:
VREF expression is multiplied by a resistance voltage division ratio
Thus, it is possible to achieve arbitrary scaling of the voltage, by design, by selection
The ratio is that the expression in brackets is designed to be zero temperature coefficient, and according to the theory of reference voltage, the temperature coefficient is about 1.2V; if the 0.8V reference needs to be output, the reference can be taken
R3 is 2R2, and a plurality of reference voltages can be output by selecting different taps using R3 resistors.
3. A method of calibrating a low voltage, low power consumption reference circuit according to claim 1, comprising the steps of:
s1: randomly selecting 20 chips in the same batch, numbering and testing;
s2: selecting a 1 st chip and placing the chip into a high-low temperature box for testing;
s3: the temperature is gradually increased from minus 40 ℃ to plus 85 ℃, each 5 ℃ is a temperature point, the value of traversing R2 is set as R2_ SEL [ N:0] at each temperature point, the corresponding VREF voltage value is recorded, the final data forms a large table, the column coordinate is the temperature point, the row coordinate is the value of R2_ SEL, and the intersection point of the row/column coordinate is the VREF test value;
s4: drawing the data table to form a cluster of VREF curves relative to the temperature T, wherein the reference variable is the value of R2_ SEL, the curve with the temperature coefficient being the minimum and close to 0 is found out, and the corresponding value of R2_ SEL is recorded;
s5: repeating the steps S3 and S4, measuring 20 chips, and recording the R2_ SEL value of each chip, wherein theoretically, the dispersion of the R2_ SEL values should be small and is presented as a fixed deviation amount;
s6: for the R2_ SEL values of the 20 chips, an average R2_ SEL value is obtained by a method of removing the maximum value, removing the minimum value and averaging the intermediate value, and the average R2_ SEL value is used as a uniform R2_ SEL configuration value of the chip and is fixed;
s7: the determination of the value of R2_ SEL is completed, denoted as R2_ SEL _ OPT, followed by the determination of the value of R3_ SEL;
s8: for the 20 chips, uniformly configuring R2_ SEL as R2_ SEL _ OPT, then traversing the value of R3 to set as R3_ SEL [ M:0] according to a dichotomy mode for each chip, and adjusting the VREF value to an expected value, wherein in principle, the temperature coefficient cannot be influenced in the process of adjusting R3;
s9: after the calibration is finished, the R3_ SEL of each chip may be different, and the R3_ SEL calibration value of each chip is stored in the NVM nonvolatile memory of the chip;
s10: to this end, the determination of the R3_ SEL value is completed;
s11: an optional link: the 20 chips are written with the configuration values of R2_ SEL and R3_ SEL which are calibrated according to the previous process, high and low temperature experiments are repeated, the temperature is gradually increased to +85 ℃ from-40 ℃, each 5 ℃ is a temperature point, corresponding VREF voltage values are recorded, whether the VREF curves relative to the temperature T are all close to zero temperature coefficients or not is checked, and the central value is an expected value.
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