EP3721314B1

EP3721314B1 - Programmable temperature coefficient analog second-order curvature compensated voltage reference and trim techniques for voltage reference circuits

Info

Publication number: EP3721314B1
Application number: EP18829584.4A
Authority: EP
Inventors: Umanath R. KAMATH; John K. Jennings; Edward Cullen; Ionut C. CICAL; Darragh WALSH
Original assignee: Xilinx Inc
Current assignee: Xilinx Inc
Priority date: 2017-12-05
Filing date: 2018-12-04
Publication date: 2022-01-26
Anticipated expiration: 2038-12-04
Also published as: EP3721314A1; CN111448531B; KR20200096586A; JP7281464B2; CN111448531A; WO2019113111A1; KR102600881B1; JP2021506006A

Description

TECHNICAL FIELD

Examples of the present disclosure generally relate to electronic circuits and, in particular, to a programmable temperature coefficient analog second-order curvature compensated voltage reference and to trim techniques for voltage reference circuits.

BACKGROUND

Precision voltage references are important blocks in integrated circuits (ICs), such as System-on-Chip (SoC) ICs. Voltage references are required for various purposes, such as for analog-to-digital converters (ADCs), power management, and the like. Generation of a voltage that is dependent on temperature is also useful in some applications, such as to compensate for temperature effects on circuits. Thus, different circuits in an IC require voltage references having different temperature coefficients (e.g., an ADC uses a temperature-independent voltage reference whereas other circuits, such as switches, require a temperature-dependent voltage reference). Further, circuits for generating voltage references typically use bipolar junction transistors (BJTs). BJTs, however, are parasitic devices in the complementary metal oxide semiconductor (CMOS) process used to fabricate ICs. BJT performance degrades as the CMOS technology scales, which is driven by digital logic. Accordingly, it is desirable to provide a voltage reference circuit that can generate flexible temperature coefficient voltages while compensating for second-order curvature introduced by BJTs.
US 2006/111865 A1 describes an on-chip temperature sensor for a semiconductor device. The sensor arrangement includes a first current generator producing a first current that is proportional to absolute temperature of the semiconductor device and a second current generator producing a second current that is inversely proportional to absolute temperature of the semiconductor device.
US 6 265 857 B1 discloses a constant current source circuit which provides current that compensates for changes in performance resulting from changes of temperature. Within the circuit, variable amounts of current having a negative temperature coefficient are mixed with variable amounts of current having a positive temperature coefficient.
In US 2010/301832 A1 systems and methods for generating a curvature-compensated bandgap voltage reference are described. A curvature-compensated bandgap reference voltage is achieved by injecting a temperature-dependent current at different points in a bandgap reference voltage circuit.

SUMMARY

Techniques for providing a programmable temperature coefficient analog second-order curvature compensated voltage reference are described. This is performed by providing a voltage reference circuit according to claim 1 and a method of generating a voltage reference according to claim 9. Other aspects of the invention are defined in the dependent claims.
These and other aspects may be understood with reference to the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope.

Fig. 1 is a block diagram depicting an integrated circuit (IC) according to an example.
Fig. 2 is a block diagram depicting a voltage reference circuit according to an example.
Fig. 3 is a schematic diagram depicting a reference circuit according to an example.
Fig. 4 is a schematic diagram depicting a resistor ladder according to example.
Fig. 5A is a schematic diagram depicting a zero temperature coefficient (Tempco) circuit according to an example.
Fig. 5B is a schematic diagram depicting a curvature correction circuit according to an example.
Fig. 5C is a schematic diagram depicting another portion of the zero Tempco circuit of Fig. 5A according to an example.
Fig. 6 is a graph illustrating the dependence of reference voltage on temperature.
Fig. 7 is a schematic diagram depicting a negative Tempco circuit according to an example.
Fig. 8 is a schematic diagram depicting a positive Tempco circuit according to an example.
Fig. 9 is a flow diagram depicting a method of generating a voltage reference according to an example.
Fig. 10 is a block diagram depicting a test system according to an example.
Fig. 11 is a flow diagram depicting a method of setting trim codes in a voltage reference circuit according to an example.
Fig. 12A is a graph 800 depicting flat trim codes versus output voltage at different temperatures according to an example.
Fig. 12B is a graph 801 depicting ref trim codes versus output voltage at a particular temperature according to an example.
Fig. 13 is a flow diagram depicting a method of setting trim codes in a voltage reference circuit according to another example.
Fig. 14A is a graph depicting measurements of a reference trim code at two different temperatures according to an example.
Fig. 14B is a graph depicting a lookup of the flat trim code according to an example.
Fig. 15 is a block diagram depicting a programmable IC in which the voltage reference circuit described herein can be used according to an example.
Fig. 16 illustrates a field programmable gate array (FPGA) implementation of the programmable IC of Fig. 15.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.

DETAILED DESCRIPTION

Various features are described hereinafter with reference to the figures. It should be noted that the figures may or may not be drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the features. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. In addition, an illustrated example need not have all the aspects or advantages shown.
Fig. 1 is a block diagram depicting an integrated circuit (IC) 100 according to an example. The IC 100 includes a voltage reference circuit 200, a control circuit 114, and circuits 102. The voltage reference circuit 200 is coupled between a supply node 110, which supplies a voltage Vcc, and a ground node 112, which supplies a ground voltage (e.g., 0 volts). The voltage Vcc may be provided by a voltage supply (not shown) either within the IC 100 or external to the IC 100. The voltage reference circuit 200 is coupled to one or more of the circuits 102 by one or more nodes 104, each of which supplies a zero temperature coefficient (Tempco) voltage. The voltage reference circuit 200 is coupled to one or more of the circuits 102 by one or more nodes 106, each of which supplies a negative Tempco voltage. The voltage reference circuit 200 is coupled to one or more of the circuits 102 by one or more nodes 108, each of which supplies a positive Tempco voltage. Thus, the voltage reference circuit 200 generates zero Tempco voltage(s), negative Tempco voltage(s), and positive Tempco voltage(s). The control circuit 114 supplies control signals to the voltage reference circuit 200 for trimming voltages and/or currents as described in detail below.
Fig. 2 is a block diagram depicting the voltage reference circuit 200 according to an example. The voltage reference circuit 200 includes a reference circuit 202, a zero Tempco circuit 204, a negative Tempco circuit 206, and a positive Tempco circuit 208. A node 210 couples one output of the reference circuit 202 to each of the Tempco circuits 204...208. A node 212 couples another output of the reference circuit 202 to each of the Tempco circuits 204...208. The nodes 210 and 212 supply control voltages to the Tempco circuits 204...208. The reference circuit 202 generates a proportional-to-temperature current (referred to as Iptat) and a complementary-to-temperature current (referred to as Ictat), as described further below. The control voltages on the nodes 210 and 212 control current sources in the Tempco circuits 204...208 to mirror the currents Iptat and Ictat, respectively. The zero Tempco circuit 204 converts a zero Tempco current Iztat (Iztat = Iptat + Ictat) into one or more zero Tempco voltages at the nodes 104. The negative Tempco circuit 206 converts the current Iztat into one or more negative Tempco voltages at the nodes 106. The positive Tempco circuit 208 converts the current Iztat into one or more positive Tempco voltages at the nodes 108.
Fig. 3 is a schematic diagram depicting the reference circuit 202 according to an example. The reference circuit 202 includes p-channel field effect transistors (FETs) 302, 304, and 306, such as p-type metal oxide semiconductor FETs (MOSFETs). A p-channel FET is a FET that uses holes as the majority carrier to carry its channel current. The reference circuit 202 further includes an operational amplifier 308, an operational amplifier 316, a multiplexer 320, a resistor 310, a resistor ladder 318, a bipolar junction transistor (BJT) 312, and a BJT 314. The BJTs 312 and 314 are PNP transistors.
A source of the FET 302 is coupled to the node 110 that supplies Vcc. A drain of the FET 302 is coupled to a node 324. A gate of the FET 302 is coupled to the node 210 that supplies a control voltage V_P. A source of the FET 304 is coupled to the node 110. A drain of the FET 304 is coupled to a node 326. A gate of the FET 304 is coupled to the node 210. A source of the FET 306 is coupled to the node 110. A gate of the FET 306 is coupled to the node 212 that supplies a control voltage Vc. A drain of the FET 306 is coupled to a node 330. The resistor ladder 318, having a total resistance R2, is coupled between the node 330 and the ground node 112.
Fig. 4 is a schematic diagram depicting a resistor ladder 400 according to example. The resistor ladder 400 can be used as the resistor ladder 318 or any other resistor ladder described herein. The resistor ladder 400 includes a resistor string 408, e.g., resistors 408₁...408_K, where K is an integer greater than one. The resistors 408₁...408_K are coupled in series between a node 410 and a node 412. The resistor ladder 400 further includes a multiplexer 402. Inputs of the multiplexer 402 are respectively coupled to a plurality of taps, e.g., taps 404₁...404_J, where J is an integer greater than one. Each tap 404₁...404_J is coupled to a respective node of the resistor string 408, where the resistor string 408 includes one or more resistors between each pair of nodes. The multiplexer 402 includes a control input 414 for receiving a signal Ctrl that selects one of the taps 404. The signal Ctrl is a digital signal having ceiling[log₂(J)] bits. The multiplexer 402 includes an output coupled to a node 406. The resistor ladder 400 provides an effective resistance R between the node 406 and the node 412 (shown in phantom for purposes of illustration), which depends on the code value of the Ctrl signal.
Returning to Fig. 3, a node 328 is coupled to a selected tap of the resistor ladder 318 based on the value of a Flat Trim code. This effectively splits the resistor ladder 318 into a resistance 318₁ between the node 330 and the node 328, and a resistance 318₂ between the node 328 and the ground node 112. The resistance 318₁ has a value R2', and the resistance 318₂ has a value R2".
An inverting input of the operational amplifier 308 is coupled to the node 324. A non-inverting input of the operational amplifier 308 is coupled to the node 326. An output of the operational amplifier 308 is coupled to the node 210. An inverting input of the operational amplifier 316 is coupled to the node 324. A non-inverting input of the operational amplifier 316 is coupled to a node 328. An output of the operational amplifier 316 is coupled to the node 212.
The resistor 310, having a resistance R1, is coupled between the node 326 and an emitter of the BJT 314. Each of a base and a collector of the BJT 314 is coupled to the ground node 112. Thus, the BJT 314 is a diode-connected BJT having an anode coupled to the resistor 310 and a cathode coupled to the ground node 112. An emitter of the BJT 312 is coupled to the node 324. Each of a base and a collector of the BJT 312 is coupled to the ground node 112. Thus, the BJT 312 is a diode-connected BJT having an anode coupled to the node 324 and a cathode coupled to the ground node 112. The BJT 314 has N times the emitter area as the BJT 312, where N is an integer greater than one.
In operation, the operational amplifier 308 is self-biasing and sets the control voltage V_P to turn on the FETs 302 and 304. The operational amplifier 308 applies negative feedback so that the voltage at the node 324 equals the voltage at the node 326. The voltage at the node 324 is a voltage V_EB1, which is the voltage between the emitter and base of the BJT 312. The voltage V_EB1 is complementary to temperature (i.e., has a negative Tempco). The voltage at the emitter of the BJT 314 is V_EB2, which is the voltage between the emitter and base of the BJT 314. The voltage V_EB2 is complementary to temperature. The voltage across the resistor 310, between the node 326 and the emitter of the BJT 314, is ΔV_BE = V_EB1 - V_EB2 = V_BE2 - V_BE1. The differential voltage ΔV_BE can be mathematically expressed as ΔV_BE = n*V_T*In(N), where V_T is the thermal temperature, n is the ideality factor, N is the ratio of emitter area between the BJT 314 and the BJT 312, and In denotes the natural logarithm function. For purposes of example herein, the ideality factor n is assumed to be one and is omitted from subsequent expressions. The thermal voltage V_T = KT/q, where T is the temperature in Kelvin, K is the Boltzmann constant, and q is the electron charge in coulombs. As such, ΔV_BE is proportional to temperature (i.e., has a positive Tempco). ΔV_BE is also dependent on the ratio of collector current, which is related to the base current by the beta factor (i.e., beta = Ic/lb, where Ic is the collector current and Ib is the base current). The current Iptat can be mathematically expressed as Iptat = ΔV_BE/R1, which is also proportional to temperature. The voltage V_P at the node 210 controls current sources in the Tempco circuits to mirror the current Iptat.
The operational amplifier 316 applies negative feedback through adjustment of the control voltage Vc to equalize the voltage at node 328 and the voltage at node 324 (e.g., V_EB1). Thus, the current Ictat (going from the node 330 into the resistor ladder 318) can be mathematically expressed as Ictat = V_EBI/R2". Since V_EB1 is complementary to temperature, then Ictat is also complementary to temperature. The voltage Vc at the node 212 controls current sources in the Tempco circuits to mirror the current Ictat. The current Ictat can be trimmed by varying the Flat Trim code. The flat trim balances the temperature coefficient by adjusting Ictat relative to Iptat so that Ictat + Iptat = Iztat is approximately constant over a range of temperature. Note that while the slope of Iptat with respect to temperature is constant, the slope of Ictat with respect to temperature is non-linear. Thus, Iztat varies from the desired constant value over a range of temperature. This first-order error is corrected, as described further below.
Fig. 5A is a schematic diagram depicting the zero Tempco circuit 204 according to an example. The zero Tempco circuit 204 includes p- channel FETs 502, 504, 506, and 508 (e.g., p-type MOSFETs). The zero Tempco circuit 204 further includes a curvature correction circuit 510, a resistor ladder 512, and a resistor ladder 554.
A source of the FET 502 is coupled to the node 110 that supplies Vcc. A drain of the FET 502 is coupled to a node 530. A gate of the FET 502 is coupled to the node 212 that supplies the control voltage Vc. A source of the FET 504 is coupled to the node 110 that supplies Vcc. A drain of the FET 504 is coupled to a node 530. A gate of the FET 504 is coupled to the node 210 that supplies the control voltage V_P. A source of the FET 506 is coupled to the node 110. A drain of the FET 506 is coupled to a node 532. A gate of the FET 506 is coupled to the node 212 that supplies the control voltage Vc. A source of the FET 508 is coupled to the node 110 that supplies Vcc. A drain of the FET 508 is coupled to the node 532. A gate of the FET 508 is coupled to the node 210 that supplies the control voltage V_P. The FETs 502 and 504 form a current source 514₁ that mirrors Ictat and Iptat. The FETs 506 and 508 form a current source 514₂ that mirrors Ictat and Iptat.
The resistor ladder 512, having a resistance R_LOAD1, is coupled between the node 530 and the ground node 112. A node 556 is coupled to a selected tap of the resistor ladder 512 based on the value of the Ref1 Trim code. Selection of the tap results in a resistance 512₁ coupled between the node 530 an the node 556, and a resistance 512₂ coupled between the node 556 and the ground node 112. The resistance 512₁ has a value R_LOAD1', and the resistance 512₂ has a value R_LOAD1". The curvature correction circuit 510 is coupled to the node 556 to supply a current Icor, as described further below.
The resistor ladder 554, having a resistance R_LOAD2, is coupled between the node 532 and the ground node 112. A node 558 is coupled to a selected tap of the resistor ladder 554 based on the value of the Ref2 Trim code. Selection of the tap results in a resistance 554₁ coupled between the node 532 and the node 558, and a resistance 554₂ coupled between the node 558 and the ground node 112. The resistance 554₁ has a value R_LOAD2', and the resistance 554₂ has a value R_LOAD2".
In operation, the control voltage Vc controls the FETs 502 and 506 to supply the current Ictat. The control voltage V_P controls the FETs 504 and 508 to supply the current Iptat. The currents Ictat and Iptat feed the node 530. The control circuit 114 sets the Ref1 Trim to control values of R_LOAD1' and R_LOAD1". The curvature correction circuit 510 supplies a current Icor to the resistor ladder 512 such that, in steady state condition, the sum of the currents Iztat and Icor conducts through the resistance R_LOAD1".
The node 556 supplies a voltage that is proportional to Iztat+lcor, which is referred to as V_ref1. The voltage V_ref1 has a zero Tempco.
The currents Ictat and Iptat feed the node 532. In steady state condition, the current Iztat conducts through the resistor ladder 554. The control circuit 114 controls sets Ref2 Trim to control values for R_LOAD2' and R_LOAD2". The node 558 supplies a voltage, V_ref2, which is proportional to Iztat. The voltage V_ref2 has a zero Tempco. The voltage output by the LPF 538 is proportional to Iztat. The operational amplifier 540, the resistor 544, the resistor 546, and the resistor 552 are configured as a non-inverting amplifier that applies a configured amount of gain to the voltage output by the LPF 538. The gain is determined by the resistance values of the resistors 544, 546, and 552. The node 542 supplies a zero Tempco voltage V_ref2. The resistors 544, 548, and 552 form a voltage divider that supplies a fraction of V_ref2 at the node 550 (e.g., half of the voltage to generate Vref₂/2).
The Ref1 Trim and Ref2 Trim codes set a direct current (DC) level of the corresponding pre-gain voltages at the nodes 556 and 558, respectively. Gain circuits can be used to amplifier or attenuate the pre-gain voltages. Voltage dividers can then provide one or more fractions of the post-gain reference voltage.
In the example, the zero Tempco circuit 204 includes two current sources 514 for mirroring Ictat and Iptat to generate three zero Tempco voltages. In other examples, the zero Tempco circuit 204 can include less or more than two current sources 514 for generating any number of zero Tempco voltages. In an example, one or both of the gain circuits 516 can be omitted. Alternatively, another current source 514 can feed another resistor ladder that supplies a pre-gain output voltage.
Fig. 5B is a schematic diagram depicting the curvature correction circuit 510 according to an example. The curvature correction circuit 510 includes p- channel FETs 564, 566, and 568 (e.g., p-type MOSFETs). The curvature correction circuit 510 further includes PNP BJTs 570 and 572, as well as a trans-conductance circuit 578.
Sources of the FETs 564, 566, and 568 are coupled to the node 110 that supplies Vcc. A drain of the FET 564 is coupled to the node 574, and a gate of the FET 564 is coupled to the node 212 that supplies the control voltage Vc. Drains of the FETs 566 and 568 are coupled to the node 5576. A gate of the FET 566 is coupled to the node 212 that supplies the control voltage Vc. A gate of the FET 568 is coupled to the node 210 that supplies the control voltage V_P. The width of the FETs 566 and 568 are half that of the FET 564. The FET 564 supplies a mirror of the current Ictat, the FET 566 supplies a mirror of the current Ictat/2, and the FET 568 supplies a mirror of the current lptat/2.
An emitter of the BJT 570 is coupled to the node 574 to provide the voltage V_EB3. An emitter of the BJT 572 is coupled to the node 576 to provide the voltage V_EB4. Bases and collectors of the BJTs 570 and 572 are coupled to the ground node 112. Thus, the BJTs 570 and 572 are diode-connected BJTs coupled between the node 574 and the ground node 112, and between the node 576 and the ground node 112, respectively. The BJT 572 has N' times the emitter area as the BJT 570, where N' is an integer greater than one.
Inputs of the trans-conductance circuit 578 are coupled to the nodes 574 and 576. An output of the trans-conductance circuit 578 is coupled to the node 556 and supplies the current Icor.
In operation, the current Ictat varies non-linearly with temperature. That is, the derivative of Ictat with respect to temperature is not constant. As such, any voltage generated from Iztat will vary over temperature. Fig. 6 is a graph 600 illustrating the dependence of V_ref1 on temperature. The graph 600 includes an axis 602 representing temperature, and an axis 606 representing the voltage V_ref1 in volts. As shown by a curve 610, the voltage V_ref1 has a convex bow with respect to temperature. That is, V_ref1 increases with increasing temperature until reaching a maximum value and then decreases with further increases in temperature.
Returning to Fig. 5B, the curvature correction circuit 510 applies second-order correction to Iztat to mitigate the temperature dependence of V_ref1 due to first-order error in Ictat. In particular, the differential voltage AV_BE2 = V_BE4 - V_BE3 = V_T*In((N'*Iztat/2)/I_S4) - V_T*In(Ictat/I_S3), where I_S4 and I_S3 are the reverse saturation currents of the BJTs 570 and 572, respectively. If the reverse saturation currents are approximately equal, the expression reduces to AV_BE2 = V_T ^*(In(N'^*Iztat/2) - In(Ictat)). The graph 600 in Fig. 6 includes an axis 604 representing AV_BE2 in volts. As shown by a curve 608, the voltage AV_BE2 has a concave bow with respect to temperature. That is, AV_BE2 decreases with increasing temperature until reaching a minimum value and then increases with further increases in temperature. The trans-conductance circuit 578 converts the differential voltage ΔV_BE2 into the current Icor, which has the same concave curvature over temperature. The trans-conductance circuit 578 injects the current Icor into the node 556. As temperature varies, the current Ictat + Icor is substantially constant due to the second-order curvature correction.
Fig. 5C is a schematic diagram depicting another portion 204A of the zero Tempco circuit 204 according to an example. The portion 204A of the zero Tempco circuit 204 includes p- channel FETs 580 and 582, as well as a resistor ladder 586. A source of the FET 580 is coupled to the node 110 that supplies Vcc. A drain of the FET 580 is coupled to a node 584. A gate of the FET 580 is coupled to the node 212 that supplies the control voltage Vc. A source of the FET 582 is coupled to the node 110 that supplies Vcc. A drain of the FET 582 is coupled to the node 584. A gate of the FET 582 is coupled to the node 210 that supplies the control voltage V_P. The FETs 580 and 582 form a current source 514₃ that mirrors Ictat and Iptat.
The resistor ladder 586, having a resistance R_LOAD3, is coupled between the node 584 and the ground node 112. A node 588 is coupled to a selected tap of the resistor ladder 586 based on the value of the Ref3 Trim code. Selection of the tap results in a resistance 586₁ coupled between the node 584 and the node 588, and a resistance 586₂ coupled between the node 588 and the ground node 112. The resistance 586₁ has a value R_LOAD3', and the resistance 586₂ has a value R_LOAD3". The node 588 supplies a voltage Vref3 that is a pre-gain zero Tempco voltage.
Fig. 7 is a schematic diagram depicting the negative Tempco circuit 206 according to the invention. The negative Tempco circuit 206 includes six p-channel FETs 702...712 and resistor ladders 718, 720, 728, and 730. Sources of the FETs 702...712 are coupled to the node 110 that supplies Vcc. Drains of the FETs 702 and 704 are coupled to a node 714. A drain of the FET 706 is coupled to a node 724. Drains of the FETs 708 and 710 are coupled to a node 716. A drain of the FET 712 is coupled to a node 736. Gates of the FETs 702 and 708 are coupled to the node 210 that supplies the control voltage V_P. Gates of the FETs 704, 706, 710, and 712 are coupled to the node 212 that supplies the control voltage Vc. The FETs 702, 704, and 706 form a first current source 715₁, and the FETs 708, 710, and 712 form a second current source 715₂.
The resistor ladder 718, having a resistance R3, is coupled between the node 714 and a node 726. The resistor ladder 720, having a resistance R4, is coupled between the node 726 and the ground node 112. The resistor ladders 718 and 720 are coupled in series between the node 714 and the ground node 112. A selected tap of the resistor ladder 718, as determined by the code Neg1 Trim generated by the control circuit 114, is coupled to a node 722. The resistor ladder 718 is effectively split between a resistance 718₁ and a resistance 718₂, where the resistance 718₁ has a value R3' and the resistance 718₂ has a value R3". A selected tap of the resistor ladder 720, as determined by the code Neg1 Slope Trim generated by the control circuit 114, is coupled to the node 724. The resistor ladder 720 is effectively split between a resistance 720₁ and a resistance 720₂, where the resistance 720₁ has a value R4' and the resistance 720₂ has a value R4".
The resistor ladder 728, having a resistance R5, is coupled between the node 716 and a node 734. The resistor ladder 730, having a resistance R6, is coupled between the node 734 and the ground node 112. The resistor ladders 728 and 730 are coupled in series between the node 716 and the ground node 112. A selected tap of the resistor ladder 728, as determined by the code Neg2 Trim generated by the control circuit 114, is coupled to a node 732. The resistor ladder 728 is effectively split between a resistance 728₁ and a resistance 728₂, where the resistance 728₁ has a value R5' and the resistance 728₂ has a value R5". A selected tap of the resistor ladder 730, as determined by the code Neg2 Slope Trim generated by the control circuit 114, is coupled to the node 736. The resistor ladder 730 is effectively split between a resistance 730₁ and a resistance 730₂, where the resistance 730₁ has a value R6' and the resistance 730₂ has a value R6".
In operation, the FETs 702 and 704 supply a current Iztat (i.e., Ictat+lptat) through the series combination of the resistor ladder 718 and the resistor ladder 720. The FET 706 supplies a mirror of Ictat through the resistance 720₂. The voltage at the node 722 is V_neg1 = Iztat*(R3+R4) + Ictat*R4". The voltage V_neg1 has a zero Temoco component Iztat*(R3+R4) and a negative Tempco component Ictat*R4". Thus, the voltage V_neg1 has a negative Tempco. The control circuit 114 sets the code Neg1 Slope Trim to control the slope of the negative Tempco for the voltage V_neg1. The control circuit 114 sets the code Neg1 Trim to control the DC level of the voltage V_neg1 given the code used for Neg1 Slope Trim.
The FETs 708 and 710 supply a current Iztat (i.e., Ictat+lptat) through the series combination of the resistor ladder 728 and the resistor ladder 730. The FET 712 supplies a mirror of Ictat through the resistance 730₂. The voltage at the node 732 is V_neg2 = Iztat*(R5+R6) + Ictat*R6". The voltage V_neg2 has a zero Temoco component Iztat*(R5+R6) and a negative Tempco component Ictat*R6". Thus, the voltage V_neg2 has a negative Tempco. The control circuit 114 sets the code Neg2 Slope Trim to control the slope of the negative Tempco for the voltage V_neg2. The control circuit 114 sets the code Neg2 Trim to control the DC level of the voltage V_neg2 given the code used for Neg2 Slope Trim. The voltage V_neg2 is set independent of the voltage V_neg1.
Although two current sources 715 and two pairs of resistor ladders are shown, the negative Tempco circuit 206 can include any number of current sources 715, each coupled to a pair of resistor ladders as shown in Fig. 7. In this manner, the negative Tempco circuit can supply any number of complementary-to-temperature voltages. In addition, although gain circuits are omitted from Fig. 7, in some examples, one or both of the pre-gain voltage outputs can be coupled to a gain circuit, similar to the configuration shown in Fig. 5A.
Fig. 8 is a schematic diagram depicting the positive Tempco circuit 208 according to an example. The positive Tempco circuit 208 includes p- channel FETs 802 and 804, a resistor ladder 824, switches 808 and 810, and digital-to-analog (DAC) current sources 816 and 820. Sources of the FETs 802 and 804 are coupled to the node 110 that supplies the voltage Vcc. Drains of the FETs 802 and 804 are coupled to a node 806. A gate of the FET 802 is coupled to the node 212 that supplies the control voltage Vc. A gate of the FET 804 is coupled to the node 210 that supplies the control voltage V_P. The FETs 802 and 804 form a current source 815 that supplies Iztat = Ictat + Iptat.
The resistor ladder 824, having a resistance R7, is coupled between the node 806 and the ground node 112. A selected tap of the resistor ladder 824, as controlled by the Blk Trim code set by the control circuit 114, is coupled to a node 826. The resistor ladder 824 is effectively split into a resistance 824₁ and a resistance 824₂, having values R7' and R7", respectively. The resistance 824₁ is coupled between the node 806 and the node 826. The resistance 824₂ is coupled between the node 826 and the ground node 112. The node 826 supplies a voltage V_BLK.
One terminal of the switch 808 is coupled to the node 210 that supplies the control voltage V_P. Another terminal of the switch 808 is coupled to a node 812. A reference voltage input of the current DAC 816 is coupled to the node 812. The current DAC 816 includes a digital control input coupled to a bus 818 that supplies a digital signal Blk_p. A current output of the current DAC 816 is coupled to the node 806. A supply voltage input of the current DAC 816 is coupled to the node 110 that supplies the voltage Vcc.
One terminal of the switch 810 is coupled to the node 212 that supplies the control voltage Vc. Another terminal of the switch 810 is coupled to a node 814. A reference voltage input of the current DAC 820 is coupled to the node 814. The current DAC 820 includes a digital control input coupled to a bus 822 that supplies a digital signal Blk_c. A current output of the current DAC 820 is coupled to the ground node 112. A supply voltage input of the current DAC 820 is coupled to the node 806.
In operation, the voltage V_BLK = Iztat^*R7" + Idac*R7". The current Idac, which flows into the node 806, depends on the state of the switches 808 and 810. If both switches 808 and 810 are open, the current Idac is zero. If the switch 808 is closed and the switch 810 is open, the current DAC 816 receives the voltage V_P. The current DAC 816 provides a ratio of the current Iptat based on the code supplied by the digital signal Blk_p. The current DAC 816 outputs a current ldac_p. The current Idac equals the current Idac_p supplied by the current DAC 816. In such case, the voltage V_BLK includes a zero Tempco component Iztat^*R7" and a positive Tempco component Idac_p*R7".
If the switch 810 is closed and the switch 808 is open, the current DAC 820 receives the voltage Vc. The current DAC 820 sinks a ratio of the current Ictat based on the code supplied by the digital signal Blk_C. The current DAC 820 sinks a current Idac_c. The current Idac equals the -Idac_c supplied by the current DAC 820. In such case, the voltage V_BLK includes a zero Tempco component Iztat^*R7" and a positive Tempco component -Idac_c*R7".
If both switches 808 and 810 are closed, the current Idac = Idac_p - ldac_c. In such case, the voltage V_BLK includes a zero Tempco component Iztat^*R7" and a positive Tempco component (Idac_p-Idac_c)*R7".
In some examples, the control circuit 114 generates control signals Blk Ptat and Blk Ctat to open and close the switches 808 and 810 in an alternating sequence. The control circuit 114 controls the magnitude of the oscillation using the digital signals Blk_p and Blk_c. The control circuit 114 controls the DC level of the voltage V_BLK using the Blk Trim code. While a single current source 815 and load (resistor ladder 824 and current DACs 816, 820) are shown, it is to be understood that the positive Tempco circuit 208 can include more than one current source 815 and associated load to generate more than one positive Tempco voltage. In some examples, the pre-gain voltage V_BLK can be coupled to a gain circuit to provide a positive Tempco voltage with gain.
Fig. 9 is a flow diagram depicting a method 900 of generating a voltage reference according to an example. The method 900 begins at block 902, where the reference circuit 202 generates Iptat and the control voltage Vp. At block 904, the reference circuit 202 generates Ictat and the control voltage Vc. At block 906, one or more current sources generate a sum current of Iptat and Ictat in response to the control voltages Vp and Vc. For example, at block 908, the zero Tempco circuit 204 generates a zero Tempco voltage from the sum current. At block 910, the negative Tempco circuit 206 generates a negative Tempco voltage from the sum current. At block 912, the positive Tempco circuit 208 generates a positive Tempco voltage from the sum current.
Fig. 10 is a block diagram depicting a test system 1000 according to an example. The test system 1000 includes automatic test equipment (ATE) 1002 and a wafer 1004 having a plurality of ICs 1100. The ATE 1002 includes a central processing unit (CPU) 1008, a memory 1012, input/output (IO) circuits 1010, and support circuits 1006. The CPU 1008 can be any type of general-purpose processor, such as an x86-based processor, ARM^®-based processor, or the like. The CPU 1008 can include one or more cores and associated circuitry (e.g., cache memories, memory management units (MMUs), interrupt controllers, etc.). The CPU 1008 is configured to execute program code that perform one or more operations described herein and which can be stored in the memory 1012. The support circuits 1006 include various devices that cooperate with the CPU 608. For example, the support circuits 1006 can include a chipset (e.g., a north bridge, south bridge, platform host controller, etc.), voltage regulators, firmware (e.g., a BIOS), and the like. In some examples, the CPU 1008 can be a System-in-Package (SiP), System-on-Chip (SoC), or the like, which absorbs all or a substantial portion of the functionality of the chipset (e.g., north bridge, south bridge, etc.). The IO circuits 1010 include various circuits configured for communication with the ICs 1100.
The memory 1012 is a device allowing information, such as executable instructions and data, to be stored and retrieved. The memory 1012 can include, for example, one or more random access memory (RAM) modules, such as double-data rate (DDR) dynamic RAM (DRAM). The ATE 1002 can include various other devices, including local storage devices (e.g., one or more hard disks, flash memory modules, solid state disks, and optical disks) and/or a storage interface that enables the test system 1000 to communicate with one or more network data storage systems.
Fig. 11 is a flow diagram depicting a method 1100 of setting trim codes in a voltage reference circuit according to an example. The method 1100 can be performed by the ATE 1002 for setting the Flat Trim in the reference circuit 202, and the Ref_x Trim (e.g., Ref1 Trim, Ref2 Trim, etc.) in the circuit 500A, for each IC 100 on the wafer 604.
The method 1100 begins at step 1102, where the wafer 1004 is disposed in a 0 degree Celsius (0C) environment and the ATE 1002 sequences through trim codes for the Flat Trim and measures Vref1. The ATE 1002 obtains a plurality of Vref1 values for a corresponding plurality of trim codes of the Flat Trim. At step 704, the ATE 1002 fits the Vref1 values obtained at step 1102 to a polynomial curve having one or more coefficients (e.g., three coefficients). The ATE 1002 stores the values of the coefficients in the IC 100 (e.g., in the control circuit 114 using, for example, an electronic fuse (e-fuse) or the like type memory element). Fig. 12A is a graph 1200 depicting flat trim codes versus output voltage at different temperatures according to an example. In the graph 1200, the horizontal axis represents flat trim code and the vertical axis represents output voltage. A curve 1202 represents the polynomial curve determined at 1104 (where T1 = 0 C).
At step 1106, the wafer 1004 is disposed in a 100 degree Celsius (100C) environment and the ATE 1002 sequences through trim codes for the Flat Trim and measures Vref1. The ATE 1002 obtains a plurality of Vref1 values for a corresponding plurality of trim codes of the Flat Trim. At step 1108, the ATE 1002 fits the Vref1 values obtained at step 1106 to a polynomial curve having the same order as that used in step 1104. In the graph 1200, a curve 1204 represents the polynomial curve determined at step 1108.
At step 1110, the ATE 1002 determines an intersection between the Vref1 curve at 0C and the Vref1 curve at 100C. The ATE 1002 can generate the Vref1 curve at 0C by obtaining the coefficients stored by the control circuit 114 in the IC 100. The ATE 1002 generates the Vref1 curve at 100C in step 1108. At step 712, the ATE 1002 determines a trim setting for the Flat Trim corresponding to the intersection between the Vref1 curve at 0C and the Vref1 curve at 100C. As shown in the graph 1200, the intersection of the curve 1202 and 1204 results in the determined flat trim code value. At step 1114, the ATE 1002 sets the Flat Trim to the determined trim code at step 1112 and adjusts the Ref1 Trim to set a desired voltage of Vref1 (e.g., 1V). Fig. 12B is a graph 1201 depicting ref trim codes versus output voltage at a particular temperature (T = T2) according to an example. In the graph 1201, the horizontal axis represents ref trim code and the vertical axis represents output voltage. A curve 1206 represents ref trim code versus output voltage and an output voltage of 1V results in the determined ref trim code value.
Fig. 13 is a flow diagram depicting a method 1300 of setting trim codes in a voltage reference circuit according to an example. The method 1300 can be performed by the ATE 1002 for setting the Flat Trim in the reference circuit 202, and the Ref_x Trim (e.g., Ref1 Trim, Ref2 Trim, etc.) in the circuit 500A, for each IC 100 on the wafer 1004.
The method 1300 begins at step 902, where the ATE 1002 selects an approximate trim code for the Flat Trim. The approximate trim code for the Flat Trim can be set based on simulations of the voltage reference circuit. At step 1304, the wafer 1004 is disposed in a 0C environment and the ATE 1002 selects a trim code for the Ref1 Trim that sets Vref1 to a desired value (e.g., 1 V). The ATE 1002 can adjust the Ref1 Trim and measure Vref1 until Vref1 obtains the desired value. At step 1306, the ATE 1002 stores the selected trim code for Ref1 Trim in the IC 100 (e.g., in the control circuit 114 using, for example, an electronic fuse (e-fuse) or the like type memory element). At step 1308, the wafer 1004 is disposed in a 100C environment and the ATE 1002 selects a trim code for the Ref1 Trim that sets Vref1 to the desired value (e.g., 1 V). At step 1310, the ATE 1002 determines the slope of the Ref1 Trim code over temperature. For example, the ATE 1002 can compute the difference between the Ref1 Trim code values at 0C and at 100C. Fig. 14A is a graph 1400 depicting measurements of the Ref1 Trim Code at two different temperatures according to an example. In the graph 1400, the horizontal axis represents temperature and the vertical axis represents Ref1 Trim Code value. At temperature T1, code1 is obtained. At temperature T2, code2 is obtained. If the temperature coefficient was zero, the same code would be obtained at both temperatures. The ATE 1002 determines the slope of curve 1002 at step 1310. At step 912, the ATE 1002 obtains a trim code value for the Flat Trim from a lookup table based on the Ref1 Trim code slope determined at step 1310. The lookup table can include a plurality of trim code values for the Flat Trim for a corresponding plurality of Ref1 Trim code slope values. Fig. 14B is a graph 1001 depicting a lookup of the flat trim code given a slope of Ref1 Trim according to an example. In the graph 1401, the horizontal axis represents flat trim code and the vertical axis represents the slope of the curve 1402 shown in Fig. 10A. The temperature coefficient determined in step 1310 from the curve 1402 is corrected by changing the flat trim code setting based on a curve 1404.
Fig. 15 is a block diagram depicting a programmable IC 1 according to an example in which the voltage reference circuit 200 described herein can be used. The programmable IC 1 includes programmable logic 3, configuration logic 25, and configuration memory 26. The programmable IC 1 can be coupled to external circuits, such as nonvolatile memory 27, DRAM 28, and other circuits 29. The programmable logic 3 includes logic cells 30, support circuits 31, and programmable interconnect 32. The logic cells 30 include circuits that can be configured to implement general logic functions of a plurality of inputs. The support circuits 31 include dedicated circuits, such as transceivers, input/output blocks, digital signal processors, memories, and the like. The logic cells and the support circuits 31 can be interconnected using the programmable interconnect 32. Information for programming the logic cells 30, for setting parameters of the support circuits 31, and for programming the programmable interconnect 32 is stored in the configuration memory 26 by the configuration logic 25. The configuration logic 25 can obtain the configuration data from the nonvolatile memory 27 or any other source (e.g., the DRAM 28 or from the other circuits 29). In some examples, the programmable IC 1 includes a processing system 2. The processing system 2 can include microprocessor(s), memory, support circuits, IO circuits, and the like.
Fig. 16 illustrates a field programmable gate array (FPGA) implementation of the programmable IC 1 that includes a large number of different programmable tiles including transceivers 37, configurable logic blocks ("CLBs") 33, random access memory blocks ("BRAMs") 34, input/output blocks ("IOBs") 36, configuration and clocking logic ("CONFIG/CLOCKS") 42, digital signal processing blocks ("DSPs") 35, specialized input/output blocks ("I/O") 41 (e.g., configuration ports and clock ports), and other programmable logic 39 such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. The FPGA can also include PCle interfaces 40, analog-to-digital converters (ADC) 38, and the like.
In some FPGAs, each programmable tile can include at least one programmable interconnect element ("INT") 43 having connections to input and output terminals 48 of a programmable logic element within the same tile, as shown by examples included at the top of Fig. 11. Each programmable interconnect element 43 can also include connections to interconnect segments 49 of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element 43 can also include connections to interconnect segments 50 of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments 50) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments 50) can span one or more logic blocks. The programmable interconnect elements 43 taken together with the general routing resources implement a programmable interconnect structure ("programmable interconnect") for the illustrated FPGA.
In an example implementation, a CLB 33 can include a configurable logic element ("CLE") 44 that can be programmed to implement user logic plus a single programmable interconnect element ("INT") 43. A BRAM 34 can include a BRAM logic element ("BRL") 45 in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile 35 can include a DSP logic element ("DSPL") 46 in addition to an appropriate number of programmable interconnect elements. An IOB 36 can include, for example, two instances of an input/output logic element ("IOL") 47 in addition to one instance of the programmable interconnect element 43. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element 47 typically are not confined to the area of the input/output logic element 47.
In the pictured example, a horizontal area near the center of the die (shown in Fig. 16) is used for configuration, clock, and other control logic. Vertical columns 51 extending from this horizontal area or column are used to distribute the clocks and configuration signals across the breadth of the FPGA.
Some FPGAs utilizing the architecture illustrated in Fig. 11 include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic.
Note that Fig. 16 is intended to illustrate only an exemplary FPGA architecture. For example, the numbers of logic blocks in a row, the relative width of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top of Fig. 11 are purely exemplary. For example, in an actual FPGA more than one adjacent row of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA.
A number of non-limited examples are provided below.
In one example, a voltage reference circuit according to claim 1 is provided.
Some such voltage reference circuit may further include: a third current source coupled to a third load circuit, the third current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the third load circuit generating a positive Tempco voltage from the sum current and at least one of the complementary-to-temperature current and the proportional-to-temperature current.
In some such voltage reference circuit, the third current source may include a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage.
In some such voltage reference circuit, the third load circuit may include: a first current digital-to-analog converter (DAC), switchably coupled to receive the first control voltage, and configured to supply a first positive temperature coefficient (Tempco) current; a second current DAC, switchably coupled to receive the second control voltage, and configured to supply a second positive Tempco current; and a resistor ladder coupled between the first common drain and a ground node, the resistor ladder converting the sum current plus one or both of the first positive Tempco current and the second positive Tempco current into the positive Tempco voltage.
In some such voltage reference circuit, the first current source may include a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage, and wherein the first load circuit may include a resistor ladder coupled between the first common drain and a ground node, the resistor ladder converting the sum current into the zero Tempco voltage.
Some such voltage reference circuit may include: a curvature compensation circuit configured to inject a correction current into the resistor ladder to combine with the sum current, the curvature compensation circuit comprising: a third FET and a fourth FET having a second common source and a second common drain, a gate of the third FET coupled to receive the first control voltage and a gate of the third FET coupled to receive the second control voltage; a fifth FET having a gate coupled to receive the second control voltage; a first diode-connected bipolar junction transistor (BJT) coupled between a drain of the fifth FET and the ground node; a second diode-connected bipolar junction transistor (BJT) coupled between the second common drain and the ground node; and a trans-conductance circuit configured to convert a voltage between the drain of the fifth FET and the second common drain to the correction current.
In some such voltage reference circuit, the second current source may include: a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage; and a third FET having a gate coupled to the second control voltage; and wherein the second load circuit may include: a first resistor ladder and a second resistor ladder coupled in series between the first common drain and a ground node, the first and second resistor ladders receiving the sum current from the first common drain, a portion of the second resistor ladder receiving the complementary-to-temperature current from a drain of the third FET.
In some such voltage reference circuit, the reference circuit may include: a first field effect transistor (FET) and a second FET having a first common source and a first common gate; a first diode-connected bipolar junction transistor (BJT) coupled between a drain of the first FET and a ground node; a first resistor and a second diode-connected BJT coupled in series between a drain of the second FET and the ground node; a first operational amplifier having a non-inverting input coupled to the drain of the second FET, an inverting input coupled to the drain of the first FET, and an output coupled to the first common gate; a third FET having a source coupled to the common source; a resistor ladder coupled between a drain of the third FET and the ground node; and a second operational amplifier having an inverting input coupled to the drain of the first FET, a non-inverting input coupled to the resistor ladder, and an output coupled to a gate of the third FET.
In another example, a method of generating a voltage reference according to claim 9 is provided. Some such method may further include: generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in a third current source response to the first and second control voltages; and generating a positive Tempco voltage from the sum current and at least one of the complementary-to-temperature current and the proportional-to-temperature current in a third load circuit coupled to the third current source. In some such method, the step of generating the positive Tempco voltage may include: supplying a first positive Tempco current from a first current digital-to-analog converter (DAC) switchably coupled to receive the first control voltage;

supplying a second positive Tempco current from a second current DAC switchably coupled to receive the second control voltage; and
converting the sum current plus one or both of the first positive Tempco current and the second positive Tempco current into the positive Tempco voltage in a resistor ladder circuit.

Some such method may further include: injecting a correction current into the first load circuit to combine with the sum current.
While the foregoing is directed to specific examples, other and further examples may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

A voltage reference circuit (200), comprising:
a reference circuit (202) comprising a first circuit configured to generate a proportional-to-temperature current (Iptat) and corresponding first control voltage (Vp) and a second circuit configured to generate a complementary-to-temperature current (Ictat) and corresponding second control voltage (Vc);

a first load circuit; and

a first current source (514₁-514₃) coupled to the first load circuit, the first current source (514₁-514₃) generating a sum current of the proportional-to-temperature current (Iptat) and the complementary-to-temperature current (Ictat) in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient, Tempco, voltage from the sum current; the voltage reference circuit characterised in that it further comprises:
a second load circuit; and

a second current source (715₂) coupled to the second load circuit, the second current source (715₂) generating another sum current of the proportional-to-temperature current (Iptat) and the complementary-to-temperature current (Ictat) in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the other sum current and the complementary-to-temperature current (Ictat), wherein the second load circuit comprises a first resistor ladder (728) and a second resistor ladder (730) coupled in series between the second current source (715₂) and a ground node (112), the first and second resistor ladders (728, 730) receiving the other sum current, a portion of the second resistor ladder (730) receiving the complementary-to-temperature current (Ictat), the first resistor ladder (728) configured to control the level of the negative Tempco voltage and the second resistor ladder (730) configured to control the slope of the negative Tempco voltage.
The voltage reference circuit (200) of claim 1, further comprising:
a third current source coupled to a third load circuit, the third current source generating the sum current of the proportional-to-temperature current (Iptat) and the complementary-to-temperature current (Ictat) in response to the first and second control voltages, the third load circuit generating a positive Tempco voltage from the sum current and at least one of the complementary-to-temperature current (Ictat) and the proportional-to-temperature current (Iptat).
The voltage reference circuit (200) of claim 2, wherein the third current source comprises a first field effect transistor, FET, and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage (Vp) and a gate of the second FET coupled to receive the second control voltage (Vc).
The voltage reference circuit (200) of claim 3, wherein the third load circuit comprises:
a first current digital-to-analog converter, DAC, switchably coupled to receive the first control voltage (Vp), and configured to supply a first positive temperature coefficient, Tempco, current;

a second current DAC, switchably coupled to receive the second control voltage (Vc), and configured to supply a second positive Tempco current; and

a resistor ladder coupled between the first common drain and a ground node (112), the resistor ladder converting the sum current plus one or both of the first positive Tempco current and the second positive Tempco current into the positive Tempco voltage.
The voltage reference circuit (200) of claim 1, wherein the first current source (514₁) comprises a first field effect transistor, FET, (502) and a second FET (504) having a first common source and a first common drain, a gate of the first FET (502) coupled to receive the first control voltage (Vp) and a gate of the second FET (504) coupled to receive the second control voltage (Vc), and wherein the first load circuit comprises a third resistor ladder (512) coupled between the first common drain and a ground node (112), the third resistor ladder converting the sum current into the zero Tempco voltage.
The voltage reference circuit (200) of claim 5, further comprising:
a curvature compensation circuit (510) configured to inject a correction current (Icor) into the third resistor ladder to combine with the sum current, the curvature compensation circuit (510) comprising:
a third FET (568) and a fourth FET (566) having a second common source and a second common drain, a gate of the third FET (568) coupled to receive the first control voltage (Vp) and a gate of the fourth FET (566) coupled to receive the second control voltage (Vc);

a fifth FET (564) having a gate coupled to receive the second control voltage (Vc);

a first diode-connected bipolar junction transistor, BJT, (570) coupled between a drain of the fifth FET (564) and the ground node (112);

a second diode-connected bipolar junction transistor, BJT, (572) coupled between the second common drain and the ground node (112); and

a trans-conductance circuit (578) configured to convert a voltage between the drain of the fifth FET (564) and the second common drain to the correction current (Icor).
The voltage reference circuit (200) of claim 1, wherein the second current source (715₂) comprises:
a first field effect transistor, FET, and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage; and

a third FET having a gate coupled to the second control voltage.
The voltage reference circuit (200) of claim 1, wherein the reference circuit (202) comprises:
a first field effect transistor, FET, (302) and a second FET (304) having a first common source and a first common gate;

a first diode-connected bipolar junction transistor, BJT, (312) coupled between a drain of the first FET (302) and a ground node (112);

a first resistor (310) and a second diode-connected BJT (314) coupled in series between a drain of the second FET (304) and the ground node (112);

a first operational amplifier (308) having a non-inverting input coupled to the drain of the second FET (304), an inverting input coupled to the drain of the first FET (302), and an output coupled to the first common gate;

a third FET (306) having a source coupled to the common source;

a resistor ladder (318) coupled between a drain of the third FET (306) and the ground node (112); and

a second operational amplifier (316) having an inverting input coupled to the drain of the first FET (302), a non-inverting input coupled to the resistor ladder (318), and an output coupled to a gate of the third FET (306).
A method of generating a voltage reference, comprising:
generating a proportional-to-temperature current (Iptat) and corresponding first control voltage in a first circuit of a reference circuit (202);

generating a complementary-to-temperature current (Ictat) and corresponding second control voltage in a second circuit of the reference circuit (202);

generating a sum current of the proportional-to-temperature current (Iptat) and the complementary-to-temperature current (Ictat) in a first current source (514₁-514₃) in response to the first and second control voltages and

generating a zero temperature coefficient, Tempco, voltage from the sum current in a first load circuit coupled to the first current source ;characterised in that the method further comprises:
generating another sum current of the proportional-to-temperature current (Iptat) and the complementary-to-temperature current (Ictat) in a second current source (715₂) in response to the first and second control voltages; and

generating a negative Tempco voltage from the other sum current and the complementary-to-temperature current (Ictat) in a second load circuit coupled to the second current source (715₂), wherein the second load circuit comprises a first resistor ladder and a second resistor ladder coupled in series between the second current source (715₂) and a ground node (112), the first and second resistor ladders receiving the other sum current, a portion of the second resistor ladder receiving the complementary-to-temperature current (Ictat), the first resistor ladder configured to control the level of the negative Tempco voltage and the second resistor ladder configured to control the slope of the negative Tempco voltage.
The method of claim 9, further comprising:
generating the sum current of the proportional-to-temperature current (Iptat) and the complementary-to-temperature current (Ictat) in a third current source response to the first and second control voltages; and

generating a positive Tempco voltage from the sum current and at least one of the complementary-to-temperature current (Ictat) and the proportional-to-temperature current (Iptat) in a third load circuit coupled to the third current source.
The method of claim 10, wherein the step of generating the positive Tempco voltage comprises:
supplying a first positive Tempco current from a first current digital-to-analog converter (DAC) switchably coupled to receive the first control voltage;

supplying a second positive Tempco current from a second current DAC switchably coupled to receive the second control voltage; and

converting the sum current plus one or both of the first positive Tempco current and the second positive Tempco current into the positive Tempco voltage in a resistor ladder circuit.
The method of claim 9, further comprising:
injecting a correction current into the first load circuit to combine with the sum current.