JPH0618012B2 - Constant voltage circuit - Google Patents

Description

The present invention relates to a constant voltage circuit using a reference voltage source.

First, a conventional constant voltage circuit will be described.

As an example of a conventional constant voltage circuit, there are circuits shown in FIGS. 1 and 2. FIG. 1 shows the most basic circuit example of a constant voltage circuit. In FIG. 1, reference numeral 1 is an operational amplifier, 2 is a zener diode, and 3 is a resistor. The reference voltage source 4 is constituted by a circuit in which the zener diode 2 and the resistor 3 are connected in series. By using the non-inverting input terminal as a reference voltage, the terminal 5
This is a circuit system for controlling the constant voltage circuit voltage Vreg taken out to Vreg = Vz (201).

FIG. 2 shows an example in which a constant voltage circuit is configured by providing a reference voltage source as a reference voltage circuit in a MOS integrated circuit. In FIG. 2, 6 is an operational amplifier, and 7, 8 and 11 are P channels M.
OSFET, 9 is an N-channel MOSFET, and 12 is a load. MOSFETs 7, 8 and 9 are respectively connected in series, the connection point between MOSFETs 7 and 8 is connected to the gate of MOSFET 7, and the connection point between MOSFETs 8 and 9 is MOSF.
The reference voltage circuit 10 is formed by connecting to the gates of ET8 and ET9. Where P channel MOSF
The βs of the ETs 7 and 8 and the N-channel MOSFET 9 are set to β _p0 , β _p1 , and β _N1 , respectively, and the threshold voltages are set to V _TP , V _TP , and V _TN , respectively. Also M
The potential at the connection point between the OSFETs 7 and 8 is V ₀ , and the MOSFET is
The potential at the connection point of 8 and 9 is V _1, and −V _SS is a reference of 0 potential, and the potential difference between + V _DD and −V _SS is V _DD
If so, the currents flowing through the MOSFETs 7, 8 and 9 are equal. The relational expression of However, Is obtained.

By designing β _p0 << β _p1 β _p0 << β _N1 , the equation (203) becomes V ₀ ≈V _TP + V _TN (204). Looking at the equation (204), V ₀ is the power supply voltage V
Since there is no _DD term, it can be used as a reference voltage.

The output V ₀ of the reference voltage circuit 10 configured as described above is input to the inverting input terminal of the operational amplifier 6, and the output voltage of the constant voltage circuit is input to the non-inverting input terminal of the operational amplifier 6, so that the reference voltage circuit 10 P channel M compared with the reference voltage
The potential V of the constant voltage circuit output terminal 13 is controlled by controlling the gate potential of the OSFET 11 and adjusting the equivalent resistance.
_{Reg is controlled} to V _reg ≉V _TP + V _TN (205).

The operation of the conventional constant voltage circuit shown in FIGS. 1 and 2 has been briefly described above. Before describing the advantages and disadvantages, the circuit shown in FIG. 3 will be described as an example of the load side.

The circuit shown in FIG. 3 is an amplifier circuit using a CMOS inverter that constitutes a part of the oscillator circuit. In FIG. 3, 14
Is P-channel MOSFET, 15 is N-channel MOSF
ET, 16 are capacitors as loads of the amplifier circuit, 17
Is a feedback resistor for adjusting the DC bias. P Channel M
The gates of the OSFET 14 and the N-channel MOSFET 15 are commonly connected, and the drains thereof are also commonly connected. Β of MOSFETs 14 and 15 are respectively β _PC and β
_NC and the threshold voltage is V
Let _TP and V _TN . When the power supply voltage is V _DD , the electrostatic capacity of the capacitor 16 is C, and the input signal is a sine wave with an angular frequency ω, the signal input from the input terminal 18 is defined by the amplitude ratio of the signal output to the output terminal 19. Gain G
Is approximately when the input amplitude is small Is represented. The current Ic consumed by the circuit of FIG. 3 is Is proportional to, or has a strong correlation with. The main conditions required for the amplifier circuit of FIG. 3 are that a high gain G is obtained and that the current consumption Ic is small. However, as can be seen from the equations (206) and (207), it is a conflicting requirement that the current consumption increases as the gain increases and the gain decreases as the current consumption decreases. I understand. Therefore, it is conceivable to secure the minimum required gain and to let only the corresponding consumption current flow.
The value of V _{DD in} the equations (6) and (207) is changed to (V
Control according to the value of _TP + V _TN , that is, approximately (V
It is preferable to operate with a constant voltage circuit that outputs the value of ( _TP + V _TN ), in the case of the load of the circuit as shown in FIG.

The constant voltage circuit shown in FIG. 1 is a circuit based on the idea of maintaining a constant voltage as much as possible, and is a desirable circuit for a load that requires the condition, and is generally widely used.
However, as described above, for the load of the circuit shown in FIG. 3, the sum of the threshold voltages (V _TP +
When V _TN ) varies due to manufacturing factors, it is preferable that the output voltage of the constant voltage circuit also be changed accordingly. Therefore, the constant voltage circuit as shown in FIG. 2 is preferable. Recognize. Therefore, it has been found that it is not always good to keep a constant voltage regardless of the load. Also consider the temperature characteristics of the output voltage of the constant voltage circuit.

In the circuit of FIG. 1, the Zener voltage of the Zener diode 2 has a certain temperature characteristic, but if a resistance element having a temperature characteristic that cancels it is used for the resistor 3, the temperature characteristic of the constant voltage circuit can be almost eliminated. I can. However, since the gain of the amplifier circuit of FIG. 3 is expressed by the equation (206),
The oscillation stop voltage VOSC as an oscillation circuit having a close relationship with the gain also has temperature characteristics because β and the threshold voltage have temperature characteristics.

In FIG. 4, 20 shows an example of the temperature characteristic of the oscillation stop voltage, and 21 shows an example of the temperature characteristic of the output voltage of the constant voltage circuit of FIG. The β of the MOSFET decreases as the temperature rises, and the threshold voltage also decreases, but the temperature characteristic of the threshold voltage is (2
Since the influence is large in the expression (06), the oscillation stop voltage decreases as the temperature rises. On the contrary, the oscillation stop voltage becomes high when the temperature is low. On the other hand, assuming that the output voltage of the constant voltage circuit has almost no temperature characteristic, as shown in the characteristic of FIG.
0 and 21 reverse at a certain temperature. In this case, it means that the oscillation stops at a low temperature. In other words, it is not always good that the output voltage of the constant voltage circuit does not have temperature characteristics.

FIG. 5 shows the temperature characteristics of the output voltage of the constant voltage circuit shown in FIG. The output voltage of the constant voltage circuit in FIG.
As expressed by the equation (05), since it is almost the sum of the threshold voltages, it also has a temperature characteristic relatively close to the temperature characteristic 20 of the oscillation stop voltage related to the sum of the threshold voltages. The temperature characteristic 22 of the output voltage of the constant voltage circuit shown in FIG. 2 is different from the temperature characteristic 20 of the oscillation stop voltage by an amount irrelevant to the temperature characteristic of β related to. Therefore, in the case of FIG. 5, it means that the oscillation stops at high temperature. The constant voltage circuit shown in FIG. 2 is a circuit designed to meet the requirements of the circuit shown in FIG. 3 as a load, but suggests that it is difficult to match even the subtle characteristics of the temperature characteristics. .

As described above, the conventional constant voltage circuit is mainly a circuit configured based on the idea of maintaining a constant voltage.However, when the characteristics on the load side cause manufacturing variations or have temperature characteristics, the Continuing to maintain the voltage can have bad consequences. In addition, although the temperature characteristic is included as a result, there are many circuits that do not necessarily have the desired characteristic on the load side because the design concept is insufficient. Further, in the conventional constant voltage circuit, an auxiliary element or circuit for temperature compensating the reference voltage source is used, but since it is basically constituted by only one reference voltage source, The degree of freedom in designing the circuit is limited, and it is not always possible to obtain a circuit with satisfactory characteristics.

The present invention breaks away from the conventional idea of “keeping a constant voltage circuit at a constant voltage” and provides the most desirable characteristics for the load side.
The present invention provides a circuit that is positively applied to a constant voltage circuit and a circuit design method.

The essence of the present invention is to obtain a constant voltage circuit having arbitrary characteristics by combining the characteristics of a plurality of reference voltage sources having different characteristics.

Hereinafter, the present invention will be described in detail based on examples. In addition,
In the following description, the "characteristic" of the "most desirable characteristic for the load side" described above may be anything,
For the sake of clarity, the temperature characteristics will be described as an example. Further, any circuit may be used as long as the circuit operation is essentially the same, but in the following description, an example of a MOS integrated circuit will be described.

FIG. 6 is a first embodiment of a constant voltage circuit for explaining the present invention.

In FIG. 6, the circuit indicated by the broken line 10 is the same circuit as the reference voltage circuit 10 for outputting the sum of the threshold voltages by the P-channel MOSFETs 7 and 8 and the N-channel MOSFET 9 described in FIG. Is. Therefore, the first reference voltage circuit 10 in FIG.
Is the voltage shown in equation (204) as the reference voltage.
Obtained from the connection point of ET8 and ET7. The circuit indicated by the broken line 27 is the second reference voltage circuit. In the second reference voltage circuit 27, 23 and 24 are P channel MOSFETs.
And 25 and 26 are N-channel MOSFETs.
The sources of the P-channel MOSFETs 23 and 24 are + V
N channel MOSFETs 25 and 26 connected to _DD
Source is connected to -V _SS . P Channel MO
Drain of SFET23 and N channel MOSFET25
The drains of are connected. P-channel MOSFET
The drain of 24 and the drain of the N-channel MOSFET 26 are connected. The gate of the P-channel MOSFET 23 is connected to the drain of the P-channel MOSFET 23. The gate of the P-channel MOSFET 24 is -V
_It is connected to _SS . The gates of the N-channel MOSFETs 25 and 26 are both connected to the drain of the N-channel MOSFET 26. Where P channel MOSF
Let β of ET23 and 24 be β _p2, and threshold voltages be V _TPL and V _TPH , respectively. Both β of the N-channel MOSFETs 25 and 26 are set to β _N2, and both threshold voltages are set to V _TN . Also, -V
_{SS is set} to 0 potential, and the potential difference between + V _DD and −V _SS is V
Let _DD be the potential at the connection point of MOSFETs 23 and 25 as V
₂ and the potential at the connection point of MOSFETs 24 and 26 is V ₃
And At this time, the MOSFETs 23, 24, 25, 2
If 6 works in all saturation regions, the MOSFE
Since the currents flowing through T23 and 25 are equal The relational expression of is obtained. Also, because the currents flowing through MOSFETs 24 and 26 are equal The relational expression of is obtained. (208), and _{(209) V 2 = V TPH} -V TPL ......... by solving the equation (210). Therefore, the second reference voltage circuit 27 is
The reference voltage represented by the equation (210) is taken out from the connection point of the FETs 23 and 25. 28 and 29 are operational amplifiers having a very high gain. 30 and 31 are P channel MO
These are SFETs, each of which serves as a resistance control circuit. 32 is a load. P-channel MOSFET 30
And 31 are connected in series with the load 32 as a circuit connected in parallel, and are connected between the power supplies. P Channel M
The connection point between the parallel circuit of the OSFETs 30 and 31 and the load 32 serves as the output terminal 33 of the constant voltage circuit. Operational amplifier 2
The output of the first reference voltage circuit 10 is connected to the inverting input terminal of the second reference signal 8, and the second input terminal of the operational amplifier 29 is connected to the second input.
The output of the reference voltage circuit 27 is connected. The output terminals 33 of the constant voltage circuit are both input to the non-inverting input terminals of the operational amplifiers 28 and 29. The output of the operational amplifier 28 is connected to the gate of the P-channel MOSFET 30,
The output of the operational amplifier 29 is the P channel MOSFET 31.
Is connected to the gate.

Now, in the above circuit configuration, the first reference voltage circuit 1
0, an operational amplifier 28 and a P-channel MOSFET 30 whose equivalent resistance is limited by the gate potential, the potential of the output terminal 33 of the constant voltage circuit is (20
The circuit series composed of the second reference voltage circuit 27, the operational amplifier 29, and the P-channel MOSFET 31 operates in principle so as to maintain the output of the constant voltage circuit. It acts so as to keep the potential of the terminal 33 at a voltage equal to the difference between the threshold voltages represented by the equation (210). By the way, the threshold voltage has a negative temperature characteristic, that is, the threshold voltage decreases as the temperature rises. Therefore, the output V ₀ of the first reference voltage circuit 10 that outputs the sum of the threshold voltages as expressed by the equation (204) has the characteristic shown by the characteristic line 23 in FIG. 7. . Further, the output V ₂ of the second reference voltage circuit 27 which outputs the voltage of the difference between the threshold voltages as expressed by the equation (210) has the temperature characteristic canceled and is indicated by the characteristic line 34 in FIG. 7. It becomes a characteristic.

In FIG. 7, the characteristic line 23 and the characteristic line 34 intersect at a certain temperature, V ₀ > V _{2 at} low temperature, and V ₀ at high temperature.
₂ > V ₀ . Now consider the operation of the circuit of FIG. First, in the low temperature region satisfying V ₀ > V ₂ , when the relation of (i) V _reg <V ₂ <V ₀ is established between the potential V _reg of the constant voltage circuit output terminal 33 and the potential V _reg , both the operational amplifiers 28 and 29 are Since the potential of the inverting input terminal is higher than the potential of the non-inverting input terminal and the gains of the operational amplifiers 28 and 29 are very high, the outputs of the operational amplifiers 28 and 29 are almost -V _SS (0 potential).
And the equivalent resistances of the P-channel MOSFETs 30 and 31 are both reduced, and the potential of the constant voltage circuit output terminal 33 is corrected to be higher.

(ii) When V _reg = V ₂ <V ₀ , the equivalent resistance of the P-channel MOSFET 31 does not change so as to maintain V _reg = V ₂ , but the voltage V _{0 at} the inverting input terminal of the operational amplifier 28 is Since it is higher than the potential V _reg of the non-inverting input terminal, the output of the operational amplifier 28 is almost close to −V _SS , and the P channel MOSFET 30.
Has a smaller equivalent resistance, and acts to increase the potential V _reg of the constant voltage circuit output terminal 33. Here, the equivalent resistance of the P-channel MOSFET 31 is a value that maintains V _reg = V ₂ , and the equivalent resistance of the P-channel MOSFET 30 is V
_The value is such that _reg > V ₂ , but P channel MO
Since the SFETs 30 and 31 are connected in parallel, the P-channel MOSFET 30 operates with priority, and the constant voltage circuit output V _reg becomes higher than V ₂ .

(iii) In the relationship of V ₂ <V _reg <V ₀ , the potential V ₀ of the inverting input terminal is higher than the potential V _reg of the non-inverting input terminal in the operational amplifier 28, so the output of the operational amplifier 28 becomes −V _SS . It becomes closer, and the equivalent resistance of the P-channel MOSFET 30 becomes smaller. On the other hand, in the operational amplifier 29, the potential V ₂ of the inverting input terminal is lower than the potential V _reg of the non-inverting input terminal, so the output of the operational amplifier 29 becomes close to + V _DD , and the P channel MOSF
The equivalent resistance of ET31 becomes large. That is, P channel M
Although the OSFETs 30 and 31 act in the opposite directions, since the P-channel MOSFETs 30 and 31 are in a parallel circuit, the P-channel MOSFET 30 has a reduced equivalent resistance, similar to the ON / OFF priority relationship in the parallel circuit.
Is preferentially corrected, and V _reg is corrected in the higher direction.

(iv) When V ₂ <V _reg = V ₀ , the potential V ₀ of the inverting input terminal is equal to the potential V _reg of the non-inverting input terminal in the operational amplifier 28, so that the equivalent resistance of the P-channel MOSFET 30 is V _reg.
Acts to keep = V ₀ . In the operational amplifier 29, the potential V ₂ of the inverting input terminal is the potential V ₂ of the non-inverting input terminal.
Since it is smaller than _reg , the output of the operational amplifier 29 is + V.
_It becomes close to _DD , and the equivalent resistance of the P-channel MOSFET 31 is very large, and it is practically turned off. _Therefore, it stabilizes at V _reg = V ₀ .

(v) When V ₂ <V ₀ <V _reg , the operational amplifiers 28 and 29 have lower inverting input terminal potentials than non-inverting input terminal potentials.
The outputs of operational amplifiers 28 and 29 are both close to V _DD ,
The equivalent resistances of the P-channel MOSFETs 30 and 31 are both increased, and the constant voltage circuit output potential V _reg is modified to be low.

As described above, when the cases of (i) to (v) are summed up, when V ₀ > V ₂ , it stabilizes at V _reg = V ₀ . That is, it can be seen that the output of the constant voltage circuit is stable at the higher reference voltage. Therefore, as shown in FIG. 7, V ₂ > V ₀ at high temperature.
Then, in this region, the output V _reg of the constant voltage circuit stabilizes at the higher reference voltage V ₂ and V _reg = V ₂ . Therefore, in the case of the circuit of FIG. 6, the constant voltage circuit output V _reg
Since the higher voltage of the output voltage V ₂ of the output voltage V ₀ and the second reference voltage circuit 27 of the first reference voltage circuit 10, will have the characteristics of thick solid line 35 shown in FIG. 8 . The characteristic line 20 in FIGS. 7 and 8 shows the temperature characteristic of the oscillation stop voltage of the oscillation circuit including the circuit of FIG. 3 described above, and the temperature coefficient is between the temperature coefficients of the characteristic lines 23 and 34. Has a value of. Therefore, when the circuit of FIG. 3 is operated by the constant voltage circuit with the reference voltage source having the characteristic line 23, the oscillation stops at high temperature, and the constant voltage circuit with the reference voltage source having the characteristic line 34 When the circuit of FIG. 3 is operated, oscillation stops at a low temperature. Therefore, in the constant voltage circuit of the reference voltage source having one of the characteristic lines 23 or 34, the operation of the circuit of FIG. You cannot be satisfied over a wide temperature range,
Since the constant voltage circuit of FIG. 6 that synthesizes the characteristic lines 23 and 34 has the characteristic line of the thick solid line 35 of FIG. 8, the characteristic line 20 of the oscillation stop voltage should always be exceeded at both low and high temperatures. It can be seen that the constant voltage circuit satisfies the operation of the circuit of FIG. 3 in a wide temperature range. The broken line in FIG. 8 is a part of the characteristic lines 23 and 34 in FIG.

FIG. 9 is a second embodiment of the constant voltage circuit for explaining the present invention. FIG. 6 shows the case where two reference voltage sources are used and two resistance value control circuits are connected in parallel, but FIG. 9 is further expanded to use three reference voltage sources and three reference voltage sources. It is a circuit when the resistance value control circuits of are connected in parallel. In FIG. 9, 39 is a first reference voltage source, 40 is a second reference voltage source, and 41 is a third reference voltage source. 36, 37, 3
8 is an operational amplifier with a very high gain. 42,4
Reference numerals 3 and 44 are P-channel MOSFETs, each of which functions as a resistance value control circuit. 45 is a load. The P-channel MOSFETs 42, 43 and 44 are connected in series with a load 45 as a circuit connected in parallel, and are connected between power sources. P-channel MOSFET 42, 43, 4
The connection point between the parallel circuit 4 and the load 45 serves as the output terminal 46 of the constant voltage circuit. The inverting input terminal of the operational amplifier 36 is connected to the output of the first reference voltage source 39, the inverting input terminal of the operational amplifier 37 is connected to the output of the second reference voltage source 40, and the inverting input terminal of the operational amplifier 38 is connected. Is connected to the output of the third reference voltage source 41. The output terminals 46 of the constant voltage circuits are input to the non-inverting input terminals of the operational amplifiers 36, 37 and 38, respectively. The output of the operational amplifier 36 is connected to the gate of the P-channel MOSFET 42, and the output of the operational amplifier 37 is the P-channel MOSFET 4
3 and the output of the operational amplifier 38 is connected to the gate of the P-channel MOSFET 44.

By the way, the above circuit configuration is merely an extension of the principle of the circuit of FIG. 6, and in the parallel circuit, the principle that the lower equivalent resistance value preferentially operates does not change even in the case of three circuits. The output voltage V _reg of the constant voltage circuit of FIG. 9 is controlled to be the highest voltage among the output voltages of the first, second and third reference voltage sources 39, 40 and 41. Therefore, the tenth
In the figure, a characteristic line 47 is an output voltage characteristic of the first reference voltage source 39, a characteristic line 48 is an output voltage characteristic of the second reference voltage source 40, and a characteristic line 49 is an output voltage characteristic of the third reference voltage source 41. Then, the output voltage V _reg of the constant voltage circuit of FIG.
The characteristic of is a characteristic synthesized as shown by a thick solid line 50 in FIG. The broken line in FIG.
It is a part of the characteristic lines 47, 48 and 49 in the figure.

As described above, in the case of two reference voltage sources in FIG. 6 and the case of three reference voltage sources in FIG. 9, the resistance value is not limited to the number of reference voltage sources. When the control circuits are connected in parallel, the output voltage of the constant voltage circuit has a characteristic obtained by combining the highest values of the plurality of reference voltage sources.

FIG. 12 is a third constant voltage circuit for explaining the present invention.
It is an example of. In the circuits of FIGS. 6 and 9 described above, both the reference voltage source and the output of the constant voltage circuit are based on −V _DD (0 potential), but in FIG. The circuit output is also based on + V _DD . In FIG. 12, 54 is a first reference voltage source based on + V _DD , 55 is a similar second reference voltage source,
Reference numeral 56 is a similar third reference voltage source. 51, 52, 5
3 is an operational amplifier with a very high gain. 57,5
Reference numerals 8 and 59 are N-channel MOSFETs, each of which functions as a resistance control circuit. 60 is a load. The N-channel MOSFETs 57, 58, and 59 are connected in series with a load 60 as a circuit connected in parallel, and are connected between power sources. N-channel MOSFET 57, 58, 5
The connection point between the parallel circuit 9 and the load 60 serves as the output terminal 61 of the constant voltage circuit. The output of the first reference voltage source 54 is connected to the inverting input terminal of the operational amplifier 51, the output of the second reference voltage source 55 is connected to the inverting input terminal of the operational amplifier 52, and the inverting input terminal of the operational amplifier 53 is connected. Is the third
The output of the reference voltage source 56 is connected. The output terminals 61 of the constant voltage circuits are input to the non-inverting input terminals of the operational amplifiers 51, 52 and 53, respectively. The output of the operational amplifier 51 is connected to the gate of the N-channel MOSFET 57, and the output of the operational amplifier 52 is the N-channel MOSFET 57.
58, the output of the operational amplifier 53 is N
It is connected to the gate of the channel MOSFET 59.

The circuit described above, the circuit of Figure 9 from _{-V SS} reference + V
Since only the _DD reference is replaced, the constant voltage circuit output terminal 61 has a characteristic that a voltage having the largest absolute value of the potential difference between the first, second, and third reference voltage sources is combined from the + V _DD side. Is output. Although FIG. 12 shows the case where there are three reference voltage sources, even in the case of such a + V _DD reference constant voltage circuit, the same principle can be used regardless of the number of reference voltage sources.

FIGS. 13 and 14 show an example of the circuit of the reference voltage source based on + V _DD used in the circuit of FIG.
FIG. 13 is a diagram in which the reference voltage source 10 based on −V _SS used in the circuit of FIG. 6 is replaced with a + V _DD reference. In FIG. 13, 62 is a P channel MO
The SFETs 63 and 64 are N-channel MOSFETs. The MOSFETs 62, 63 and 64 are connected in series to connect between the power supplies, and the MOSFETs 62 and 6 are connected.
The connection point of 3 is connected to the gates of MOSFETs 62 and 63, and the connection point of MOSFETs 63 and 64 is connected to MOSFET 6
It is connected to the gate of 4. P-channel MOSFET 6
The β of the 2, N channel MOSFETs 63 and 64 is β _p4 , β _N4 and β _N5 , respectively, and the threshold voltages are V _TP , V _TN and V _TN , respectively. Also, MO
The potential at the connection point between the SFETs 62 and 63 is set to V ₄ , MOSFE
The potential of the connection point of T63 and 64 is set to V _5, and -V _SS
Is 0 potential, and the potential difference between + V _DD and −V _SS is V _DD , the currents flowing through the MOSFETs 62, 63, 64 are equal. And these are solved, However Becomes Therefore, by designing β _N5 << β _p4 β _N5 // β _N4 , the equation (212) becomes V ₅ ≈V _DD −V _TP −V _TN (...) (213). From the equation (213), it can be seen that the circuit of FIG. 13 serves as a reference voltage circuit for extracting the sum of the threshold voltages as the + V _DD reference from the terminal 65.

Also, FIG. 14 shows the -V used in the circuit of FIG.
_The reference voltage source 27 based on _SS is replaced with a + V _DD reference. In FIG. 14, 66 and 67 are P
Channel MOSFET, 68 and 69 are N channel MOS
It is a FET. The sources of the P-channel MOSFETs 66 and 67 are connected to + V _DD , and the N-channel MOSFETs are connected.
The sources of 68 and 69 are connected to -V _SS . P
Drain of channel MOSFET 66 and N channel MO
The drain of SFET 68 is connected. The drain of the P-channel MOSFET 67 and the N-channel MOSFET
The drains of 69 are connected. N channel MOSF
The gate of ET69 is connected to the drain of N-channel MOSFET 69. N-channel MOSFET 68
_Has its gate connected to + V _DD . P Channel MO
The gates of SFETs 66 and 67 are both P channel MOS.
It continues to the drain of the FET 66. Further, β of the N-channel MOSFETs 68 and 69 are both β _N6 , and threshold voltages are V _TNH and V _TNL , respectively.
Β of the P-channel MOSFETs 66 and 67 are both β _p6 ,
Both the threshold voltage is V _TP . Also -V
_{SS is set} to 0 potential, + V _DD and −V _DD are set, and MOS is
The potential at the connection point of the FETs 66 and 68 is V ₆ , MOSFET
The electric potential at the connection point between 67 and 69 is V ₇ . At this time MO
Since the currents flowing through SFETs 66 and 68 are equal Holds. Also, since the currents flowing through the MOSFETs 67 and 69 are equal, Is obtained, and by solving the equations (214) and (215), V ₇ = V _DD − (V _TNH −V _TNL ) ... (2
16). From the equation (216), it can be seen that the circuit shown in FIG. 14 serves as a reference voltage circuit for extracting the voltage of the difference between the threshold voltages from the terminal 70 as the + V _DD reference.

FIG. 15 is a fourth constant voltage circuit for explaining the present invention.
It is an example of. In the circuits of FIG. 6 and FIG. 9, the resistance value control circuits were connected in parallel with each other.
The circuit shown in the figure has resistance value control circuits connected in series. In FIG. 15, 73 is a first reference voltage source, and 74
Is a second reference voltage source. Reference numerals 71 and 72 are operational amplifiers having a very high gain. 75 and 76 are P channels M
These are OSFETs, each of which serves as a resistance value control circuit. Reference numeral 77 is a load. P channel MOSF
The ETs 75 and 76 are connected in series as a circuit, and are further connected in series with a load 77 and are connected between power sources.
P-channel MOSFET 75 and 76 series circuit and load 7
The connection point of 7 serves as the output terminal 78 of the constant voltage circuit. The output of the first reference voltage source 73 is connected to the inverting input terminal of the operational amplifier 71, and the output of the second reference voltage source 74 is connected to the inverting input terminal of the operational amplifier 72. The non-inverting input terminals of the operational amplifiers 71 and 72 are both input to the output terminal 78 of the constant voltage circuit. The output of the operational amplifier 71 is connected to the gate of the P-channel MOSFET 75, and the output of the operational amplifier 72 is the P-channel MOSF.
It is connected to the gate of ET76. Further, with −V _SS as a reference of 0 potential, the output voltage of the first reference voltage source 73 is V ₈ , the output voltage of the second reference voltage source 74 is V _9, and V ₈ and V ₉ are Characteristic line 8 in Fig. 16
It is assumed that there is a temperature characteristic of 0 and the characteristic line 79.

In the above circuit, at low temperature, as shown in FIG. 16, V ₈ <V ₉ and the voltage V at the terminal 78 is V
_In the relationship with _reg (a) when V _reg <V ₈ <V ₉ , the potentials of the inverting input terminals of the operational amplifiers 71 and 72 are both higher than that of the non-inverting input terminal, and the operational amplifiers 71 and 72 have the same potential. Since the gain is very high, the outputs of the operational amplifiers 71 and 72 are close to -V _SS , the equivalent resistance value of the P-channel MOSFETs 75 and 76 is small, and the potential V _{reg of the} constant voltage circuit output terminal 78 is small.
Is modified to be high.

(b) When V _reg = V ₈ <V ₉ , the potentials of the inverting input terminal and the non-inverting input terminal of the operational amplifier 71 are equal, so that the P channel MOS
The FET 75 stabilizes at a value that keeps V _reg = V ₈ . Since the potential of the inverting input terminal of the operational amplifier 72 is higher than the potential of the non-inverting input terminal, the output of the operational amplifier 72 is -V _SS.
When saturated, the P-channel MOSFET 76 saturates and stabilizes at the lowest equivalent resistance value. Therefore, V _reg = V ₈
Stabilizes at.

(c) In the relationship of V ₈ <V _reg <V ₉ , the potential of the inverting input terminal of the operational amplifier 71 is lower than the potential of the non-inverting input terminal, so the output of the operational amplifier 71 becomes a value close to + V _DD , The equivalent resistance value of the P-channel MOSFET 75 becomes so large that it acts to lower the potential V _reg of the constant voltage circuit output terminal 78. Since the potential of the inverting input terminal of the operational amplifier 72 is higher than the potential of the non-inverting input terminal, the output of the operational amplifier 72 has a value close to −V _SS , and the P channel MOSF
The equivalent resistance value of ET76 reaches the minimum value. Therefore, the P channel MOSFET 75 is turned off,
Although the P-channel MOSFET 76 is turned on and the equivalent resistance value is lowered, since the MOSFETs 75 and 76 are connected in series, the function of the OFF side has priority and the potential V _reg of the constant voltage circuit output terminal 78 becomes low. Will be corrected to.

(d) When V ₈ <V _reg = V ₉ , the potential of the inverting input terminal of the operational amplifier 71 is lower than the potential of the non-inverting input terminal of the operational amplifier 71.
The output of 1 becomes a value close to + V _DD , and P channel M
The equivalent resistance value of the OSFET 75 becomes so large that it acts to lower the constant voltage circuit output V _reg . Further, since the potential of the inverting input terminal of the operational amplifier 72 and the potential of the non-inverting input terminal are equal, the equivalent resistance value of the P channel MOSFET 76 has a value such that V _reg = V ₉ is maintained.
Since the SFETs 75 and 76 are connected in series,
The action of the FF is prioritized, and the potential V _reg of the constant voltage circuit output terminal 78 is corrected to be low.

(e) When V ₈ <V ₉ <V _reg , the operational amplifiers 71 and 72 both have an inverting input terminal potential lower than the non-inverting input terminal potential, and therefore the operational amplifiers 71 and 72 both output + V. _It becomes close to _DD , and the equivalent resistance value of the P-channel MOSFETs 75 and 76 becomes very large, and the constant voltage circuit output voltage V _reg is increased.
Is modified to be lower.

As described above, when the cases (a) to (e) are summed up, when V ₈ <V ₉ , V _reg = V ₈ is stable. That is, it is understood that when the resistance value control circuits are connected in series, the output of the constant voltage circuit is stable at the lower reference voltage. Therefore, as shown in FIG. 16, conversely at high temperature, V ₉ <V ₈
In this case, the lower reference voltage V ₉ stabilizes and V
_reg = V ₉ . If the although the circuit of the connexion FIG. 15, the output V _reg of the constant voltage circuit, lower voltage of the output voltage V ₉ of the output voltage V ₈ and the second reference voltage circuit 74 of the first reference voltage circuit 73 Therefore, the characteristic of the thick solid line 81 shown in FIG. 17 is obtained. The broken line in FIG. 17 is a part of the characteristic lines 79 and 80 in FIG.

FIG. 18 is a fifth constant voltage circuit for explaining the present invention.
It is an example of. FIG. 15 shows the case where two reference voltage sources are used and two resistance value control circuits are connected in series, but FIG. 18 is further expanded to use three reference voltage sources. This is a circuit when three resistance value control circuits are connected in series. In FIG. 18, 85 is a first reference voltage source and 86
Is a second reference voltage source, and 87 is a first reference voltage source.
Reference numerals 82, 83 and 84 are operational amplifiers having a very high gain. Reference numerals 88, 89 and 90 denote P-channel MOSFETs, each of which serves as a resistance control circuit. 91 is a load. The P-channel MOSFETs 88, 89 and 90 are
The circuit connected in series is connected in series to the load 91 and is connected between the power supplies. P-channel MOSFET
A connection point between the series circuit of 88, 89 and 90 and the load 91 serves as an output terminal 92 of the constant voltage circuit. Operational amplifier 82
Is connected to the output of the first reference voltage source 85, the inverting input terminal of the operational amplifier 83 is connected to the output of the second reference voltage source 86, and the inverting input terminal of the operational amplifier 84 is connected to , The output of the third reference voltage source 87 is connected. The constant voltage circuit output terminal 92 is input to the non-inverting input terminals of the operational amplifiers 82, 83, 84. The output of the operational amplifier 82 is connected to the gate of the P-channel MOSFET 88, the output of the operational amplifier 83 is connected to the gate of the P-channel MOSFET 89, and the operational amplifier 84.
Is connected to the gate of the P-channel MOSFET 90.

Now, the above circuit configuration is merely an extension of the principle of the circuit of FIG. 15, and in the series circuit, the principle that the higher equivalent resistance value is preferentially operated does not change even in the case of three circuits. The output voltage V _reg of the constant voltage circuit of FIG.
The output voltage of the first, second, and third reference voltage sources 85, 86, 87 is controlled to the lowest voltage. Therefore, in FIG. 19, the characteristic line 93 is the output voltage characteristic of the first reference voltage source 85, the characteristic line 94 is the output voltage characteristic of the second reference voltage source 86, and the characteristic line 95 is the third reference voltage source 87. The output voltage V _reg of the constant voltage circuit of FIG. 18 has a combined characteristic as shown by the thick solid line 96 in FIG. The broken line in FIG. 20 is a part of the characteristic lines 93, 94 and 95 in FIG.

As described above, in FIG. 15, in the case of two reference power sources, the first
Although FIG. 8 describes the case of three reference voltage sources, in general, no matter how many reference voltage sources are used, if the resistance value control circuit is connected in series, the output voltage of the constant voltage circuit becomes plural. The lowest value of the reference voltage source is the combined characteristic.

FIG. 21 is a sixth constant voltage circuit for explaining the present invention.
It is an example of. In the circuits of FIGS. 15 and 18 described above, both the reference voltage source and the constant voltage circuit output are -V _SS (0
The reference voltage source and the constant voltage circuit are based on + V _DD in FIG. 21. In FIG. 21, 100 is a first reference voltage source based on + V _DD , 101 is a similar second reference voltage source, and 102 is a similar third reference voltage source. 97,
Reference numerals 98 and 99 are operational amplifiers having a very high gain.
Reference numerals 103, 104, and 105 denote N-channel MOSFETs, each of which functions as a resistance value control circuit. 106
Is the load. N-channel MOSFETs 103 and 104
And 105 are connected in series to form a load 106.
Is connected in series and is connected between the power supplies. The connection point between the series circuit of the N-channel MOSFETs 103, 104 and 105 and the load 106 serves as the output terminal 107 of the constant voltage circuit. The output of the first reference voltage source 100 is connected to the inverting input terminal of the operational amplifier 97, the output of the second reference voltage source 101 is connected to the inverting input terminal of the operational amplifier 98, and the inverting input terminal of the operational amplifier 99 is connected. Is connected to the output of the third reference voltage source 102. Operational amplifier 97, 9
The output terminals 107 of the constant voltage circuit are both input to the non-inverting input terminals of 8, 99. The output of the operational amplifier 97 is
The output of the operational amplifier 98 is connected to the gate of the N-channel MOSFET 103, the output of the operational amplifier 98 is connected to the gate of the N-channel MOSFET 104, and the output of the operational amplifier 99 is connected to the gate of the N-channel MOSFET 105.

The circuit described above is merely the circuit of FIG. 18 converted to the −V _SS reference, so that the constant voltage circuit output terminal 107 has + V.
_{From the DD} side, the voltage having the smallest absolute value of the voltage difference between the first, second, and third reference voltage sources is output as a combined characteristic. Note that FIG. 21 shows the case where there are three reference voltage sources, but even in the case of such a + V _DD reference constant voltage circuit, the reference voltage source is constructed by the same principle no matter how many cases. It goes without saying that you can do it.

FIG. 22 shows a first embodiment of the circuit of the present invention. When three reference voltage sources are used, the resistance value control circuits are all connected in parallel in the circuit of FIG. 9, and all of them are connected in series in the circuit of FIG. However, FIG. 22 is a circuit in which a circuit in which two resistance value control circuits are connected in series is connected in parallel with the remaining one resistance value control circuit. In FIG. 22, 39 is a first reference voltage source,
40 is a second reference voltage source and 41 is a third reference voltage source. Reference numerals 108, 109, and 110 are operational amplifiers having a very high gain. Reference numerals 111, 112 and 113 are P-channel MOSFETs, each of which serves as a resistance control circuit. 114 is a load. P channel MOSF
The ETs 111 and 112 are connected in parallel with the P-channel MOSFET 113 in a circuit connected in series. The P channel MOSFETs 111, 112, 11
The circuit constituted by 3 and the load 114 are connected in series and are connected between the power sources. P-channel MOSFET
The connection point between the circuit constituted by 111, 112 and 113 and the load 114 serves as the output terminal 115 of the constant voltage circuit. The inverting input terminal of the operational amplifier 108 is connected to the output of the first reference voltage source 39, the inverting input terminal of the operational amplifier 109 is connected to the output of the second reference voltage source 40, and the inverting input terminal of the operational amplifier 110 is connected. Is connected to the output of the third reference voltage source 41. Operational amplifier 108,
The constant voltage circuit output terminal 115 is input to both non-inverting input terminals of 109 and 110. The output of the operational amplifier 108 is connected to the gate of the P-channel MOSFET 111, and the output of the operational amplifier 109 is the P-channel MOSFET.
The output of the operational amplifier 110 is connected to the gate of the P-channel MOSFET 113.

Now, in the above circuit, it is assumed that the first, second and third reference voltage sources in FIG. 22 are equal to the characteristics of the first, second and third reference voltage sources in FIG. Assuming that the characteristics of the first, second, and third reference voltage sources correspond to the characteristic lines 47, 48, and 49 in FIG. 10, respectively, the higher one is obtained when the resistance value control circuits are in parallel according to the above description. 22. Since the lower reference voltage becomes dominant in the case of series, the output voltage characteristic of FIG. 22 becomes like the characteristic of the thick solid line 116 of FIG. Note that in FIG. 23, the broken lines are the characteristic lines 47, 48, 4 in FIG.
9 shows a part of 9.

FIG. 24 shows a second embodiment of the circuit of the present invention. Second
4 has the same configuration as that of FIG. 22 as a circuit, but in FIG. 22, the first reference voltage source 39 having the characteristic of the characteristic line 47 in FIG. 10 has a resistance value of a serial configuration. The third reference voltage source 41 having the characteristic of the characteristic line 49 acts as a reference for controlling the control circuit 111 and as a reference for controlling the resistance value control circuit 113 having the parallel configuration. In the figure, the first reference voltage source 39 having the characteristic of the characteristic line 47 is used as a reference for controlling the resistance value control circuit 120 in the parallel configuration, and the third reference voltage source having the characteristic of the characteristic line 49 is used. Source 41 is configured to act as a reference for controlling resistance control circuit 122 in a series configuration. That is, the circuits of FIGS. 22 and 24 are essentially the same, but the reference voltage source used as an example is replaced with that of FIGS. 22 and 24. In FIG. 24, reference voltage sources 39, 4
0 and 41 are characteristic lines 47 and 4 in FIG. 10, respectively.
With the output characteristics of 8, 49, the higher reference voltage is dominant when the resistance value control circuit is in parallel, and the lower reference voltage is dominant when the resistance value control circuit is in series. The voltage circuit output has the characteristic indicated by the thick solid line 125 in FIG. Note that in FIG. 25, the broken line shows a part of the characteristic lines 47, 48, 49 in FIG.

FIG. 26 shows a third embodiment of the circuit of the present invention. In the case where three reference voltage sources are used, the resistance value control circuit is connected in series or in parallel, or a combination thereof is used.
As shown in FIGS. 18, 18 and 22, FIG. 26 shows a case where a circuit in which two resistance value control circuits are connected in parallel is connected in series with the remaining one resistance value control circuit. Circuit.
In FIG. 26, 39 is a first reference voltage source, 40 is a second reference voltage source, and 41 is a third reference voltage source. 12
Reference numerals 6, 127 and 128 are operational amplifiers having a very high gain. 129, 130, 131 are P-channel MOSF
ET, each of which serves as a resistance control circuit. 132 is a load. P-channel MOSFET 12
9 and 131 are connected in series with the P-channel MOSFET 130 as a circuit connected in parallel. The P
The circuit constituted by the channel MOSFETs 129 and 131 and the load 132 are connected in series and connected between the power supplies. P-channel MOSFETs 129, 130 and 1
The connection point of the circuit constituted by 31 and the load 132 serves as the output terminal 133 of the constant voltage circuit. The output of the first reference voltage source 39 is connected to the inverting input terminal of the operational amplifier 126, and the second input is connected to the inverting input terminal of the operational amplifier 127.
The output of the reference voltage source 40 of
The output of the third reference voltage source 41 is connected to the inverting input terminal of. The constant voltage circuit output terminal 133 is input to the non-inverting input terminals of the operational amplifiers 126, 127, and 128. The output of the operational amplifier 126 is the P channel MO.
Connected to the gate of SFET129, operational amplifier 127
Is connected to the gate of the P-channel MOSFET 130, and the output of the operational amplifier 128 is the P-channel MOSF.
It is connected to the gate of ET131.

In the above circuit, assuming that the characteristics of the first, second, and third reference voltage sources in FIG. 26 correspond to the characteristic lines 47, 48, 49 in FIG. 10, respectively, the resistance value control circuits are in parallel. In the case of, the higher reference voltage source dominates, and in the case of a series, the lower reference voltage dominates, and the constant voltage circuit output of FIG. 26 has the characteristics of the thick solid line 134 of FIG. Become. Note that in FIG. 27, the broken line shows a part of the characteristic lines 47, 48, 49 in FIG.

Now, in the circuits of FIGS. 9, 22, 24, and 26, three reference voltage sources each having three characteristic lines shown in FIG. By changing the series-parallel combination of the resistance value control circuits to be controlled respectively, FIG. 11, FIG. 23, and FIG.
As shown in FIG. 27 and FIG. 27, it can be seen that the output characteristics of the constant voltage circuit can be variously changed. Therefore, in general, when it is not possible to obtain a constant voltage circuit with a target characteristic by one reference voltage source, a plurality of different reference voltage sources each having a part of or close to the target characteristic are used, By variously combining the series and parallel of the resistance value control circuits controlled by each, the characteristics can be freely combined to obtain the constant voltage circuit having the desired characteristics.

In the circuit described above, the circuit in the case where the output voltage of the reference voltage source and the output voltage of the constant voltage circuit are the same has been described. FIG. 28 shows the output voltage of the reference voltage source and the output of the constant voltage circuit. This is a circuit when the voltages are not necessarily equal. In the circuit of FIG. 28, 135 and 137 are P-channel MOSFETs, 136 and 138 are N-channel MOSFETs, and MOSFETs 135, 136 and 136.
A reference voltage circuit 139 is configured by 137 and 138. 140 is an operational amplifier with a very high gain. Reference numeral 141 denotes a P-channel MOSFET, which serves as a resistance value control circuit. 142 is a load. P-channel MOSFET 135 and N-channel MOSFET 13
6 is connected in series and is connected between power supplies. P-channel MOSFET 135 and N-channel MOSFET 13
The gates of 6 are both P-channel MOSFET 135 and N.
It is connected to the connection point of the channel MOSFET 136. P-channel MOSFET 141 and P-channel MOS
The FET 137 and the N-channel MOSFET 138 are connected in series and connected between the power supplies. MOSFET 13
The gates of 7 and 138 are both MOSFETs 137 and 13
8 connection points. The inverting input terminal of the operational amplifier 140 is connected to the connection point of the MOSFETs 135 and 136, and the non-inverting input terminal thereof is the MOSFETs 137 and 138.
Is connected to the connection point of. The output of the operational amplifier 140 is connected to the gate of the P-channel MOSFET 141. The connection point between the P-channel MOSFETs 141 and 137 becomes the constant voltage circuit output terminal 143, and the load 142 is connected between the constant voltage circuit output terminal 143 and -V _SS . Here, the MOSFETs 135, 136, 137, 13
8 β is β _P10 , β _N10 , β _P11 , β
_N11 and threshold voltages are V _TP , V _TN , V _TP and V _TN , respectively. MOSFET
The potential of the connection point of 135 and 136 is set to V ₁₀ , and the MOSF
The potential at the connection point between ET137 and 138 is V ₁₁ . Further, −V _SS is 0 potential, the potential difference between + V _DD and −V _SS is V _DD, and the potential of the constant voltage circuit output terminal 143 is V _DD.
reg . At this time, the currents flowing through the MOSFETs 135 and 136 are equal, There is a relationship of However Becomes If we design β _P10 << β _N10 (21
The expression 8) is V ₁₀ ≈V _TN (...) (219). Also, since the currents flowing through the MOSFETs 137 and 138 are equal, There is a relationship of Becomes Since the gain of the operational amplifier 140 is very high, V ₁₀ = V ₁₁ (222) at the stable point. Therefore, (219), (221), (22
According to the formula 2), V _reg = V _TP + V _TN (223) Therefore, in the circuit of FIG. 28, the voltages V ₁₀ and V ₁₁ output from the reference voltage source 139 are both approximately V _TN , while the constant voltage circuit output is (V _TP + V _TN ) And that there is such a circuit.

Now, referring to FIG. 29, a first reference voltage source 139, an operational amplifier 140, and a P channel MOS as a resistance value control circuit.
The FET 141 is a circuit in which the output voltage of the reference voltage source described in FIG. 28 and the constant voltage circuit output are not necessarily the same. In addition, the second reference voltage source 144 and the operational amplifier 145
And a P-channel MOSFET 14 as a resistance control circuit
Reference numeral 6 is a circuit which outputs a constant voltage circuit output which is the same as the voltage of the reference voltage source shown in FIGS. 6 and 9 described in FIG. In FIG. 29, 147 is a load,
Reference numeral 48 is a constant voltage circuit output terminal. Now, assuming that the output voltage of the second reference voltage source is V ₁₂ , the resistance control circuit 141
And 146 are connected in parallel, so (V _TP + V
_The one with the larger value of _TN ) and V ₁₂ is output alone or as a composite. In other words, the combination of the characteristics of the plurality of reference voltage sources is not limited to the circuit in which the output voltage of the reference voltage source and the output voltage of the constant voltage circuit are equal to each other. In this case, the characteristics can be combined.

As described above, according to the present invention, a plurality of FETs are connected between the power source and the constant voltage output terminal, and a plurality of these F
By connecting ET in series and in parallel in an arbitrary combination according to the temperature characteristics of the corresponding reference voltage source, there is an effect that a constant voltage having an arbitrary temperature characteristic can be output from the constant voltage output terminal.

In particular, according to the present invention, by selecting the connection of the FETs in parallel or in series, a higher reference voltage or a lower reference voltage can be arbitrarily selected from a plurality of reference voltage sources having different temperature characteristics. Can be selected to generate a constant voltage having a desired temperature characteristic.

[Brief description of drawings]

1 and 2 are circuit diagrams showing examples of conventional constant voltage circuits,
FIG. 3 is a circuit diagram showing an example of the load, and FIGS. 4 and 5 are
FIG. 6 is a circuit diagram showing temperature characteristics of a constant voltage circuit output voltage and oscillation stop voltage, FIG. 6 is a circuit diagram showing a first embodiment of a constant voltage circuit for explaining the present invention, and FIG. 7 is a circuit diagram of FIG. The temperature characteristic of the reference voltage source used and the temperature characteristic of the oscillation stop voltage of the circuit of FIG. 3 are shown. FIG. 8 is the temperature characteristic of the output voltage of the constant voltage circuit of FIG. FIG. 9 is a diagram showing a temperature characteristic of an oscillation stop voltage of the circuit, FIG. 9 is a circuit diagram showing a second embodiment of a constant voltage circuit for explaining the present invention, and FIG. 10 is a reference voltage used in the circuit of FIG. Figure 11 shows the temperature characteristics of the source,
FIG. 9 is a diagram showing the temperature characteristics of the output voltage of the constant voltage circuit of FIG. 9, FIG. 12 is a circuit diagram showing a third embodiment of the constant voltage circuit for explaining the present invention, and FIGS. 13 and 14 are + V. FIG. 15 is a circuit diagram showing an example of a reference voltage source based on _DD , FIG. 15 is a circuit diagram showing a fourth embodiment of a constant voltage circuit for explaining the present invention, and FIG.
6 shows the temperature characteristics of the reference voltage source used in the circuit of FIG. 15, FIG. 17 shows the temperature characteristics of the output voltage of the constant voltage circuit of FIG. 15, and FIG. 18 explains the present invention. FIG. 19 is a circuit diagram showing a fifth embodiment of a constant voltage circuit for operating the circuit, FIG. 19 is a diagram showing temperature characteristics of a reference voltage source used in the circuit of FIG.
18 is a diagram showing the temperature characteristics of the output voltage of the constant voltage circuit shown in FIG. 18, FIG. 21 is a circuit diagram showing a sixth embodiment of the constant voltage circuit for explaining the present invention, and FIG. 22 is a diagram showing the present invention. FIG. 23 is a circuit diagram showing one embodiment, FIG. 23 is a diagram showing temperature characteristics of output voltage of the constant voltage circuit of FIG. 22, FIG. 24 is a diagram showing a second embodiment of the present invention, and FIG. The figure which shows the temperature characteristic of the output voltage of the constant voltage circuit of the figure, FIG. 26 is the circuit diagram which shows 3rd Example of this invention, FIG. 27 shows the temperature characteristic of the output voltage of the constant voltage circuit of FIG. FIG. 28 is a circuit diagram showing a third example of a conventional constant voltage circuit, and FIG. 29 is a circuit diagram showing a fourth example of the present invention. 1, 6, 28, 29, 36, 37, 38, 51, 52,
53, 71, 72, 82, 83, 84, 97, 98, 9
9, 108, 109, 110, 117, 118, 11
9, 126, 127, 128, 140, 145 ... Operational amplifier 2 ... Zener diode 3, 17 ... Resistor 4, 10, 27, 39, 40, 41, 54, 55, 5
6, 73, 74, 85, 86, 87, 100, 101,
102, 139, 144 ... Reference voltage source 5, 13, 18, 19, 33, 46, 61, 65, 7
0,78,92,107,115,124,133,1
43,148 ... Terminals 7,8,14,23,24,62,66,67,13
5,137 ... P channel MOSFET 9, 15, 25, 26, 63, 64, 68, 69, 13
6,138 ... N channel MOSFET 11, 30, 31, 42, 43, 44, 75, 76, 8
8, 89, 90, 111, 112, 113, 120, 1
21,122,129,130,131,141,14
6 ... P-channel MOSFET 57, 58, 59, 103, 104, 105 as resistance value control circuit ... N-channel MOSFET 12, 32, 45, 60, 77, 91, 106, 11 as resistance value control circuit
4,123,132,142,147 ... Load 16 ... Capacitor

Claims (1)

[Claims] 1. At least three reference voltage sources having different temperature characteristics, and a reference voltage output from the corresponding reference voltage source is input to a first input terminal, and the output voltage of the constant voltage output terminal or this output voltage A plurality of operational amplifiers, each of which has a voltage having a predetermined relationship input to the second input terminal, and a plurality of FEs, which are connected between the power supply and the constant voltage output terminal and whose resistance value is controlled by the output voltage of the corresponding operational amplifier.
T includes, and the plurality of FETs are connected in series and in parallel in any combination according to the temperature characteristics of the corresponding reference voltage source, and output a constant voltage having an arbitrary temperature characteristic from the constant voltage output terminal. A constant voltage circuit characterized by: