JP2021506006A - Programmable Temperature Coefficient Analog Secondary Curvature Compensation Voltage Reference and Voltage Reference Circuit Trimming Method - Google Patents

Abstract

The illustrated voltage reference circuit is configured to generate a temperature proportional current and a corresponding first control voltage, a first circuit (308), and a temperature compensating current and a corresponding second control voltage. The reference circuit (202) including the second circuit (316) configured in the above, and the first current source (5141) coupled to the first load circuit (512), the first current source is In response to the first control voltage and the second control voltage, the sum of the temperature proportional current and the temperature compensation current is generated, and the first load circuit generates a zero temperature coefficient (Tempco) voltage from the sum current. , A first current source (5141) and a second current source (7151) coupled to a second load circuit (718, 720), the second current source being the first control voltage and A second current source that, in response to the second control voltage, produces a sum of the temperature proportional current and the temperature compensating current, and the second load circuit produces a negative Tempco voltage from the sum current and the temperature compensating current. 7151) and. [Selection diagram] Fig. 2

Description

The examples of the present disclosure generally relate to electronic circuits, in particular to programmable temperature coefficient analog secondary curvature compensation voltage references, and trimming techniques for voltage reference circuits.

Precision voltage reference is an important block in integrated circuits (ICs) such as system-on-chip (SoC) ICs. Voltage references are needed for a variety of purposes, such as analog-to-digital converters (ADCs) and power management. Temperature-dependent voltage generation is also useful in some applications, such as to compensate for temperature effects on circuits. Thus, different circuits in an IC require a voltage reference with a different temperature coefficient (eg, ADCs use a temperature-independent voltage reference, whereas other circuits, such as switches, use a temperature-dependent voltage reference. To do). In addition, circuits for generating voltage reference typically use bipolar junction transistors (BJTs). However, BJTs are parasitic elements in complementary metal oxide semiconductor (CMOS) processes used to make ICs. The higher the CMOS technology, the lower the BJT performance, which is caused by digital logic. Therefore, it is desirable to compensate for the quadratic curvature introduced by the BJT while providing a voltage reference circuit capable of generating a flexible temperature coefficient voltage.

A technique for providing a programmable temperature coefficient analog secondary curvature compensated voltage reference will be described. In one example, the voltage reference circuit is configured to generate a first circuit configured to generate a temperature proportional current and a corresponding first control voltage, and a temperature compensating current and a corresponding second control voltage. A reference circuit including a second circuit to be generated, and a first current source coupled to the first load circuit, the first current source responding to a first control voltage and a second control voltage. Then, the sum current of the temperature proportional current and the temperature compensation current is generated, and the first load circuit generates a zero temperature coefficient (Tempco) voltage from the sum current, in the first current source and the second load circuit. A second source of current to be coupled, the second current source produces a sum current of temperature proportional current and temperature compensation current in response to the first control voltage and the second control voltage. The load circuit of 2 includes a second current source, which produces a negative Tempco voltage from the sum current and the temperature compensation current.

In one example, an integrated circuit includes one or more circuits and a voltage reference circuit that supplies at least one voltage to the one or more circuits. The voltage reference circuit is configured to generate a temperature proportional current and a corresponding first control voltage, and a temperature compensating current and a corresponding second control voltage. A reference circuit including two circuits and a first current source coupled to the first load circuit, the first current source responding to a first control voltage and a second control voltage. The first load circuit is coupled to the first current source and the second load circuit, which produces the sum of the temperature proportional current and the temperature compensation current and generates the zero temperature coefficient (Tempco) voltage from the sum current. A second current source, the second current source, in response to the first control voltage and the second control voltage, generates a sum current of the temperature proportional current and the temperature compensation current, and the second load. The circuit includes a second current source, which produces a negative Tempco voltage from the sum current and the temperature compensation current.

In another example, the method of generating the voltage reference is to generate the temperature proportional current and the corresponding first control voltage in the first circuit of the reference circuit, and the temperature compensation current and in the second circuit of the reference circuit. Generating the corresponding second control voltage and generating the sum of the temperature proportional current and the temperature compensation current in the first current source in response to the first control voltage and the second control voltage. , Generating a zero temperature coefficient (Tempco) voltage from the sum current in the first load circuit coupled to the first current source, and in response to the first and second control voltages, the second To generate the sum of the temperature proportional current and the temperature compensation current in the current source of, and to generate the negative Tempco voltage from the sum current and the temperature compensation current in the second load circuit coupled to the second current source. And, including.

The trimming method of the voltage reference circuit will be described. In one example, the method of trimming a voltage reference in an integrated circuit (IC) produces a temperature proportional current and a corresponding first control voltage, and a temperature compensation current and a corresponding second control voltage at a first temperature. Arranging the first plurality of trim cords for the voltage reference reference circuit configured as described above, and the voltage reference voltage output for each of the first plurality of trim cords in order to obtain the first voltage output value. To measure, to arrange the second plurality of trim cords for the reference circuit at the second temperature, and to obtain the second voltage output value of the voltage reference for each of the second plurality of trim cords. It includes measuring the voltage output and selecting a trim code for the reference circuit based on the first voltage output value and the second voltage output value.

In another example, the device for trimming the voltage reference in the integrated circuit (IC) is the memory and the temperature proportional current and the corresponding first control voltage at the first temperature, and the temperature compensation current and the corresponding first. Arrange the first plurality of trim cords for the reference circuit of the voltage reference configured to generate the control voltage of 2, and the voltage for each of the first plurality of trim cords to obtain the first voltage output value. The reference voltage output is measured, the second plurality of trim cords for the reference circuit are arranged at the second temperature, and the voltage reference for each of the second plurality of trim cords is obtained in order to obtain the second voltage output value. A processor configured to execute a memory-stored code to measure the voltage output of and select a trim code for the reference circuit based on the first voltage output value and the second voltage output value. including.

These and other aspects can be understood with reference to the detailed description below.

A more detailed description briefly summarized above can be provided by reference to the exemplary implementations so that the above features can be understood in detail, some of these implementations in the accompanying drawings. It is shown. However, it should be noted that the accompanying drawings are not considered to limit this scope, as they merely show typical exemplary implementations.

It is a block diagram which shows the integrated circuit (IC) by an example. It is a block diagram which shows the voltage reference circuit by an example. It is a schematic diagram which shows the reference circuit by an example. It is a schematic diagram which shows the rudder resistor by an example. It is a schematic diagram which shows the zero temperature coefficient (Tempco) circuit by an example. It is a schematic diagram which shows the curvature correction circuit by an example. FIG. 5 is a schematic diagram showing another portion of the zero Tempco circuit of FIG. 5A, by way of example. It is a graph which shows the dependence of a reference voltage on a temperature. It is a schematic diagram which shows the negative Tempco circuit by an example. It is a schematic diagram which shows the positive Tempco circuit by an example. It is a flow figure which shows the method of generating the voltage reference by an example. It is a block diagram which shows the test system by an example. It is a blow figure which shows the method of setting the trim code in the voltage reference circuit by an example. FIG. 1200 is a graph 1200 showing flat trim codes for output voltages at different temperatures, by way of example. FIG. 1201 shows a reference trim code for an output voltage at a particular temperature by way of example. It is a flow chart which shows the method of setting the trim code in the voltage reference circuit by another example. It is a graph which shows the measurement of the reference trim code at two different temperatures by one example. It is a graph which shows the lookup of the flat trim code by an example. By way of example, it is a block diagram showing a programmable IC in which the voltage reference circuit described herein can be used. It is a figure which shows the field programmable gate array (FPGA) mounting form of the programmable IC of FIG.

For ease of understanding, where possible, the same reference numerals are used to specify the same elements that are common to the figures. It is conceivable that the elements of one example can be beneficially incorporated into another.

The various features will be described below with reference to the figures. It should be noted that the figure may or may not be drawn on a constant scale and elements of similar structure or function are represented by similar reference numerals throughout the figure. It should be noted that the figures are only intended to facilitate the description of the features. These features are not intended to be a comprehensive description of the claimed invention, nor are they intended to limit the scope of the claimed invention. Moreover, the examples shown need not have all of the aspects or advantages shown. The embodiments or benefits described in conjunction with a particular example are not necessarily limited to that example and can be practiced in any other example, whether not so indicated or expressly described. Is.

FIG. 1 is a block diagram showing an integrated circuit (IC) 100 according to an example. The IC 100 includes a voltage reference circuit 200, a control circuit 114, and a circuit 102. Voltage reference circuit 200 includes a supply node 110 supplies a voltage _{V CC,} ground voltage (e.g., 0 volts) is coupled between the ground node 112 for supplying. Voltage _{V CC} is, IC 100 within or on either outside of the IC 100, may be provided by (not shown) voltage supply. The voltage reference circuit 200 is coupled to one or more of the circuits 102 by one or more nodes 104, each of which supplies a zero temperature coefficient (Tempco) voltage. The voltage reference circuit 200 is coupled to one or more of the circuits 102 by one or more nodes 106, each of which supplies a negative Tempco voltage. The voltage reference circuit 200 is coupled to one or more of the circuits 102 by one or more nodes 108, each of which supplies a positive Tempco voltage. Thus, the voltage reference circuit 200 produces a zero Tempco voltage, a negative Tempco voltage, and a positive Tempco voltage. The control circuit 114 supplies a control signal to the voltage reference circuit 200 to trim the voltage and / or current, as described in detail below.

FIG. 2 is a block diagram showing a voltage reference circuit 200 according to an example. The voltage reference circuit 200 includes a reference circuit 202, a zero Tempco circuit 204, a negative Tempco circuit 206, and a positive Tempco circuit 208. Node 210 couples one output of reference circuit 202 to each of Tempco circuits 204 ... 208. Node 212 couples another output of reference circuit 202 to each of Tempco circuits 204 ... 208. Nodes 210 and 212 supply control voltages to Tempco circuits 204 ... 208. The reference circuit 202 generates a temperature proportional current (referred to as Iptat) and a temperature compensation current (referred to as Ictat), as will be further described later. The control voltage for the nodes 210 and 212 controls the current source in the Tempco circuits 204 ... 208 to mirror the currents Iptat and Ictat. The zero Tempco circuit 204 converts the zero Tempco current Iztat (Iztat = Iptat + Ictat) into one or more zero Tempco voltages at the node 104. The negative Tempco circuit 206 converts the current Iztat into one or more negative Tempco voltages at the node 106. The positive Tempco circuit 208 converts the current Iztat into one or more positive Tempco voltages at node 108.

FIG. 3 is a schematic diagram showing a reference circuit 202 according to an example. The reference circuit 202 includes p-channel FETs 302, 304, and 306, such as p-type metal oxide semiconductor field effect transistors (FETs) (MOSFETs). The p-channel FET is an FET that uses holes as a majority carrier for transmitting this channel current. The reference circuit 202 further includes an operational amplifier 308, an operational amplifier 316, a multiplexer 320, a resistor 310, a ladder resistor 318, a bipolar junction transistor (BJT) 312, and a BJT 314. BJT 312 and 314 are PNP transistors.

The source of the FET302 _is coupled to the supply node 110 to _{V CC.} The drain of the FET 302 is coupled to the node 324. The gate of the FET302 is coupled to supply node 210 of the control voltage _{V P.} The source of the FET 304 is coupled to the node 110. The drain of the FET 304 is coupled to the node 326. The gate of the FET 304 is coupled to the node 210. The source of FET 306 is coupled to node 110. The gate of the FET306 is coupled to supply node 212 of the control voltage _{V C.} The drain of the FET 306 is coupled to the node 330. A ladder resistor 318 with full resistance R2 is coupled between node 330 and ground node 112.

FIG. 4 is a schematic view showing a ladder resistor 400 according to an example. The ladder resistor 400 can be used as a ladder resistor 318, or any other ladder resistor described herein. The ladder resistor 400 includes a resistor string 408, such as resistors 408 ₁ ... 408 _K , where K is an integer greater than 1. Resistors 408 ₁ ... 408 _K are coupled in series between node 410 and node 412. The ladder resistor 400 further includes a multiplexer 402. The input of the multiplexer 402 is coupled to a plurality of taps, for example, taps 404 ₁ ... 404 _J , where J is an integer greater than 1. Each tap 404 ₁ ... 404 _J is coupled to a corresponding node of resistance string 408, where resistance string 408 comprises one or more resistors between each node pair. The multiplexer 402 includes a control input 414 for receiving a signal Ctrl that selects one of the taps 404. The signal Ctrl is a digital signal having a sealing [log ₂ (J)] bit. The multiplexer 402 contains an output coupled to node 406. The rudder resistor 400 provides an effective resistance R between node 406 (shown by an imaginary line for illustration purposes) and node 412, which depends on the code value of the Ctrl signal.

Referring to FIG. 3, the node 328 is coupled to the selected tap of the rudder resistor 318 based on the value of the flat trim cord. Thus, the ladder resistor 318 is effectively divided into resistor 318 ₂ between the resistor 318 ₁ between node 330 and node 328, and a node 328 and ground node 112. The resistor 318 ₁ has a value R2'and the resistor 318 ₂ has a value R2'.

The inverting input of the operational amplifier 308 is coupled to node 324. The non-inverting input of the operational amplifier 308 is coupled to node 326. The output of the operational amplifier 308 is coupled to the node 210. The inverting input of the operational amplifier 316 is coupled to the node 324. The non-inverting input of the operational amplifier 316 is coupled to the node 328. The output of the operational amplifier 316 is coupled to the node 212.

The resistor 310 having the resistor R1 is coupled between the node 326 and the emitter of the BJT 314. Each of the base and collector of BJT314 is coupled to ground node 112. Thus, the BJT314 is a diode-connected BJT having an anode coupled to the resistor 310 and a cathode coupled to the ground node 112. The emitter of BJT312 is coupled to node 324. Each of the base and collector of the BJT 312 is coupled to the ground node 112. Thus, the BJT 312 is a diode-connected BJT having an anode coupled to the node 324 and a cathode coupled to the ground node 112. BJT314 has an emitter region N times that of BJT312, where N is an integer greater than 1.

In operation, operational amplifier 308 is self-biased to, and sets the control voltage _{V P} to turn on the FET302 and 304. By applying negative feedback, the operational amplifier 308 makes the voltage at the node 324 equal to the voltage at the node 326. The voltage at node 324 is the voltage between the emitter and the base of BJT312 a voltage _{V EB1.} The voltage V _EB1 compensates for the temperature (ie, has a negative Tempco). The voltage at the emitter of the BJT314 is VEB2, which is the voltage between the emitter and the base of the _BJT314 . The voltage V _EB2 compensates for the temperature. The voltage across the resistor 310 between node 326 and the emitter of BJT314 is ΔV _BE = V _EB1- V _EB2 = V _BE2- V _BE1 . Differential voltage [Delta] V _BE is mathematically, it can be expressed as _{Δ BE = n * V T *} In (N), where, _{V T} is the thermal temperature, n is the ideality factor, N is the BJT314 the BJT312 Is the ratio of the emitter region between and, where In represents the natural logarithm function. For purposes of illustration herein, the ideal coefficient n is assumed to be 1 and is omitted from subsequent equations. The thermal voltage _VT = KT / q, where T is the temperature in Kelvin, K is the Boltzmann constant, and q is the electron charge in Coulomb. As such, ΔV _BE is proportional to temperature (ie, has positive Tempco). ΔV _BE also depends on the ratio of collector currents, which is related to the base current due to the beta factor (ie, beta = Ic / Ib, where Ic is the collector current and Ib is the base current. Is). The current Iptat can be mathematically expressed as Iptat = ΔV _BE / R1, which is proportional to the temperature. Voltage _{V P} at node 210 controls the current source in Tempco circuit for mirroring the current Iptat.

Operational amplifier 316 applies a negative feedback through the adjustment in the control voltage _{V C} to equalize the voltage _{(e.g., V EB1)} in the voltage and node 324 at node 328. Therefore, (coming into the ladder resistor 318 from node 330) current ICTAT is mathematically can be expressed as _{Ictat = V EB1 / R2 ''} . Since V _EB1 is to compensate for the temperature, ICTAT also compensates for the temperature. Voltage _{V C} at node 212 controls the current source in Tempco circuit for mirroring the current ICTAT. The current source Ictat can be trimmed by changing the flat trim cord. Flat trim balances the temperature coefficient by adjusting Ictat relative to Iptat so that Ictat + Iptat = Iztata is an approximate constant over the temperature range. It should be noted that the slope of Ictat with respect to temperature is non-linear while the slope of Iptat with respect to temperature is constant. Therefore, Iztat varies from a desired constant value over a temperature range. Further, as will be described later, this primary error is corrected.

FIG. 5A is a schematic diagram showing an example zero Tempco circuit 204. The zero Tempco circuit 204 includes p-channel FETs 502, 504, 506, and 508 (eg, p-type MOSFETs). The zero Tempco circuit 204 further includes a curvature correction circuit 510, a rudder resistor 512, and a rudder resistor 554.

The source of the FET502 _is coupled to the supply node 110 to _{V CC.} The drain of the FET 502 is coupled to the node 530. The gate of the FET502 is coupled to the supply node 212 a control voltage _{V C.} The source of the FET504 _is coupled to the supply node 110 to _{V CC.} The drain of FET 504 is coupled to node 530. The gate of the FET504 is coupled to supply node 210 of the control voltage _{V P.} The source of FET 506 is coupled to node 110. The drain of FET 506 is coupled to node 532. The gate of the FET506 is coupled to supply node 212 of the control voltage _{V C.} The source of the FET508 is coupled to supply node 110 to _{V CC.} The drain of FET 508 is coupled to node 532. The gate of the FET508 is coupled to supply node 210 of the control voltage _{V P.} FETs 502 and 504 form a current source 514 ₁ that mirrors Ictat and Iptat. FET506 and 508 form a current source 514 ₂ mirroring Ictat and Iptat.

A ladder resistor 512 with resistor R _LOAD1 is coupled between node 530 and ground node 112. Node 556 is coupled to the selected tap of the rudder resistor 512 based on the value of the Ref1 trim code. The tap selection results in a resistor 512 ₁ coupled between node 530 and node 556, and a resistor 512 ₂ coupled between node 556 and ground node 112. Resistor 512 ₁ ^'has a resistance 512 ₂ values _{R ^LOAD1'} value _{R LOAD1} has a ^'. The curvature correction circuit 510 is coupled to the node 556 to supply the current Icor, as will be further described later.

A ladder resistor 554 with resistor R _LOAD2 is coupled between node 532 and ground node 112. Node 558 is coupled to the selected tap of rudder resistor 554 based on the value of the Ref2 trim code. The tap selection, resistors 554 ₁ are combined, and node 558 and resistor 554 ₂ is coupled between the ground node 112 is brought between node 532 and node 558. Resistor 554 ₁ ^'has a resistance 554 ₂ values _{R ^LOAD2'} value _{R LOAD2} has a ^'.

In operation, the control voltage V C controls the FET502 and 506 to supply current ICTAT. Control voltage V P which controls the FET504 and 508 to supply current Iptat. Currents Ictat and Iptat are sent to node 530. The control circuit 114 sets the Ref1 trim control values of R LOAD1 'and R LOAD1' '. The curvature correction circuit 510 supplies the current Icor to the ladder resistor 512, so that the sum of the currents Iztat and Icor is conducted through the resistor R LOAD1 '' under steady state conditions.

Node 556 _is referred to as _{V ref1,} it supplies a voltage proportional to Iztat + Icor. The voltage V _ref1 has zero Tempco.

The currents Ictat and Iptat are sent to node 532. Under steady-state conditions, the current Iztat conducts through the rudder resistor 554. The control circuit 114 sets the Ref2 trim control values of R LOAD2 'and R LOAD2' '. Node 558 supplies a voltage V ref 2 proportional to Iztat. The voltage V ref2 has zero Tempco. The voltage output by LPF538 is proportional to Iztat. The operational amplifier 540, resistor 544, resistor 546, and resistor 552 are configured as non-inverting amplifiers that apply a configured amount of gain to the voltage output by LPF538. The gain is determined by the resistance values of resistors 544, 546, and 552. Node 542 supplies zero Tempco voltage V ref2 . Resistors 544, and 552, a fraction (e.g., half the voltage for generating the V ref2 / 2) of the V ref2 at node 550 to form a voltage divider for supplying.

The Ref1 trim code and Ref2 trim code set the direct current (DC) level of the corresponding pregain voltage at nodes 556 and 558, respectively. Gain circuits can be used to amplify or attenuate the pregain voltage. The voltage divider can also provide one or more fractions of the post-gain reference voltage.

In the example, the zero Tempco circuit 204 includes two current sources 514 for mirroring Ictat and Iptat to generate three zero Tempco voltages. In another example, the zero Tempco circuit 204 can include less than two or more than two current sources 514 to generate any number of zero Tempco voltages. In one example, one or both of the gain circuits 516 can be omitted. Alternatively, another current source 514 can be fed to another ladder resistor that supplies the pregain output voltage.

FIG. 5B is a schematic diagram showing a curvature correction circuit 510 according to an example. The curvature correction circuit 510 includes p-channel FETs 564, 566, and 568 (eg, p-type MOSFETs). The curvature correction circuit 510 further includes PNP BJT570 and 572, and a transconductance circuit 578.

FET564,566 and 568 source, _is coupled to node 110 supplies _{V CC.} The drain of the FET564 is coupled to node 574, a gate of the FET564 is coupled to the supply node 212 a control voltage _{V C.} The drains of FETs 566 and 568 are coupled to node 576. The gate of the FET566 is coupled to the supply node 212 a control voltage _{V C.} The gate of the FET568 is coupled to the supply node 210 a control voltage _{V P.} The width of FETs 566 and 568 is half that of FET564. The FET 564 supplies a mirror of the current Ictat, the FET 566 supplies a mirror of the current Ict / 2, and the FET 568 supplies a mirror of the current Ipt / 2.

The emitter of the BJT570 is coupled to the node 574 to provide the voltage _VEB3 . The emitter of the BJT572 is coupled to the node 576 to provide the voltage _VEB4 . The base and collector of BJT570 and 572 are coupled to ground node 112. Thus, the BJT 570 and 572 are diode-connected BJTs coupled between the node 574 and the ground node 112 and between the node 576 and the ground node 112, respectively. BJT572 has N'times the emitter region of BJT570, where N'is an integer greater than 1.

The inputs of the transconductance circuit 578 are coupled to nodes 574 and 576. The output of the transconductance circuit 578 is coupled to the node 556 and supplies the current Icor.

During operation, the current Ictat changes non-linearly with temperature. That is, the derivative of Ictat with respect to temperature is not constant. As such, any voltage generated from Iztat will change with temperature. FIG. 6 is a graph 600 showing the dependence of V _ref1 on temperature. The graph 600 includes an axis 602 representing the temperature and an axis 606 representing the voltage V _ref1 in volts. As shown by the curve 610, the voltage V _ref1 becomes convex with respect to temperature. That is, V _ref1 increases as the temperature increases until it reaches the maximum value, and then decreases as the temperature further increases.

Returning to Figure 5B, the curvature correction circuit 510 adds the secondary correction Iztat, to reduce the temperature dependence of _{V ref1} by the primary error of ICTAT. Especially, the differential voltage is _{ΔV BE2 = V BE4 -V BE3 =} V T * In ((N '* Iztat / 2) / I S4) -V T * In (Ictat / I S3), wherein each I _S4 and _{I S3} are reverse saturation current of BJT570 and 572. If reverse saturation current are approximately equal, equation is reduced to _{ΔV BE2 = V T * (In} (N '* Iztat / 2) -In (Ictat)). Graph 600 of FIG. 6 includes an axis 604 representing ΔV _BE2 in volts. As shown by the curve 608, the voltage ΔV _BE2 becomes concave with respect to temperature. That is, ΔV _BE2 decreases as the temperature increases until it reaches the minimum value, and then increases as the temperature further increases. The transconductance circuit 578 converts the differential voltage ΔV _BE2 into a current Icor having the same concave curvature with respect to temperature. The transconductance circuit 578 injects current Icor into node 556. As the temperature changes, the current Ict + Icor becomes substantially constant due to the quadratic curvature correction.

FIG. 5C is a schematic diagram showing another portion 204A of the zero Tempco circuit 204 by way of example. Part 204A of zero Tempco circuit 204 includes p-channel FETs 580 and 582, as well as a ladder resistor 586. The source of the FET580 _is coupled to the supply node 110 to _{V CC.} The drain of FET 580 is coupled to node 584. The gate of the FET580 is coupled to supply node 212 of the control voltage _{V C.} The source of the FET582 is coupled to supply node 110 to _{V CC.} The drain of FET 582 is coupled to node 584. The gate of the FET582 is coupled to supply node 210 of the control voltage _{V P.} FET580 and 582 form a current source 514 ₃ mirroring Ictat and Iptat.

A ladder resistor 586 with resistor R _LOAD3 is coupled between node 584 and ground node 112. Node 588 is coupled to the selected tap of rudder resistor 586 based on the value of the Ref3 trim code. Tap selection results in a resistor 586 ₁ coupled between node 584 and node 588 and a resistor 586 ₂ coupled between node 588 and ground node 112. Resistor 586 ₁ ^'has a resistance 586 ₂ values _{R ^LOAD3'} value _{R LOAD3} having ^'. Node 588 supplies voltage Vref3, which is a pregain zero Tempco voltage.

FIG. 7 is a schematic diagram showing a negative Tempco circuit 206 according to an example. Negative Tempco circuit 206 includes six p-channel FETs 702 ... 712 and ladder resistors 718, 720, 728, and 730. The source of the FET702 ... 712 _is coupled to the supply node 110 to _{V CC.} The drains of FETs 702 and 704 are coupled to node 714. The drain of the FET 706 is coupled to the node 724. The drains of FETs 708 and 710 are coupled to node 716. The drain of the FET 712 is coupled to the node 736. The gate of the FET702 and 708 are coupled to the supply node 210 a control voltage _{V P.} FET704,706,710, and 712 of the gate is coupled to the supply node 212 a control voltage _{V C.} The FETs 702, 704, and 706 form the first current source 715 ₁ , and the FETs 708, 710, and 712 form the second current source 715 ₂ .

A ladder resistor 718 with resistor R3 is coupled between node 714 and node 726. A rudder resistor 720 with resistor R4 is coupled between node 726 and ground node 112. The rudder resistors 718 and 720 are coupled in series between node 714 and ground node 112. The selected tap of the rudder resistor 718 is coupled to the node 722 as determined by the code Neg1 trim generated by the control circuit 114. The rudder resistor 718 is effectively divided between the resistor 718 ₁ and the resistor 718 ₂ , in which case the resistor 718 ₁ has the value R3'and the resistor 718 ₂ has the value R3''. The selected tap of the rudder resistor 720 is coupled to the node 724, as determined by the code Neg1 tilt trim generated by the control circuit 114. The rudder resistor 720 is effectively divided between the resistor 720 ₁ and the resistor 720 ₂ , in which case the resistor 720 ₁ has the value R4'and the resistor 720 ₂ has the value R4''.

A ladder resistor 728 with a resistor R5 is coupled between node 716 and node 734. A ladder resistor 730 with resistor R6 is coupled between node 734 and ground node 112. Ladder resistors 728 and 730 are coupled in series between node 716 and ground node 112. The selected tap of the rudder resistor 728 is coupled to the node 732 as determined by the code Neg2 trim generated by the control circuit 114. The rudder resistor 728 is effectively split between the resistor 728 ₁ and the resistor 728 ₂ , in which case the resistor 728 ₁ has the value R5'and the resistor 728 ₂ has the value R5'. The selected tap of the rudder resistor 730 is coupled to the node 736, as determined by the code Neg2 tilt trim generated by the control circuit 114. The rudder resistor 730 is effectively split between the resistor 730 ₁ and the resistor 730 ₂ , where the resistor 730 ₁ has the value R6'and the resistor 730 ₂ has the value R6''.

During operation, the FETs 702 and 704 supply current Iztat (ie, Ictat + Iptat) through a series combination of rudder resistors 718 and rudder resistors 720. The FET 706 supplies a mirror of Ictat through a resistor 720 ₂ . The voltage at node 722 is V _neg1 = Iztat * (R3 + R4) + Ictat * R4''. The voltage V _neg1 has a zero Temoco component Iztat * (R3 + R4) and a negative Tempco component Ictat * R4''. Therefore, the voltage V _neg1 has a negative Tempco. The control circuit 114 sets the code Neg1 tilt trim to control the tilt of the negative Tempco with respect to the voltage V _neg1 . The control circuit 114 sets the code Neg1 trim to control the DC level of the voltage V _neg1 given the code used for the Neg1 tilt trim.

The FETs 708 and 710 supply the current Iztat (ie, Ictat + Iptat) through a series combination of the rudder resistor 728 and the rudder resistor 730. The FET 712 supplies a mirror of Ictat through a resistor 730 ₂ . The voltage at node 732 is V _neg2 = Iztat * (R5 + R6) + Ictat * R6''. The voltage V _neg2 has a zero Temoco component Iztat * (R5 + R6) and a negative Tempco component Ictat * R6''. Therefore, the voltage V _neg2 has a negative Tempco. The control circuit 114 sets the code Neg2 tilt trim to control the tilt of the negative Tempco with respect to the voltage V _neg2 . The control circuit 114 sets the code Neg2 trim to control the DC level of the voltage V _neg2 given the code used for the Neg2 tilt trim. The voltage V _neg2 is set independently of the voltage V _neg1 .

Although two current sources 715 and two ladder resistor pairs are shown, the negative Tempco circuit 206 can include any number of current sources 715, each coupled to a ladder resistor pair as shown in FIG. Will be done. In this way, the negative Tempco circuit can supply any number of temperature compensation voltages. Further, although the gain circuit is omitted from FIG. 7, in some examples one or both of the pregain voltage outputs can be coupled to a gain circuit similar to the configuration shown in FIG. 5A.

FIG. 8 is a schematic diagram showing a positive Tempco circuit 208 according to an example. Positive Tempco circuits 208 include p-channel FETs 802 and 804, ladder resistors 824, switches 808 and 810, and digital / analog (DAC) current sources 816 and 820. The source of the FET802 and 804 are coupled to the supply node 110 to voltage _{V CC.} The drains of FETs 802 and 804 are coupled to node 806. The gate of the FET802 is coupled to the supply node 212 a control voltage _{V C.} The gate of the FET804 is coupled to the supply node 210 a control voltage _{V P.} The FETs 802 and 804 form a current source 815 that supplies Iztat = Ictat + Iptat.

A ladder resistor 824 with a resistor R7 is coupled between node 806 and ground node 112. The selected tap of the ladder resistor 824, as controlled by the Blk trim code set by the control circuit 114, is coupled to the node 826. The rudder resistor 824 is effectively divided into resistors 824 ₁ and resistor 824 ₂ having values R7'and R7', respectively. The resistor 824 ₁ is coupled between node 806 and node 826. The resistor 824 ₂ is coupled between the node 826 and the ground node 112. Node 826 supplies the voltage V _BLK .

One terminal of the switch 808 is coupled to the supply node 210 a control voltage _{V P.} Another terminal of switch 808 is coupled to node 812. The reference voltage input of the current DAC816 is coupled to node 812. The current DAC816 includes a digital control input coupled to a bus 818 that supplies the digital signal Blk_p. The current output of the current DAC816 is coupled to node 806. Supply voltage input of the current DAC816 is coupled to the supply node 110 to voltage _{V CC.}

One terminal of the switch 810 is coupled to the supply node 212 a control voltage _{V C.} Another terminal of the switch 810 is coupled to the node 814. The reference voltage input of the current DAC820 is coupled to node 814. The current DAC820 includes a digital control input coupled to a bus 822 that supplies the digital signal Blk_c. The current output of the current DAC820 is coupled to the ground node 112. The supply voltage input of the current DAC820 is coupled to the node 806.

During operation, the voltage V _BLK = Iztat * R7'' + Idac * R7''. The current Idac flowing into the node 806 depends on the state of the switches 808 and 810. If both switches 808 and 810 are open, the current Idac is zero. If switch 808 is closed and switch 810 is opened, current DAC816 receives the voltage _{V P.} The current DAC816 provides a ratio of the current Iptat based on the code supplied by the digital signal Blk_p. The current DAC816 outputs the current Idac_p. The current Idac is equal to the current Idac_p supplied by the current DAC816. In such a case, the voltage V _BLK includes the zero Temoco component Iztat * R7'' and the positive Tempco component Idac_p * R7''.

If switch 810 is closed and switch 808 is opened, current DAC820 receives a voltage _{V C.} The current DAC820 reduces the ratio of the current Ictat based on the code supplied by the digital signal Blk_C. The current DAC820 reduces the current Idac_c. The current Idac is equal to -Idac_c supplied by the current DAC820. In such a case, the voltage V _BLK contains a zero Temoco component Iztat * R7'' and a positive Tempco component-Idac_c * R7''.

If both switches 808 and 810 are closed, the current Idac = Idac_p-Idac_c. In such a case, the voltage V _BLK includes a zero Temoco component Iztat * R7'' and a positive Tempco component (Idac_p-Idac_c) * R7''.

In some examples, the control circuit 114 produces control signals Blk Ptat and Blk Ctat for opening and closing switches 808 and 810 in alternating order. The control circuit 114 uses the digital signals Blk_p and Blk_c to control the magnitude of vibration. The control circuit 114 uses a Blk trim cord to control the DC level of the voltage V _BLK . Although the signal current source 815 and the load (ladder resistor 824 and current DAC816, 820) are shown, the positive Tempco circuit 208 has multiple current sources 815 and associated loads to generate multiple positive Tempco voltages. It should be understood that it can be included. In some examples, the pregain voltage V _BLK can be coupled to the gain circuit to provide a positive Tempco voltage along with the gain.

FIG. 9 is a flow chart showing a method 900 for generating a voltage reference according to an example. Method 900 starts at block 902, where the reference circuit 202 produces an Iptat and a control voltage Vp. At block 904, the reference circuit 202 produces an Ictat and a control voltage Vc. In block 906, one or more current sources generate a sum of Ipt and Ictat in response to control voltages Vp and Vc. For example, in block 908, the zero Tempco circuit 204 produces a zero Tempco voltage from the sum current. At block 910, the negative Tempco circuit 206 produces a negative Tempco voltage from the sum current. At block 912, the positive Tempco circuit 208 produces a positive Tempco voltage from the sum current.

FIG. 10 is a block diagram showing a test system 1000 according to an example. The test system 1000 includes an automatic test equipment (ATE) 1002 and a wafer 1004 with a plurality of ICs 1100. The ATE 1002 includes a central processing unit (CPU) 1008, a memory 1012, an input / output (IO) circuit 1010, and a support circuit 1006. The CPU 1008 can be any type of general purpose processor, such as an x86-based processor or an ARM®-based processor. The CPU 1008 may include one or more cores and related networks (eg, cache memory, memory management unit (MMU), interrupt controller, etc.). The CPU 1008 is configured to perform one or more of the operations described herein and to execute program code that can be stored in memory 1012. The support circuit 1006 includes various devices that cooperate with the CPU 608. For example, the support circuit 1006 can include a chipset (eg, north bridge, south bridge, platform host controller, etc.), voltage regulator, and firmware (eg, BIOS). In some examples, the CPU 1008 may be a system-in-package (SiP) or system-on-chip (SoC) that absorbs all and a significant portion of the functionality of the chipset (eg, north bridge, south bridge, etc.). be able to. The IO circuit 1010 includes various circuits configured to communicate with the IC 1100.

Memory 1012 is a device that makes it possible to store and retrieve information such as executable instructions and data. The memory 1012 may include one or more RAM modules such as, for example, a double data rate (DDR) dynamic random access memory (RAM) (DRAM). The ATE1002 allows local storage devices (eg, one or more hard disks, flash memory modules, solid disks, and optical disks) and / or test system 1000 to communicate with one or more network data storage systems. Can include a variety of other devices, including storage interfaces.

FIG. 11 is a blow diagram showing a method 1100 for setting a trim code in a voltage reference circuit according to an example. Method 1100 can be performed by ATE1002 to set flat trim in reference circuit 202 and Ref_x trim in circuit 500A (eg Ref1 trim, Ref2 trim, etc.) for each IC100 on wafer 604.

Method 1100 begins in step 1102, where wafer 1004 is placed in a 0 degree Celsius (0C) environment, ATE1002 arranges trim cords for flat trim, and measures Vref1. The ATE1002 obtains a plurality of Vref1 values for a plurality of corresponding trim cords of the flat trim. In step 704, ATE1002 aligns the Vref1 value obtained in step 1102 with a polynomial curve having one or more coefficients (eg, three coefficients). The ATE 1002 stores a coefficient value in the IC 100 (eg, in a control circuit 114 that uses a type of memory element such as an electronic fuze (e-fuse)). FIG. 12A is a graph 1200 showing a flat trim code for output voltages at different temperatures by way of example. In Graph 1200, the horizontal axis represents the flat trim cord and the vertical axis represents the output voltage. Curve 1202 represents a polynomial curve determined at 1104 (T1 = 0C).

In step 1106, the wafer 1004 is placed in a 100 degrees Celsius (100C) environment, the ATE 1002 arranges the trim cords for the flat trim and measures Vref1. The ATE1002 obtains a plurality of Vref1 values for a plurality of corresponding trim cords of the flat trim. In step 1108, the ATE 1002 aligns the Vref1 value obtained in step 1106 with a polynomial curve having the same degree as that used in step 1104. In graph 1200, curve 1204 represents a polynomial curve determined in step 1108.

In step 1110, the ATE1002 determines the intersection of the Vref1 curve at 0C and the Vref1 curve at 100C. The ATE1002 can generate a Vref1 curve at 0C by obtaining the coefficients stored by the control circuit 114 in the IC100. The ATE1002 produces a Vref1 curve at 100C in step 1108. In step 712, the ATE 1002 determines the trim setting for the flat trim corresponding to the intersection of the Vref1 curve at 0C and the Vref1 curve at 100C. As shown in Graph 1200, the intersection of curves 1202 and 1204 yields the determined flat trim code value. In step 1114, the ATE1002 sets the flat trim to the determined trim code in step 1112 and adjusts the Ref1 trim to set the desired voltage of Vref1 (eg, 1V). FIG. 12B is a graph 1201 showing a reference trim code (T = T2) for an output voltage at a particular temperature by way of example. In graph 1201, the horizontal axis represents the reference trim code and the vertical axis represents the output voltage. Curve 1206 represents a reference trim code for the output voltage, and an output voltage of 1V yields the determined reference trim code value.

FIG. 13 is a flow chart showing a method 1300 for setting a trim code in a voltage reference circuit according to an example. Method 1300 can be performed by ATE1002 to set flat trim in reference circuit 202 and Ref_x trim in circuit 500A (eg Ref1 trim, Ref2 trim, etc.) for each IC 100 on wafer 1004.

Method 1300 begins at step 902, where ATE1002 selects an approximate trim code for flat trim. The approximate trim code for flat trim can be set based on the simulation of the voltage reference circuit. In step 1304, wafer 1004 is disposed in a 0C environment and ATE1002 selects a trim code for Ref1 trim that sets Vref1 to the desired value (eg, 1V). The ATE1002 can adjust the Ref1 trim and measure Vref1 until Vref1 gets the desired value. In step 1306, the ATE1002 stores the selected trim code for the Ref1 trim in the IC100 (eg, in the control circuit 114 that uses a memory element of the type such as an electronic fuze (e-fuse)).
In step 1308, wafer 1004 is disposed in a 100C environment and ATE1002 selects a trim code for Ref1 trim that sets Vref1 to the desired value (eg, 1V). In step 1310, the ATE1002 determines the inclination of the Ref1 trim cord with respect to temperature. For example, the ATE1002 can calculate the difference between Ref1 trim code values at 0C and 100C. FIG. 14A is a graph 1400 showing measurements of Ref1 trim cords at two different temperatures by way of example. In graph 1400, the horizontal axis represents temperature and the vertical axis represents Ref1 trim code values. At temperature T1, code 1 is obtained. At temperature T2, code 2 is obtained. If the temperature coefficient is zero, it is possible that the same code will be obtained at both temperatures. The ATE 1002 determines the slope of the curve 1002 in step 1310. In step 912, the ATE 1002 obtains the trim code value for the flat trim from the look-up table based on the Ref1 trim code tilt determined in step 1310. The lookup table can include multiple trim code values for flat trim for a plurality of corresponding Ref1 trim code tilt values. FIG. 14B is a graph 1401 showing a look-up of a flat trim code given a Ref1 trim tilt, as an example. In graph 1401, the horizontal axis represents the flat trim code and the vertical axis represents the slope of curve 1402 shown in FIG. 10A. The temperature coefficient determined in steps 1402 to 1310 is corrected by changing the flat trim code setting based on curve 1404.

FIG. 15 is a block diagram showing a programmable IC 1 according to an example in which the voltage reference circuit 200 described herein can be used. The programmable IC 1 includes a programmable logic 3, a configuration logic 25, and a configuration memory 26. The programmable IC 1 can be coupled to an external circuit such as the non-volatile memory 27, the DRAM 28, and another circuit 29. The programmable logic 3 includes a logic cell 30, a support circuit 31, and a programmable interconnect 32. The logic cell 30 includes a circuit that can be configured to implement general logic functions of a plurality of inputs. The support circuit 31 includes dedicated circuits such as a transceiver, an input / output block, a digital signal processor, and a memory. The logic cell and support circuit 31 can be interconnected using the programmable interconnect 32. Information for programming the logic cell 30, setting the parameters of the support circuit 31, and programming the programmable interconnect 32 is stored in the configuration memory 26 by the configuration logic 25. The configuration logic 25 can obtain configuration data from the non-volatile memory 27 or any other source (eg, from the DRAM 28 or other circuit 29). In some examples, the programmable IC 1 includes a processing system 2. The processing system 2 can include a microprocessor, a memory, a support circuit, an IO circuit, and the like.

FIG. 16 shows transceiver 37, configurable logic block (“CLB”) 33, random access memory block (“BRAM”) 34, input / output block (“IOB”) 36, configuration and clocking logic (CONFIG / CLOCKS). 42, digital signal processing block (“DSP”) 35, specialized input / output block (I / O) 41 (eg, configuration port and clock port), and digital clock manager, analog-to-digital converter, and A field programmable gate array (FPGA) implementation of a programmable IC 1 comprising a number of different programmable tiles including other programmable logic 39 such as system monitoring logic is shown. The FPGA can also include a PCIe interface 40 and an analog-to-digital converter (ADC) 38 and the like.

In some FPGAs, each programmable tile has at least one programmable interconnect element that has a connection to the input / output terminals 48 of the programmable logic element in the same tile, as shown by the example included at the top of FIG. ("INT") 43 can be included. Each programmable interconnect element 43 can also include connections of adjacent programmable interconnect elements in the same tile or other tiles to interconnect segments 49. Each programmable interconnect element 43 can also include a connection of general routing resources between logical blocks (not shown) to the interconnect segment 50. General routing resources are routed between a logical block (not shown) containing tracks in an interconnect segment (eg, interconnect segment 50) and a switch block (not shown) for connecting interconnect segments. Can include channels. An interconnect segment of a general routing resource (eg, an interconnect segment 50) can span one or more logical blocks. The programmable interconnect element 43, along with general routing resources, implements a programmable interconnect structure (“programmable interconnect”) for an exemplary FPGA.

In an exemplary implementation, the CLB 33 includes a single programmable interconnect element (“INT”) 43 plus a configurable logic element (“CLE”) 44 that is programmable to implement user logic. be able to. The BRAM 34 may include a BRAM logic element (“BRL”) 45 in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements contained in a tile depends on the height of the tile. In the illustrated example, the BRAM tile has the same height as the 5 CLBs, but other numbers (eg, 4) can be used. The DSP tile 35 can include a DSP logic element (“DSPL”) 46 in addition to an appropriate number of programmable interconnect elements. The IOB 36 can include, for example, one instance of the programmable interconnect element 43 and two instances of the input / output logic element (“IOL”) 47. As will be apparent to those skilled in the art, for example, the actual I / O pad connected to the I / O logic element 47 is typically not limited to the region of the input / output logic element 47.

In the example depicted, the horizontal region near the center of the die (shown in FIG. 16) is used for configuration, clock, and other control logic. Vertical columns 51 extending from this horizontal region or column are used to distribute the clock and configuration signals over the width of the FPGA.

Some FPGAs that utilize the architecture shown in FIG. 11 include additional logical blocks that block the regular columnar structure that makes up the majority of the FPGA. The additional logic blocks can be programmable blocks and / or dedicated logic.

It should be noted that FIG. 16 is intended to show only the exemplary FPGA architecture. For example, the number of logical blocks in a row, the relative width of the rows, the number and order of rows, the types of logical blocks contained in a row, the relative size of logical blocks, and the interconnect / logical implementations included at the top of FIG. It is just an example. For example, in a real FPGA, multiple adjacent CLB rows are typically included wherever the CLB appears, but to facilitate efficient implementation of user logic, but adjacent CLB rows. The number of depends on the overall size of the FPGA.

Some non-limiting examples are provided below.

In one example, a voltage reference circuit can be provided. Such a voltage reference circuit is configured to generate a first circuit configured to generate a temperature proportional current and a corresponding first control voltage, and a temperature compensating current and a corresponding second control voltage. A reference circuit including a second circuit to be generated, and a first current source coupled to the first load circuit, the first current source responding to a first control voltage and a second control voltage. Then, the sum current of the temperature proportional current and the temperature compensation current is generated, and the first load circuit generates a zero temperature coefficient (Tempco) voltage from the sum current, in the first current source and the second load circuit. The second current source to be coupled, the second current source, in response to the first control voltage and the second control voltage, generates a sum current of the temperature proportional current and the temperature compensation current, and the first The load circuit of 2 may include a second current source, which produces a negative Tempco voltage from the sum current and the temperature compensation current.

Some such voltage reference circuits are a third current source coupled to a third load circuit, the third current source responding to a first control voltage and a second control voltage. The third load circuit generates a positive Tempco voltage from the sum current and at least one of the temperature compensating current and the temperature compensating current. It may further include a current source of.

In some such voltage reference circuits, the third current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain, the first The gate of the first FET is coupled to receive the first control voltage, and the gate of the second FET is coupled to receive the second control voltage, including the first FET and the second FET. Good.

In some such voltage reference circuits, a third load circuit is switchably coupled to receive a first control voltage and is configured to supply a first positive temperature coefficient (Tempco) current. A second current that is switchably coupled to receive a second control voltage and is configured to supply a second positive Tempco current with a first current digital-to-analog converter (DAC). A rudder resistor coupled between the DAC and the first common drain and ground node that, in addition to the sum current, has one or both of the first positive Tempco current and the second positive Tempco current. , A ladder resistor, which converts to a positive Tempco voltage, and may be included.

In some such voltage reference circuits, the first current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain. The gate of one FET is coupled to receive a first control voltage and the gate of a second FET is coupled to receive a second control voltage, including a first FET and a second FET. Often, the first load circuit is a ladder resistor coupled between the first common drain and the ground node and may include a ladder resistor that converts the sum current to a zero-Tempco voltage.

Some such voltage reference circuits may include a curvature compensating circuit configured to inject a correction current into the ladder resistor and combine it with the sum current, and the curvature compensating circuit is a second common source and a second common source. A third FET and a fourth FET having two common drains, the gate of the third FET is coupled to receive the first control voltage, and the gate of the third FET is the second control voltage. A third and fourth FETs coupled to receive, a fifth FET with a gate coupled to receive a second control voltage, and a drain and ground node of the fifth FET. A first diode-connected bipolar junction transistor (BJT) coupled between the two, a second diode-connected bipolar junction transistor (BJT) coupled between the second common drain and the ground node, and a fifth It includes a transconductance circuit configured to convert the voltage between the drain of the FET and the second common drain into a correction current.

In some such voltage reference circuits, the second current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain. The gate of the first FET is coupled to receive the first control voltage, and the gate of the second FET is coupled to receive the second control voltage, the first FET and the second FET, and the second FET. A third FET having a gate coupled to the control voltage of 2 may be included, and the second load circuit is a first ladder coupled in series between the first common drain and the ground node. A resistor and a second ladder resistor may be included, the first ladder resistor and the second ladder resistor receive a sum current from the first common drain, and a part of the second ladder resistor is a third. Receives temperature compensation current from the drain of the FET.

In some such voltage reference circuits, the reference circuit is a first field effect transistor (FET) having a first common source and a first common gate, a second FET, and a drain of the first FET. A first diode-connected bipolar junction transistor (BJT) coupled between the and ground node, and a first resistor and second resistor coupled in series between the drain of the second FET and the ground node. A first arithmetic amplifier with a diode-connected BJT and a non-inverting input coupled to the drain of a second FET, an inverting input coupled to the drain of a first FET, and an output coupled to a first common gate. And a third FET having a source coupled to a common source, a ladder resistor coupled between the drain and ground node of the third FET, and an inverting input coupled to the drain of the first FET. , A non-inverting input coupled to a ladder resistor, and a second arithmetic amplifier having an output coupled to the gate of a third FET.

In another example, integrated circuits may be provided. Such an integrated circuit may include one or more circuits and a voltage reference circuit that supplies at least one voltage to the one or more circuits, the voltage reference circuit corresponding to the temperature proportional current. A reference circuit comprising a first circuit configured to generate a first control voltage and a second circuit configured to generate a temperature compensation current and a corresponding second control voltage, and a first. The first current source coupled to the load circuit of the above, the first current source, in response to the first control voltage and the second control voltage, is the sum current of the temperature proportional current and the temperature compensation current. The first current source, which is generated and the first load circuit generates a zero temperature coefficient (Tempco) voltage from the sum current, is a first current source and a second current source coupled to the second load circuit, the second. In response to the first control voltage and the second control voltage, the current source of the second load circuit generates a sum current of the temperature proportional current and the temperature compensation current, and the second load circuit is a negative Tempco from the sum current and the temperature compensation current. Includes a second source of current that produces a voltage.

In some such integrated circuits, the voltage reference circuit is further a third current source coupled to the third load circuit, the third current source being the first control voltage and the second. In response to the control voltage, a sum of the temperature proportional current and the temperature compensating current is generated, and the third load circuit draws a positive Tempco voltage from the sum current and at least one of the temperature compensating current and the temperature compensating current. It further includes a third current source to generate.

In such an integrated circuit, the third current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain of the first FET. The gate may include a first FET and a second FET coupled to receive a first control voltage and a gate of the second FET coupled to receive a second control voltage.

In some such integrated circuits, a third load circuit is switchably coupled to receive a first control voltage and is configured to supply a first positive temperature coefficient (Tempco) current. A second current DAC that is switchably coupled to receive a second control voltage and is configured to supply a second positive Tempco current with a first current digital-to-analog converter (DAC). And a ladder resistor coupled between the first common drain and the ground node, in addition to the sum current, one or both of the first positive Tempco current and the second positive Tempco current. A ladder resistor, which converts to a positive Tempco voltage, may be included.

In some such integrated circuits, the first current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain, the first. The gates of the FETs are coupled to receive a first control voltage and the gates of the second FETs may include a first FET and a second FET coupled to receive a second control voltage. The first load circuit may include a rudder resistor coupled between the first common drain and the ground node, which converts the sum current into a zero-Tempco voltage. Some such integrated circuits may further include a curvature compensating circuit configured to inject a correction current into the ladder resistor and combine it with the sum current, the curvature compensating circuit being a second common source and a second common source. A third FET and a fourth FET having two common drains, the gate of the third FET is coupled to receive the first control voltage, and the gate of the third FET is the second control voltage. A third and fourth FETs coupled to receive, a fifth FET with a gate coupled to receive a second control voltage, and a drain and ground node of the fifth FET. A first diode-connected bipolar junction transistor (BJT) coupled between the two, a second diode-connected bipolar junction transistor (BJT) coupled between the second common drain and the ground node, and a fifth It includes a transconductance circuit configured to convert the voltage between the drain of the FET and the second common drain into a correction current.

In some such integrated circuits, the second current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain, the first. The gate of the FET is coupled to receive the first control voltage, and the gate of the second FET is coupled to receive the second control voltage, the first FET and the second FET, and the second FET. A third FET, which has a gate coupled to the control voltage of the above, may be included, and the second load circuit is a first ladder resistor coupled in series between the first common drain and the ground node. A device and a second ladder resistor may be included, the first ladder resistor and the second ladder resistor receive a sum current from the first common drain, and a part of the second ladder resistor is a third. Receives temperature compensation current from the drain of the FET.

In some such integrated circuits, the reference circuit includes a first field effect transistor (FET) and a second FET with a first common source and a first common gate, and a drain of the first FET. A first diode-connected bipolar junction transistor (BJT) coupled to the ground node, and a first resistor and second diode coupled in series between the drain of the second FET and the ground node. A connected BJT and a first arithmetic amplifier having a non-inverting input coupled to the drain of a second FET, an inverting input coupled to the drain of a first FET, and an output coupled to a first common gate. , A third FET having a source coupled to a common source, a ladder resistor coupled between the drain and ground node of the third FET, and an inverting input coupled to the drain of the first FET. It may include a non-inverting input coupled to a rudder resistor and a second arithmetic amplifier having an output coupled to the gate of a third FET.

In another example, a method of generating a voltage reference may be provided. Such a method produces a temperature proportional current and a corresponding first control voltage in the first circuit of the reference circuit and a temperature compensation current and a corresponding second control voltage in the second circuit of the reference circuit. To generate a sum of temperature proportional current and temperature compensation current in the first current source in response to the first control voltage and the second control voltage, and to the first current source. Generating a zero temperature coefficient (Tempco) voltage from the sum current in the combined first load circuit and a temperature proportional current in the second current source in response to the first and second control voltages. And to generate a sum of the temperature compensating currents and to generate a negative Tempco voltage from the summing currents and the temperature compensating currents in the second load circuit coupled to the second current source. Some such methods generate a sum of temperature-proportional current and temperature-compensated current at a third current source in response to a first and second control voltage, and a third. The third load circuit coupled to the current source may further include generating a positive Tempco voltage from the sum current and at least one of the temperature compensating current and the temperature proportional current. In some such methods, the step of generating a positive temco voltage is from a first current digital-to-analog converter (DAC), which is switchably coupled to receive a first control voltage. Supplying a Tempco current, supplying a second positive Tempco current from a second current DAC switchably coupled to receive a second control voltage, and adding to the sum current in the ladder resistance circuit. It may include converting one or both of the first positive Tempco current and the second positive Tempco current into a positive Tempco voltage.

Some such methods may further include injecting a correction current into the first load circuit and combining it with the sum current.

In yet another example, a method of trimming a voltage reference in an integrated circuit (IC) may be provided. Such a method is for a voltage reference reference circuit configured to generate a temperature proportional current and a corresponding first control voltage, as well as a temperature compensation current and a corresponding second control voltage at a first temperature. Arranging the first plurality of trim cords, measuring the voltage reference voltage output for each of the first plurality of trim cords to obtain the first voltage output value, and at the second temperature. Arranging the second plurality of trim cords for the reference circuit, measuring the voltage reference voltage output for each of the second plurality of trim cords in order to obtain the second voltage output value, and the first It may include selecting a trim code for the reference circuit based on the voltage output value and the second voltage output value.

Some such methods may further include matching the first voltage output value to the polynomial and storing one or more first coefficients of the polynomial in the IC.

Some such methods further match the second voltage output value to a polynomial to generate one or more second coefficients and generate using one or more first coefficients. It may further include determining the intersection of the first curve to be made and the second curve generated using one or more second coefficients.

In some such methods, the step of selecting a trim code may include determining the trim code from the intersection between the first curve and the second curve.

Some such methods further include adjusting the trim of the temperature coefficient (Tempco) circuit, which is controlled by the reference circuit to produce the voltage output, in order to set the voltage output to the desired voltage. Good. In some such methods, the reference circuit consists of a first field effect transistor (FET) and a second FET with a first common source and a first common gate, and drain and ground of the first FET. First diode connection coupled to the node Bipolar junction transistor (BJT) and first resistor and second diode connection coupled in series between the drain of the second FET and the ground node. A BJT and a first arithmetic amplifier having a non-inverting input coupled to the drain of a second FET, an inverting input coupled to the drain of a first FET, and an output coupled to a first common gate. A third FET having a source coupled to a common source, a ladder resistor coupled between the drain and ground node of the third FET, and an inverting input, rudder coupled to the drain of the first FET. It may include a non-inverting input coupled to a resistor and a second arithmetic amplifier having an output coupled to the gate of a third FET.

In some such methods, the voltage reference is the first current source coupled to the first load circuit, the first current source being the first control voltage and the second control voltage. In response, a first current source and a second load circuit generate a sum of the temperature proportional current and the temperature compensation current, and the first load circuit produces a zero temperature coefficient (Tempco) voltage from the sum current. A second current source coupled to, the second current source, in response to the first control voltage and the second control voltage, produces a sum of temperature proportional current and temperature compensation current. The second load circuit may include a second current source, which produces a negative Tempco voltage from the sum current and the temperature compensation current.

In some such methods, the first current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain, the first. The gates of the FETs may include a first FET and a second FET that are coupled to receive a first control voltage and the gates of the second FETs are coupled to receive a second control voltage. The first load circuit may include a rudder resistor coupled between the first common drain and the ground node, which converts the sum current into a zero Tempco voltage.

In some such methods, the second current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain, the first. The gate of the FET is coupled to receive the first control voltage, and the gate of the second FET is coupled to receive the second control voltage, the first FET and the second FET, and the second FET. A third FET having a gate coupled to the control voltage may be included, and the second load circuit is a first ladder resistor coupled in series between the first common drain and the ground node. And a second ladder resistor may be included, the first ladder resistor and the second ladder resistor receive a sum current from the first common drain, and a part of the second ladder resistor is a third FET. Receives temperature compensation current from the drain of.

In some such methods, the voltage reference is a third current source coupled to the third load circuit, the third current source being the first control voltage and the second control voltage. In response, it produces a sum of the temperature proportional current and the temperature compensating current, and the third load circuit generates a positive Tempco voltage from the sum current and at least one of the temperature compensating current and the temperature compensating current. A third current source may be included.

In another example, a device for trimming a voltage reference in an integrated circuit (IC) may be provided. Such a device for trimming a voltage reference in an integrated circuit (IC) includes a memory, a temperature proportional current and a corresponding first control voltage at a first temperature, and a temperature compensation current and a corresponding second. Arrange the first plurality of trim cords for the voltage reference reference circuit configured to generate the control voltage, and obtain the first voltage output value of the voltage reference for each of the first plurality of trim cords. Measure the voltage output, arrange the second plurality of trim cords for the reference circuit at the second temperature, and obtain the voltage reference voltage for each of the second plurality of trim cords to obtain the second voltage output value. Includes a processor configured to execute a memory-stored code to measure the output and select a trim code for the reference circuit based on a first voltage output value and a second voltage output value. It's fine.

In some such devices, the processor executes code to match the first voltage output value to the polynomial and to store one or more first coefficients of the polynomial in the IC. Is further configured.

In some such devices, the processor uses the second voltage output value to match the polynomial to generate one or more second coefficients, and the one or more first coefficients. Further to run the code to determine the intersection between the first curve generated using and the second curve generated using one or more second coefficients. It is composed.

In some such devices, the processor selects the trim code by determining the trim code from the intersection between the first curve and the second curve.

In some such devices, the processor adjusts the trim of the temperature coefficient (Tempco) circuit, which is controlled by the reference circuit to produce the voltage output, in order to set the voltage output to the desired voltage. , Further configured to execute code.

In some such devices, the reference circuit is a first field effect transistor (FET) and a second FET with a first common source and a first common gate, and drain and ground of the first FET. First diode connection coupled to the node Bipolar junction transistor (BJT) and first resistor and second diode connection coupled in series between the drain of the second FET and the ground node. A BJT and a first arithmetic amplifier having a non-inverting input coupled to the drain of a second FET, an inverting input coupled to the drain of a first FET, and an output coupled to a first common gate. A third FET having a source coupled to a common source, a ladder resistor coupled between the drain and ground node of the third FET, and an inverting input, rudder coupled to the drain of the first FET. It may include a non-inverting input coupled to a resistor and a second arithmetic amplifier having an output coupled to the gate of a third FET.

In some such devices, the voltage reference is the first current source coupled to the first load circuit, the first current source being the first control voltage and the second control voltage. In response, a first current source and a second load circuit generate a sum of the temperature proportional current and the temperature compensation current, and the first load circuit produces a zero temperature coefficient (Tempco) voltage from the sum current. A second current source coupled to, the second current source, in response to the first control voltage and the second control voltage, produces a sum of temperature proportional current and temperature compensation current. The second load circuit may include a second current source, which produces a negative Tempco voltage from the sum current and the temperature compensation current.

In some such devices, the first current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain, the first. The gates of the FETs may include a first FET and a second FET that are coupled to receive a first control voltage and the gates of the second FETs are coupled to receive a second control voltage. The first load circuit is a ladder resistor coupled between the first common drain and the ground node and may include a ladder resistor that converts the sum current to a zero Tempco voltage.

In some such devices, the second current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain, the first. The gate of the FET is coupled to receive the first control voltage, and the gate of the second FET is coupled to receive the second control voltage, the first FET and the second FET, and the second FET. A third FET having a gate coupled to the control voltage may be included, and the second load circuit is a first ladder resistor coupled in series between the first common drain and the ground node. And a second ladder resistor may be included, the first ladder resistor and the second ladder resistor receive a sum current from the first common drain, and a part of the second ladder resistor is a third FET. Receives temperature compensation current from the drain of.

In some such devices, the voltage reference is a third current source coupled to the third load circuit, the third current source being the first control voltage and the second control voltage. In response, it produces a sum of the temperature proportional current and the temperature compensating current, and the third load circuit generates a positive Tempco voltage from the sum current and at least one of the temperature compensating current and the temperature compensating current. A third current source may be included.

Although the above matter is intended for specific examples, other further examples can be devised without departing from the basic scope of the invention, the scope of the invention being determined by the claims that follow. Will be done.

During operation, the FETs 702 and 704 supply current Iztat (ie, Ictat + Iptat) through a series combination of rudder resistors 718 and rudder resistors 720. The FET 706 supplies a mirror of Ictat through a resistor 720 ₂ . The voltage at node 722 is V _neg1 = Izzat * (R3'' + R4) + Ictat * R4''. The voltage V _neg1 has a zero Tempco component Iztat * (R3'' + R4) and a negative Tempco component Ictat * R4''. Therefore, the voltage V _neg1 has a negative Tampico. The control circuit 114 sets the code Neg1 tilt trim to control the tilt of the negative Tempco with respect to the voltage V _neg1 . The control circuit 114 sets the code Neg1 trim to control the DC level of the voltage V _neg1 given the code used for the Neg1 tilt trim.

The FETs 708 and 710 supply the current Iztat (ie, Ictat + Iptat) through a series combination of the rudder resistor 728 and the rudder resistor 730. The FET 712 supplies a mirror of Ictat through a resistor 730 ₂ . The voltage at node 732 is V _neg2 = Izzat * (R5'' + R6) + Ictat * R6''. The voltage V _neg2 has a zero Tempco component Iztat * (R5'' + R6) and a negative Tempco component Ictat * R6''. Therefore, the voltage V _neg2 has a negative Tempco. The control circuit 114 sets the code Neg2 tilt trim to control the tilt of the negative Tempco with respect to the voltage V _neg2 . The control circuit 114 sets the code Neg2 trim to control the DC level of the voltage V _neg2 given the code used for the Neg2 tilt trim. The voltage V _neg2 is set independently of the voltage V _neg1 .

Claims (12)

Includes a first circuit configured to generate a temperature proportional current and a corresponding first control voltage, and a second circuit configured to generate a temperature compensation current and a corresponding second control voltage. Reference circuit and
A first current source coupled to a first load circuit, the first current source responding to the first control voltage and the second control voltage, the temperature proportional current and the temperature proportional current. A first current source, which generates a sum of the temperature compensating currents and the first load circuit generates a zero temperature coefficient (Tempco) voltage from the sum of currents.
A second current source coupled to the second load circuit, the second current source responding to the first control voltage and the second control voltage, the temperature proportional current and the temperature proportional current. A voltage reference circuit comprising a second current source, which produces the sum of the temperature compensating currents and the second load circuit generates a negative Tempco voltage from the summing currents and the temperature compensating currents. A third current source coupled to the third load circuit, the third current source responding to the first control voltage and the second control voltage, the temperature proportional current and the third current source. The third load circuit generates the sum current of the temperature compensating current, and the third load circuit generates a positive Tempco voltage from the sum current and at least one of the temperature compensating current and the temperature proportional current. The voltage reference circuit according to claim 1, further comprising a current source. The third current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain, and the gate of the first FET is the first. The second FET, wherein the gate of the second FET is coupled to receive the control voltage of the second FET and includes a first FET and a second FET to be coupled to receive the second control voltage. Voltage reference circuit. The third load circuit is switchably coupled to receive the first control voltage and is configured to supply a first positive temperature coefficient (Tempco) current, a first current digital / analog. The first common with a converter (DAC) and a second current DAC that is switchably coupled to receive the second control voltage and is configured to supply a second positive Tempco current. A ladder resistor coupled between the drain and the ground node, in which, in addition to the sum current, one or both of the first positive Tempco current and the second positive Tempco current are added to the positive Tempco. The voltage reference circuit according to claim 3, further comprising a ladder resistor that converts to a current. The first current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain, and the gate of the first FET is the first. The gate of the second FET is coupled to receive the control voltage of the first and the first load circuit includes the first FET and the second FET to be coupled to receive the second control voltage. The voltage according to claim 1, wherein is a ladder resistor coupled between the first common drain and the ground node, including a ladder resistor that converts the sum current into the zero-Tempco voltage. Reference circuit. A third curvature compensating circuit is further comprising a curvature compensating circuit configured to inject a correction current into the rudder resistor and combine it with the sum current, the curvature compensating circuit having a second common source and a second common drain. A FET and a fourth FET, the gate of the third FET is coupled to receive the first control voltage, and the gate of the third FET is coupled to receive the second control voltage. Between the third FET and the fourth FET, the fifth FET having a gate coupled to receive the second control voltage, and the drain of the fifth FET and the ground node. A first diode-connected bipolar junction transistor (BJT) coupled to, a second diode-connected bipolar junction transistor (BJT) coupled between the second common drain and the ground node, and the fifth The voltage reference circuit according to claim 5, further comprising a transconductance circuit configured to convert the voltage between the drain of the FET and the second common drain into the correction current. The second current source is a first field effect transistor (FET) and a second FET having a first common source and a first common drain, and the gate of the first FET is the first. The gate of the second FET is coupled to receive the control voltage of the first and second FETs and the second control voltage to be coupled to receive the second control voltage. The second load circuit includes a third FET having a gate to be coupled, and a first ladder resistor and a second ladder resistor coupled in series between the first common drain and a ground node. The first ladder resistor and the second ladder resistor receive the sum current from the first common drain, and a part of the second ladder resistor is a part of the third ladder resistor. The voltage reference circuit according to claim 1, which receives the temperature compensation current from the drain of the FET. The reference circuit is coupled between a first field effect transistor (FET) and a second FET having a first common source and a first common gate, and a drain and a ground node of the first FET. A first diode-connected bipolar junction transistor (BJT), a first resistor and a second diode-connected BJT coupled in series between the drain of the second FET and the ground node, and the first A first arithmetic amplifier having a non-inverting input coupled to the drain of the two FETs, an inverting input coupled to the drain of the first FET, and an output coupled to the first common gate. A third FET having a source coupled to the common source, a ladder resistor coupled between the drain of the third FET and the ground node, and the drain of the first FET coupled to the drain. The voltage reference circuit according to claim 1, further comprising an inverting input, a non-inverting input coupled to the ladder resistor, and a second arithmetic amplifier having an output coupled to the gate of the third FET. .. A method of generating a voltage reference
To generate a temperature proportional current and a corresponding first control voltage in the first circuit of the reference circuit,
To generate a temperature compensation current and a corresponding second control voltage in the second circuit of the reference circuit.
In response to the first control voltage and the second control voltage, the sum current of the temperature proportional current and the temperature compensation current is generated in the first current source.
Generating a zero temperature coefficient (Tempco) voltage from the sum current in a first load circuit coupled to the first current source.
In response to the first control voltage and the second control voltage, the temperature proportional current and the sum current of the temperature compensation current are generated in the second current source.
A method comprising generating a negative Tempco voltage from the sum current and the temperature compensating current in a second load circuit coupled to the second current source. In response to the first control voltage and the second control voltage, the third current source generates the sum current of the temperature proportional current and the temperature compensation current, and the third current source. 9. The third load circuit to be coupled further comprises generating a positive Tempco voltage from the sum current and at least one of the temperature compensating current and the temperature proportional current. Method. The step of generating the positive Tempco voltage is to supply a first positive Tempco current from a first current digital-to-analog converter (DAC) that is switchably coupled to receive the first control voltage. A second positive Tempco current is supplied from a second current DAC switchably coupled to receive the second control voltage, and in a ladder resistance circuit, in addition to the sum current, the first 10. The method of claim 10, comprising converting one or both of the positive Tempco current and the second positive Tempco current into the positive Tempco voltage. The method of claim 9, further comprising injecting a correction current into the first load circuit and combining it with the sum current.

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