CN109490753A - A kind of method of combination minimal hitting set reduction integrated circuit testing set of patterns - Google Patents

A kind of method of combination minimal hitting set reduction integrated circuit testing set of patterns Download PDF

Info

Publication number
CN109490753A
CN109490753A CN201811342777.0A CN201811342777A CN109490753A CN 109490753 A CN109490753 A CN 109490753A CN 201811342777 A CN201811342777 A CN 201811342777A CN 109490753 A CN109490753 A CN 109490753A
Authority
CN
China
Prior art keywords
test pattern
collection
minimal hitting
pattern set
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201811342777.0A
Other languages
Chinese (zh)
Other versions
CN109490753B (en
Inventor
陈晓艳
张立明
欧阳丹彤
郭江姗
刘杨
刘梦
田乃予
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jilin University
Original Assignee
Jilin University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jilin University filed Critical Jilin University
Priority to CN201811342777.0A priority Critical patent/CN109490753B/en
Publication of CN109490753A publication Critical patent/CN109490753A/en
Application granted granted Critical
Publication of CN109490753B publication Critical patent/CN109490753B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The present invention relates to a kind of methods of combination minimal hitting set reduction integrated circuit testing set of patterns, belong to digital circuit test technical field.This method generates test pattern set using automatic test pattern Core Generator to specific circuit first；Then its failure collection that can detecte is obtained to each element (test pattern) in test pattern set, and the matrix between test pattern and failure is generated according to failure collection；The corresponding mode covering collection of each failure is finally generated according to test pattern ffault matrix, as input, a minimum test pattern set is obtained using minimal hitting set method for solving, and the fault coverage of the test pattern set is verified: the test pattern set is read in into tool again, if its coverage rate reduces, the solution is modified or given up；If do not reduced, solution space just is added in this minimum test pattern set.Present invention reduces the testing costs during chip development, improve testing efficiency.

Description

A kind of method of combination minimal hitting set reduction integrated circuit testing set of patterns
Technical field
The present invention relates to the methods more particularly to a kind of survey of a kind of combination minimal hitting set reduction integrated circuit testing set of patterns The method for effectively reducing test pattern set scale in examination set of patterns optimization method, belongs to circuit testing technology field.
Background technique
Circuit test is an important ring for IC industry, and with the raising of IC complexity, test is answered Miscellaneous degree is also more complicated therewith, and the testing cost of integrated circuit even accounts for the major part of chip manufacturing cost.In order to solve day Benefit testing cost problem outstanding, people began to consider that testability problem guarantees that automatic test pattern is raw in the design phase At, and then circuit test cost is effectively reduced.
So far, many scholars study automatic test pattern generation method.1966, by J.Paul Roth is put forward for the first time D method, this is first complete automatic test pattern generation method, although this method computational complexity It is higher, but its theory significance is still generally satisfactory.Then, improvement is made on the basis of D method by Goel, proposed PODEM method, this method improve the efficiency of calculating well.Since then, automatic test pattern generation method becomes a weight There is the method for many innovations in the research topic wanted, and if Fujiwara proposes FAN method, Schulz proposes the side SOCRATES Method；Hamzaoglu and Patel proposes the new technology for accelerating PODEM method；There are also the correlation techniques etc. for combining SAT.
Many research achievements are successfully applied in industrial design, as Synopsy develop TetraMAX ATPG, The TestKompress of Mentor Graphics company, Talus ATPG and the Talus ATPGX and Cadence of Magma company The Modus Test Solution of company.And wherein TetraMAX ATPG be industry function is most strong, be easiest to using it is automatic Test pattern generation tool.For different integrated circuits, TetraMAX can be within the shortest time, and generating has highest event The test pattern set for hindering coverage rate, the test pattern set generated by the tool while being used for grinding for many other fields of academia Study carefully.
In order to which the test pattern set generated to automatic test pattern Core Generator carries out further reduction, reduce test pattern Collection scale reduces testing cost, improves testing efficiency, the invention proposes a kind of combination minimal hitting set methods to test pattern set The method of reduction.
Summary of the invention
The main purpose of the present invention is to provide a kind of method of combination minimal hitting set reduction integrated circuit testing set of patterns, It realizes the reduction to the test pattern set scale of integrated circuit, reduces the testing cost during chip development, improve test effect Rate.
In conjunction with attached drawing, it is described as follows:
In conjunction with the method for minimal hitting set reduction integrated circuit testing set of patterns, following steps are included at least:
Step 1: circuit file and corresponding document of agreement needed for generating test；
Step 2: error listing test pattern set corresponding with its is generated using automatic test pattern Core Generator；
Step 3: according to test pattern set symphysis at corresponding mode fault matrix；
Step 4: the set cluster of the manageable mode covering collection of minimal hitting set method is obtained according to mode fault matrix；
Step 5: test pattern set contract letter；
Step 6: the coverage rate of minimum test pattern set each after reduction is verified, by the length of test pattern set It is ascending to be ranked up, and export all minimum test pattern sets.
The generation mode fault matrix method includes at least:
Step 1): test pattern set is separated into individual test pattern；
Step 2): it is faulty to obtain the detectable institute of each test pattern；
Step 3): mode fault matrix is generated according to the particular order of error listing.
The method of the set cluster for obtaining mode covering collection are as follows:
Step 4): the corresponding test pattern of each failure is obtained according to mode fault matrix；
Step 5): by the corresponding mode covering collection of each failure of the corresponding test pattern generation of each failure；
Step 6): by the set cluster of obtained all modes covering collection generation mode covering collection.
The test pattern set reduction method includes at least:
Step 7): the input that the set cluster of mode covering collection is solved as minimal hitting set method；
Step 8): minimal hitting set method is called to solve to obtain the detectable faulty minimum test pattern set of institute；
Beneficial effects of the present invention: The present invention gives a kind of combination minimal hitting set reduction integrated circuit testing sets of patterns Method realizes the reduction of test pattern set scale, reduces the testing cost during chip development and testing time, in turn Testing efficiency is improved, chip development speed is accelerated.
Detailed description of the invention
The structural schematic diagram of the method for Fig. 1 combination minimal hitting set reduction integrated circuit testing set of patterns；
The flow diagram of the method for Fig. 2 combination minimal hitting set reduction integrated circuit testing set of patterns；
1 mode fault matrix of table；
2 mode of table covering collection schematic diagram；
Specific embodiment
Below by way of specific embodiment and attached drawing, the present invention will be further described in detail:
Referring to Fig. 1 and Fig. 2, in conjunction with the method for minimal hitting set reduction integrated circuit testing set of patterns, step is included at least:
Step 1: circuit file and corresponding document of agreement needed for generating test；
Step 2: error listing test pattern set corresponding with its is generated using automatic test pattern Core Generator；
Step 3: according to test pattern set symphysis at corresponding mode fault matrix；
Step 4: the set of the manageable mode covering collection of minimal hitting set method for solving is obtained according to mode fault matrix Cluster；
Step 5: test pattern set contract letter；
Step 6: the coverage rate of minimum test pattern set each after reduction is verified, by the length of test pattern set It is ascending to be ranked up, and export all minimum test pattern sets.
Specifically, such as Fig. 2 of system flow in this example, firstly, using circuit synthesis tool to ifq circuit file Circuit file and corresponding test protocol file needed for generating；Then failure is generated using automatic test pattern Core Generator List test pattern set corresponding with its；Then, according to test pattern set symphysis at corresponding mode fault matrix；From square Mode covering collection is extracted in battle array, is generated the set cluster being made of mode covering collection, is that minimal hitting set method is manageable Gather cluster；Test pattern set reduction and checkout procedure in this example is as follows, and the set cluster of mode covering collection is touched as minimum The input of set method obtains all minimum test pattern sets after solution；Finally, test pattern set coverage rate is verified, The coverage rate of minimum test pattern set each after reduction is verified, is arranged by the length of test pattern set is ascending Sequence, and all minimum test pattern sets are exported, method terminates.
The generation mode fault matrix method includes at least:
Step 1): test pattern set is separated into individual test pattern；
Step 2): it is faulty to obtain the detectable institute of each test pattern；
Step 3): mode fault matrix is generated according to the particular order of error listing.
By testing tool obtain test pattern set Pattern0:..., Pattern 1:... ..., Pattern N:... }, there is fixed data structure, test pattern set is separated according to the characteristics of data structure, to obtain list Only test pattern { Pattern0:... }, { Pattern 1:... } ..., { Pattern n:... }.To be each individual Test pattern reads in tool, error listing { the DS f generated for { Pattern0:... }0,NC f1,NC f2,DS f3,DS f4, according to error listing A, generate corresponding mode fault vector { 10011 } as shown in panelb.In test pattern set Each test pattern can obtain such a mode fault vector.The mode fault vector obtained by test pattern set Mode fault matrix is generated, as shown in table 1, wherein " 1 " indicates test pattern tiFailure f can be coveredj, " 0 " indicates test Mode tiFailure f cannot be coveredj。
The method for obtaining mode covering collection are as follows:
Step 4): the corresponding test pattern of each failure is obtained according to mode fault matrix；
Step 5): by the corresponding mode covering collection of each failure of the corresponding test pattern generation of each failure；
Step 6): by the set cluster of obtained all modes covering collection generation mode covering collection.
According to mode fault matrix shown in table 1, the corresponding test pattern of each failure is obtained.Such as failure f0Corresponding survey Die trial formula is { t0}.Finally obtain f0,f1,f2,f3,f4Corresponding test pattern set is respectively { t0},{t1,t2},{t2,t3}, {t0,t2,t3And { t0,t1}.By these test pattern set symphysis at mode covering collection be respectively { 0 }, { 1,2 }, { 2,3 }, { 0,2,3 } and { 0,1 }.The set cluster of finally obtained mode covering collection be { 0 }, { 1,2 }, { 2,3 }, { 0,2,3 }, 0, 1 } }, as shown in table 2, this set cluster constitutes the input of test pattern set reduction method.
The test pattern set reduction method includes at least:
Step 7): the input that the set cluster of mode covering collection is solved as minimal hitting set method；
Step 8): minimal hitting set method is called to solve to obtain the detectable faulty minimum test pattern set of institute；
According to the content in table 2, the set cluster of available mode covering collection be { 0 }, { 1,2 }, { 2,3 }, { 0,2,3 }, { 0,1 } }, using this set cluster as the input of minimal hitting set method, call minimal hitting set method, available detectable institute Faulty minimum test pattern set { 0,2 }, and { 0,1,3 }, the two set be set cluster { 0 }, { 1,2 }, { 2,3 }, 0, 2,3 }, { 0,1 } } minimal hitting set, that is to say, that only need test pattern t0And t2Or t0,t1And t3It can detect institute Some failures, therefore this is two solutions of test pattern set reduction method, later by { 0,2 }, and { 0,1,3 } the two minimum surveys It tries set of patterns and reads in tool, verify its validity.
Finally, it should be noted that above embodiments are only to illustrate the present invention rather than limit, although referring to preferred embodiment Describe the invention in detail, those skilled in the art should understand that, can modify to the present invention or Equivalent replacement is intended to be within the scope of the claims of the invention without departing from the spirit and scope of the present invention.

Claims (4)

1. the method for combining minimal hitting set reduction integrated circuit testing set of patterns, which is characterized in that include at least following steps:
Step 1: circuit file and corresponding document of agreement needed for generating test；
Step 2: error listing test pattern set corresponding with its is generated using automatic test pattern Core Generator；
Step 3: according to test pattern set symphysis at corresponding mode fault matrix；
Step 4: the set cluster of the manageable mode covering collection of minimal hitting set method is obtained according to mode fault matrix；
Step 5: test pattern set reduction；
Step 6: the coverage rate of minimum test pattern set each after reduction is verified, by the length of test pattern set by small To being ranked up greatly, and export all minimum test pattern sets.
2. the method for combination minimal hitting set reduction integrated circuit testing collection according to claim 1, it is characterised in that step Generation mode fault matrix method described in three includes at least:
Step 1): test pattern set is separated into individual test pattern；
Step 2): it is faulty to obtain the detectable institute of each test pattern；
Step 3): mode fault matrix is generated according to the particular order of error listing.
3. the method for combination minimal hitting set reduction integrated circuit testing set of patterns according to claim 1 or 2, feature exist In the method that the mode that obtains described in step 4 covers the set cluster of collection are as follows:
Step 4): the corresponding test pattern of each failure is obtained according to mode fault matrix；
Step 5): by the corresponding test pattern generation mode covering collection of each failure；
Step 6): by the set cluster of obtained all modes covering collection generation mode covering collection.
4. the method for combination minimal hitting set reduction integrated circuit testing set of patterns according to claim 1 or 3, feature exist Test pattern set reduction method described in step 5 includes at least:
Step 7): the input that the set cluster of mode covering collection is solved as minimal hitting set method；
Step 8): minimal hitting set method is called to solve to obtain the detectable faulty minimum test pattern set of institute.
CN201811342777.0A 2018-11-13 2018-11-13 Method for reducing integrated circuit test mode set by combining minimum bump Expired - Fee Related CN109490753B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811342777.0A CN109490753B (en) 2018-11-13 2018-11-13 Method for reducing integrated circuit test mode set by combining minimum bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811342777.0A CN109490753B (en) 2018-11-13 2018-11-13 Method for reducing integrated circuit test mode set by combining minimum bump

Publications (2)

Publication Number Publication Date
CN109490753A true CN109490753A (en) 2019-03-19
CN109490753B CN109490753B (en) 2020-12-08

Family

ID=65694298

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811342777.0A Expired - Fee Related CN109490753B (en) 2018-11-13 2018-11-13 Method for reducing integrated circuit test mode set by combining minimum bump

Country Status (1)

Country Link
CN (1) CN109490753B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110687433A (en) * 2019-10-23 2020-01-14 吉林大学 Method for reducing integrated circuit test mode set by combining PMS technology

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD123129A1 (en) * 1975-12-16 1976-11-20
JPS5951369A (en) * 1982-09-17 1984-03-24 Nec Corp Automatic characteristic measuring apparatus
JPH07160753A (en) * 1993-12-02 1995-06-23 Nec Corp Scan flip flop determining method and sequential circuit
US5574734A (en) * 1995-10-05 1996-11-12 Nec Usa, Inc. Test generation of sequential circuits using software transformations
US5726996A (en) * 1995-09-18 1998-03-10 Nec Usa, Inc. Process for dynamic composition and test cycles reduction
US6049662A (en) * 1997-01-27 2000-04-11 International Business Machines Corporation System and method for model size reduction of an integrated circuit utilizing net invariants
JP2001318129A (en) * 2000-05-08 2001-11-16 Nec Microsystems Ltd Method for setting test mode, medium storing its program, semiconductor device and electronic apparatus
US20030149927A1 (en) * 2001-02-07 2003-08-07 Seongmoon Wang Low hardware overhead scan based 3-weight weighted random BIST architectures
WO2004104608A1 (en) * 2003-05-23 2004-12-02 Koninklijke Philips Electronics N.V. Automatic test pattern generation
CN104515950A (en) * 2015-01-12 2015-04-15 华南师范大学 Built-in self-testing method and application of integrated circuit
CN105445646A (en) * 2015-12-14 2016-03-30 国家电网公司 Testing method of analog-digital circuit fault diagnosis based on neural network expert system
US20160349317A1 (en) * 2015-05-26 2016-12-01 Samsung Electronics Co., Ltd. Method and apparatus for obtaining a maximally compressed verification test set
CN106991051A (en) * 2017-04-05 2017-07-28 西安邮电大学 A kind of test case reduction method based on mutation testing and correlation rule
CN107102942A (en) * 2017-04-01 2017-08-29 南京邮电大学 A kind of minimum Fault Locating Method based on input domain location of mistake

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD123129A1 (en) * 1975-12-16 1976-11-20
JPS5951369A (en) * 1982-09-17 1984-03-24 Nec Corp Automatic characteristic measuring apparatus
JPH07160753A (en) * 1993-12-02 1995-06-23 Nec Corp Scan flip flop determining method and sequential circuit
US5726996A (en) * 1995-09-18 1998-03-10 Nec Usa, Inc. Process for dynamic composition and test cycles reduction
US5574734A (en) * 1995-10-05 1996-11-12 Nec Usa, Inc. Test generation of sequential circuits using software transformations
US6049662A (en) * 1997-01-27 2000-04-11 International Business Machines Corporation System and method for model size reduction of an integrated circuit utilizing net invariants
JP2001318129A (en) * 2000-05-08 2001-11-16 Nec Microsystems Ltd Method for setting test mode, medium storing its program, semiconductor device and electronic apparatus
US20030149927A1 (en) * 2001-02-07 2003-08-07 Seongmoon Wang Low hardware overhead scan based 3-weight weighted random BIST architectures
WO2004104608A1 (en) * 2003-05-23 2004-12-02 Koninklijke Philips Electronics N.V. Automatic test pattern generation
CN104515950A (en) * 2015-01-12 2015-04-15 华南师范大学 Built-in self-testing method and application of integrated circuit
US20160349317A1 (en) * 2015-05-26 2016-12-01 Samsung Electronics Co., Ltd. Method and apparatus for obtaining a maximally compressed verification test set
CN105445646A (en) * 2015-12-14 2016-03-30 国家电网公司 Testing method of analog-digital circuit fault diagnosis based on neural network expert system
CN107102942A (en) * 2017-04-01 2017-08-29 南京邮电大学 A kind of minimum Fault Locating Method based on input domain location of mistake
CN106991051A (en) * 2017-04-05 2017-07-28 西安邮电大学 A kind of test case reduction method based on mutation testing and correlation rule

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
刘思光 等: "结合SE-Tree结构特征的极小碰集求解算法", 《计算机研究与发展》 *
欧阳丹彤 等: "基于矩阵计算极小碰集的启发式算法", 《吉林大学学报（工学版）》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110687433A (en) * 2019-10-23 2020-01-14 吉林大学 Method for reducing integrated circuit test mode set by combining PMS technology
CN110687433B (en) * 2019-10-23 2021-11-12 吉林大学 Method for reducing integrated circuit test mode set by combining PMS technology

Also Published As

Publication number Publication date
CN109490753B (en) 2020-12-08

Similar Documents

Publication Publication Date Title
CN111158967B (en) Artificial intelligence chip testing method, device, equipment and storage medium
CN111833959B (en) Method and device for testing memory, electronic equipment and computer readable storage medium
CN102169846A (en) Method for writing multi-dimensional variable password in parallel in process of testing integrated circuit wafer
CN109490753A (en) A kind of method of combination minimal hitting set reduction integrated circuit testing set of patterns
Mehta et al. Timing-aware multiple-delay-fault diagnosis
CN105701294B (en) Realize the method and system of chip complex engineering modification
CN101464205B (en) Test modal analysis method based on reduced-basis method
CN107966645A (en) A kind of temporal constraint method and device of the sweep test of integrated circuit
CN105893685A (en) VLSI (Very Large Scale Integration) formal verification platform and method
Lee et al. Efficient overdetection elimination of acceptable faults for yield improvement
CN101916305A (en) Method for verifying complex pin chip
CN116302344A (en) Method and system for batch generation of hardware simulation automation process
Takahashi et al. A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits
CN102565685B (en) Logic built-in self-test system
CN102262205B (en) A kind of screen method of test point of test vector source file and shield assembly
US7500165B2 (en) Systems and methods for controlling clock signals during scan testing integrated circuits
CN203573309U (en) Testing structure for embedded system memory
CN112597002A (en) Python script based test vector generation method
CN103605590A (en) Novel built-in system memory testing structure and method
Zhang et al. Cost-driven optimization of coverage of combined built-in self-test/automated test equipment testing
Pomeranz et al. $ z $-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs
CN100592097C (en) IC with on-board characterization unit
Ubar et al. How to Prove that a Circuit is Fault-Free?
Pomeranz et al. Path selection for transition path delay faults
JPS63140969A (en) Test facilitation system

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20201208

Termination date: 20211113

CF01 Termination of patent right due to non-payment of annual fee