DD123129A1 - - Google Patents
Info
- Publication number
- DD123129A1 DD123129A1 DD19018275A DD19018275A DD123129A1 DD 123129 A1 DD123129 A1 DD 123129A1 DD 19018275 A DD19018275 A DD 19018275A DD 19018275 A DD19018275 A DD 19018275A DD 123129 A1 DD123129 A1 DD 123129A1
- Authority
- DD
- German Democratic Republic
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DD19018275A DD123129A1 (en) | 1975-12-16 | 1975-12-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DD19018275A DD123129A1 (en) | 1975-12-16 | 1975-12-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DD123129A1 true DD123129A1 (en) | 1976-11-20 |
Family
ID=5502835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DD19018275A DD123129A1 (en) | 1975-12-16 | 1975-12-16 |
Country Status (1)
| Country | Link |
|---|---|
| DD (1) | DD123129A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3146721A1 (en) * | 1980-11-25 | 1982-09-16 | Nippon Electric Co., Ltd., Tokyo | LOGIC CIRCUIT WITH TEST POSSIBILITY |
| CN109490753A (en) * | 2018-11-13 | 2019-03-19 | 吉林大学 | A kind of method of combination minimal hitting set reduction integrated circuit testing set of patterns |
-
1975
- 1975-12-16 DD DD19018275A patent/DD123129A1/xx unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3146721A1 (en) * | 1980-11-25 | 1982-09-16 | Nippon Electric Co., Ltd., Tokyo | LOGIC CIRCUIT WITH TEST POSSIBILITY |
| CN109490753A (en) * | 2018-11-13 | 2019-03-19 | 吉林大学 | A kind of method of combination minimal hitting set reduction integrated circuit testing set of patterns |
| CN109490753B (en) * | 2018-11-13 | 2020-12-08 | 吉林大学 | Method for reducing integrated circuit test mode set by combining minimum bump |