CN109490753B - Method for reducing integrated circuit test mode set by combining minimum bump - Google Patents
Method for reducing integrated circuit test mode set by combining minimum bump Download PDFInfo
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- CN109490753B CN109490753B CN201811342777.0A CN201811342777A CN109490753B CN 109490753 B CN109490753 B CN 109490753B CN 201811342777 A CN201811342777 A CN 201811342777A CN 109490753 B CN109490753 B CN 109490753B
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The invention relates to a method for reducing an integrated circuit test pattern set by combining minimum impact, belonging to the technical field of digital circuit test. Firstly, generating a test pattern set for a specific circuit by using an automatic test pattern generation tool; then obtaining a detectable fault set for each element (test pattern) in the test pattern set, and generating a matrix between the test pattern and the fault according to the fault set; and finally, generating a mode coverage set corresponding to each fault according to the test mode fault matrix, using the mode coverage set as input, obtaining a minimum test mode set by using a minimum collision set solving method, and verifying the fault coverage rate of the test mode set: re-reading the test pattern set into the tool, and if the coverage rate is reduced, modifying or abandoning the solution; if not, then this minimal set of test patterns is added to the solution space. The invention reduces the test cost in the chip development process and improves the test efficiency.
Description
Technical Field
The invention relates to a method for reducing a test pattern set of an integrated circuit by combining minimum bump, in particular to a method for effectively reducing the scale of the test pattern set in a test pattern set optimization method, belonging to the technical field of circuit testing.
Background
Circuit testing is an important part of the integrated circuit industry, and as the complexity of integrated circuits increases, the complexity of testing becomes more complex, and the testing cost of integrated circuits even accounts for most of the manufacturing cost of chips. In order to solve the increasingly prominent test cost problem, people begin to consider the testability problem in the design stage to ensure the generation of an automatic test mode, and further effectively reduce the test cost of the circuit.
To date, many scholars have studied automatic test pattern generation methods. In 1966, the method D is proposed for the first time by J.Paul Roth, which is the first complete automatic test pattern generation method, and although the calculation complexity of the method is higher, the theoretical significance of the method is still widely accepted. Subsequently, an improvement is made by Goel on the basis of the D method, and a PODEM method is proposed, which well improves the efficiency of calculation. Therefore, the automatic test pattern generation method becomes an important research subject, and a plurality of innovative methods appear, such as the FAN method proposed by Fujiwara and the SOCRATES method proposed by Schulz; hamzaoglu and Patel propose a new technique for accelerating the PODEM method; related methods of binding SAT are also available.
Many of the research results were successfully applied to industrial design, such as TetraMAX ATPG developed by Synopsy, TestKompres by Mentor Graphics, Talus ATPG and Talus ATPGX by Magma and Modus Test Solution by Cadence. And TetraMAX ATPG is the most easily used automatic test pattern generation tool with the strongest function in the industry. TetraMAX can generate the test pattern set with the highest fault coverage in the shortest time for different integrated circuits, and the test pattern set generated by the tool is simultaneously used for research in many other fields in academia.
In order to further reduce the test mode set generated by the automatic test mode generation tool, reduce the scale of the test mode set, reduce the test cost and improve the test efficiency, the invention provides a method for reducing the test mode set by combining a minimum bump set method.
Disclosure of Invention
The invention mainly aims to provide a method for reducing the test mode set of an integrated circuit by combining minimum bump, so that the scale of the test mode set of the integrated circuit is reduced, the test cost in the chip development process is reduced, and the test efficiency is improved.
The following is explained in conjunction with the attached drawings:
the method for reducing the integrated circuit test mode set by combining minimum impact at least comprises the following steps:
the method comprises the following steps: generating a circuit file and a corresponding protocol file required by testing;
step two: generating a fault list and a corresponding test mode set by using an automatic test mode generating tool;
step three: generating a corresponding mode fault matrix according to the test mode set;
step four: obtaining a cluster of a mode coverage set which can be processed by a minimum collision set method according to the mode fault matrix;
step five: reduction of a test pattern set;
step six: and verifying the coverage rate of each reduced minimum test pattern set, sequencing the minimum test pattern sets from small to large according to the lengths of the test pattern sets, and outputting all the minimum test pattern sets.
The method for generating the mode fault matrix at least comprises the following steps:
step 1): separating the set of test patterns into individual test patterns;
step 2): obtaining all faults detectable by each test mode;
step 3): a pattern fault matrix is generated according to a particular order of the fault list.
The method for obtaining the cluster of the pattern coverage set comprises the following steps:
step 4): obtaining a test mode corresponding to each fault according to the mode fault matrix;
step 5): generating a mode coverage set corresponding to each fault by the test mode corresponding to each fault;
step 6): a cluster of pattern coverage sets is generated from all the resulting pattern coverage sets.
The test mode reduction method at least comprises the following steps:
step 7): taking the cluster of the pattern coverage set as the input of the minimum collision set method solution;
step 8): calling a minimum collision set method to solve to obtain a minimum test mode set capable of detecting all faults;
the invention has the beneficial effects that: the invention provides a method for reducing the integrated circuit test pattern set by combining minimum bump, which realizes the reduction of the scale of the test pattern set, reduces the test cost and the test time in the chip development process, further improves the test efficiency and accelerates the chip development speed.
Drawings
FIG. 1 is a schematic diagram of a method for reducing a set of test patterns for an integrated circuit in conjunction with minimal impact;
FIG. 2 is a flow diagram of a method for reducing a set of test patterns for an integrated circuit in conjunction with minimal impact;
Detailed Description
The invention is explained in more detail below by means of specific examples and the attached drawings:
referring to fig. 1 and 2, a method for reducing a set of simplified integrated circuit test patterns in conjunction with minimal impact, comprising at least the steps of:
the method comprises the following steps: generating a circuit file and a corresponding protocol file required by testing;
step two: generating a fault list and a corresponding test mode set by using an automatic test mode generating tool;
step three: generating a corresponding mode fault matrix according to the test mode set;
step four: obtaining a cluster of a mode coverage set which can be processed by a minimum collision set solving method according to the mode fault matrix;
step five: reduction of a test pattern set;
step six: and verifying the coverage rate of each reduced minimum test pattern set, sequencing the minimum test pattern sets from small to large according to the lengths of the test pattern sets, and outputting all the minimum test pattern sets.
Specifically, in the system flow in this example as shown in fig. 2, first, a circuit synthesis tool is used to generate a required circuit file and a corresponding test protocol file for an original circuit file; then, generating a fault list and a corresponding test mode set by using an automatic test mode generation tool; then, generating a corresponding mode fault matrix according to the test mode set; extracting a pattern coverage set from the matrix, and generating a set cluster formed by the pattern coverage set, wherein the set cluster can be processed by a minimum collision set method; in the test mode set reduction and inspection process in the embodiment, a cluster of a mode coverage set is used as input of a minimum bump set method, and all minimum test mode sets are obtained after solving; and finally, verifying the coverage rate of the test pattern sets, verifying the coverage rate of each reduced minimum test pattern set, sequencing the minimum test pattern sets from small to large according to the lengths of the test pattern sets, outputting all the minimum test pattern sets, and ending the method.
The method for generating the mode fault matrix at least comprises the following steps:
step 1): separating the set of test patterns into individual test patterns;
step 2): obtaining all faults detectable by each test mode;
step 3): a pattern fault matrix is generated according to a particular order of the fault list.
TABLE 1
TABLE 2
The test tool obtains a test Pattern set { Pattern 0:, Pattern 1:., Pattern n:. }, which has a fixed data structure, and the test Pattern set is separated according to the characteristics of the data structure, so that individual test patterns { Pattern 0:. }, { Pattern 1:. }, { Pattern n:. Read each individual test Pattern into the tool, generate a fault list { DSf for { Pattern 0:0,NCf1,NCf2,DSf3,DSf4according to the resultsA failure list, resulting in a corresponding mode failure vector of 10011. Such a pattern fault vector may be obtained for each test pattern in the set of test patterns. The pattern failure vectors from the test pattern set generate a pattern failure matrix, as shown in Table 1, where "1" represents test pattern tiCan be covered to the fault fjAnd "0" represents the test pattern tiCan not be covered to fault fj。
The method for obtaining the mode coverage set comprises the following steps:
step 4): obtaining a test mode corresponding to each fault according to the mode fault matrix;
step 5): generating a mode coverage set corresponding to each fault by the test mode corresponding to each fault;
step 6): a cluster of pattern coverage sets is generated from all the resulting pattern coverage sets.
And obtaining a test mode corresponding to each fault according to the mode fault matrix shown in the table 1. E.g. fault f0The corresponding test pattern is t0}. Finally, f is obtained0,f1,f2,f3,f4The corresponding test pattern sets are respectively { t }0},{t1,t2},{t2,t3},{t0,t2,t3And t0,t1}. The pattern coverage sets generated by these test pattern sets are {0}, {1,2}, {2,3}, {0,2,3} and {0,1}, respectively. The cluster of the resulting pattern coverage set is {0}, {1,2}, {2,3}, {0,2,3}, {0,1} }, and as shown in table 2, this cluster of sets constitutes the input to the test pattern reduction method.
The test mode reduction method at least comprises the following steps:
step 7): taking the cluster of the pattern coverage set as the input of the minimum collision set method solution;
step 8): calling a minimum collision set method to solve to obtain a minimum test mode set capable of detecting all faults;
according to the contents in table 2, the cluster of the pattern coverage set is { {0}, {1,2}, {2,3}, {0,2,3}, {0,1} }, and this cluster is used as the minimum collision set methodThe minimal collision method is called to obtain minimal collision sets {0, 2} and {0,1,3} of the set clusters { {0}, {1,2}, {2,3}, {0,2,3}, {0,1} } which can detect all faults, that is, only the minimal collision sets of the test patterns t are needed0And t2Or t is0,t1And t3All faults can be detected and thus are two solutions to the test pattern reduction method, after which two very small sets of test patterns 0,2, and 0,1,3 are read into the tool to verify its validity.
Finally, it should be noted that: although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (4)
1. A method for reducing a set of test patterns for an integrated circuit in conjunction with minimal impact, comprising at least the steps of:
the method comprises the following steps: generating a circuit file and a corresponding protocol file required by testing;
step two: generating a fault list and a corresponding test mode set by using an automatic test mode generating tool;
step three: generating a corresponding mode fault matrix according to the test mode set;
step four: obtaining a cluster of a mode coverage set which can be processed by a minimum collision set method according to the mode fault matrix;
step five: test mode set reduction;
step six: and verifying the coverage rate of each reduced minimum test pattern set, sequencing the minimum test pattern sets from small to large according to the lengths of the test pattern sets, and outputting all the minimum test pattern sets.
2. The method of claim 1, wherein the method of generating the pattern failure matrix in step three comprises at least:
step 1): separating the set of test patterns into individual test patterns;
step 2): obtaining all faults detectable by each test mode;
step 3): a pattern fault matrix is generated according to a particular order of the fault list.
3. The method for reducing the integrated circuit test pattern set with the minimum collision according to the claim 1 or 2, wherein the method for obtaining the cluster of the pattern coverage set in the step four is:
step 4): obtaining a test mode corresponding to each fault according to the mode fault matrix;
step 5): generating a pattern coverage set by the test pattern corresponding to each fault;
step 6): a cluster of pattern coverage sets is generated from all the resulting pattern coverage sets.
4. The method of claim 3 in combination with a minimum impact reduction integrated circuit test pattern set, wherein the test pattern reduction method of step five comprises at least:
step 7): taking the cluster of the pattern coverage set as the input of the minimum collision set method solution;
step 8): and calling a minimum collision set method to solve to obtain a minimum test mode set capable of detecting all faults.
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