CN109478536A - Circuit board, the manufacturing method of circuit board, the manufacturing method of electronic component and electronic component - Google Patents
Circuit board, the manufacturing method of circuit board, the manufacturing method of electronic component and electronic component Download PDFInfo
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- CN109478536A CN109478536A CN201780042267.9A CN201780042267A CN109478536A CN 109478536 A CN109478536 A CN 109478536A CN 201780042267 A CN201780042267 A CN 201780042267A CN 109478536 A CN109478536 A CN 109478536A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Circuit board (1) is with the 2nd layer (200) on the 1st layer (100) and the 1st layer (100) of a face.There are for 1st layer (100) multiple 1st conductor portions (6) and configure resin portion (3) between multiple 1st conductor portions (6) and multiple 1st conductor portions (6) are electrically separated.Have for 2nd layer (200) and is in contact respectively with multiple 1st conductor portions (6) and multiple 2nd conductor portions (4) electrically separated from each other.Multiple 2nd conductor portions (4) are respectively in contact with a part in the face by the 1st layer of (100) side of the 2nd conductor portion (4) with resin portion (3).
Description
Technical field
The present invention relates to circuit board, the manufacturing method of circuit board, the manufacturing methods of electronic component and electronic component.
Background technique
Such as non-patent literature 1 discloses and a kind of QFN (Quad Flat Non-Leaded Package) has been used to use group
The assembling procedure of the QFN of part band.In addition, QFN is one kind of the electronic component of no pin-type, the no pin-type is not leads ends
The structure that son extends outward.Electronic component without pin-type is other than QFN, and there are also the parts for being referred to as SON.
Existing technical literature
Non-patent literature
Non-patent literature 1: Kawai Ji peace, name youngster are friendly macro, " QFN component band ", the report of Hitachi's forming technology, Hitachi
At Industrial Co., Ltd, in July, 2002, No.39, page 17~20
Summary of the invention
Problems to be solved by the invention
However, also having the requirement for the electronic component that high-quality is easily manufactured than previous QFN.
The solution to the problem
Technical solution disclosed herein is a kind of circuit board, which includes the 1st layer；And the 2nd layer, place
In on the 1st layer of a face, the 1st layer has multiple 1st conductor portions and configuration between multiple 1st conductor portions and by multiple 1
The electrically separated resin portion of conductor portion, the 2nd layer has and is in contact respectively with multiple 1st conductor portions and electrically separated from each other multiple the
2 conductor portions, multiple 2nd conductor portions are respectively in contact with a part in the face by the 1st layer of side of the 2nd conductor portion with resin portion.
Technical solution disclosed herein is the manufacturing method of circuit board, and the manufacturing method of the circuit board includes following work
Sequence: a part of the resin base material of the layered structure with the conductor layer on resin base material and resin base material is removed；Pass through
A part of conductor layer is removed, is in contact with a part of resin base material and multiple 2nd conductors electrically separated from each other to be formed
Portion；And it is formed and is in contact respectively with multiple 2nd conductor portions and electrically separated from each other more at the position for eliminating resin base material
A 1st conductor portion.
Technical solution disclosed herein is a kind of electronic component, which includes above-mentioned circuit board；Chip,
It is on the 2nd layer；Lead is electrically connected with chip；And sealing material, by chip and the lead-in wire sealing, chip is connect
Together in the 2nd conductor portion of a part in multiple 2nd conductor portions, lead is by the another part in chip and multiple 2nd conductor portions
The electrical connection of 2nd conductor portion.
Technical solution disclosed herein is the manufacturing method of electronic component, and the manufacturing method of the electronic component includes following work
Sequence: prepare above-mentioned circuit board；Chip is engaged in the 2nd conductor portion of a part in multiple 2nd conductor portions；Using lead by core
Piece is electrically connected with the 2nd conductor portion of another part in multiple 2nd conductor portions；And it is using sealing material that chip and lead is close
Envelope.
The effect of invention
Using technical solution disclosed herein, compared with previous QFN, the electronics zero of high-quality can be easily manufactured by
Part.
Detailed description of the invention
Fig. 1 is the schematic cross sectional views of the circuit board of embodiment.
Fig. 2 is to carry out graphic schematic cross sectional views to an example of the manufacturing method of the circuit board of embodiment.
Fig. 3 is to carry out graphic schematic cross sectional views to an example of the manufacturing method of the circuit board of embodiment.
Fig. 4 is to carry out graphic schematic cross sectional views to an example of the manufacturing method of the circuit board of embodiment.
Fig. 5 is the schematic cross sectional views of the variation of the circuit board of embodiment.
Fig. 6 is the schematic cross sectional views of the electronic component of embodiment.
Fig. 7 is to carry out graphic schematic cross sectional views to an example of the manufacturing method of the electronic component of embodiment.
Fig. 8 is to carry out graphic schematic cross sectional views to an example of the manufacturing method of the electronic component of embodiment.
Fig. 9 is to carry out graphic schematic cross sectional views to an example of the manufacturing method of the electronic component of embodiment.
Figure 10 is the schematic plan of the variation of the circuit board of embodiment.
Figure 11 is the schematic plan of the electronic component of embodiment shown in fig. 6.
Figure 12 is the 1st layer of diagrammatic top of circuit board used in the electronic component of embodiment shown in fig. 6
Figure.
Figure 13 is the schematic cross sectional views for the function and effect for illustrating the circuit board of embodiment.
Figure 14 is the schematic cross sectional views for the function and effect for illustrating the circuit board of embodiment.
Figure 15 is the schematic cross sectional views for the function and effect for illustrating the circuit board of embodiment.
Figure 16 is the schematic cross sectional views of the function and effect of the circuit board and electronic component for illustrating embodiment.
(a1) of Figure 17~(a3) is to carry out graphic schematic sectional to the manufacturing method of the framework in previous QFN
Figure, (b1)~(b5) of Figure 17, which is that an example progress to the manufacturing method of the circuit board of present embodiment is graphic, schematically to be cutd open
View.
(a1) of Figure 18~(a5) is to carry out graphic schematic cross sectional views to the assembling procedure of previous QFN, Figure 18's
(b1), (b2), (b4) and (b5) is to carry out graphic signal to an example of the manufacturing method of the electronic component of present embodiment
Property cross-sectional view.
(a6) of Figure 19~(a8) is to carry out graphic schematic cross sectional views to the assembling procedure of previous QFN, Figure 19's
It (b8) is that graphic schematic cross sectional views are carried out to an example of the manufacturing method of the electronic component of present embodiment.
Specific embodiment
Illustrate embodiment below.In addition, in the attached drawing used in the explanation of embodiment, it is same referring to appended drawing reference
It indicates with a part or equivalent part.
<circuit board>
Fig. 1 shows the schematic cross sectional views of the circuit board of embodiment.As shown in Figure 1, the circuit board 1 of embodiment
The 2nd layer 200 with the 1st layer 100 and on the 1st layer 100 of a face.There are multiple 1st conductor portions 6 and place 1st layer 100
Resin portion 3 between multiple 1st conductor portions 6.The 1st adjacent conductor portion 6 configures spaced apartly.In the 1st adjacent conductor
Interval between portion 6 is configured with resin portion 3.The 1st adjacent conductor portion 6 is electrically separated from each other using the resin portion 3 of insulating properties.
There are multiple 2nd conductor portions 4, the 2nd adjacent conductor portion 4 is spaced apart the configuration of 5 ground of opening portion for 2nd layer 200.Adjacent
Component is not configured in opening portion 5 between 2nd conductor portion 4, makes a part exposure of the 1st layer 100 of resin portion 3.It leads adjacent the 2nd
Body portion 4 is electrically separated from each other using opening portion 5.
Multiple 2nd conductor portions 4 are electrically connected with being in contact with respective the 1st opposite conductor portion 6 of multiple 2nd conductor portions 4 respectively
It connects.In addition, multiple 2nd conductor portions 4 are respectively connected with a part in the face by the 1st layer of 100 side of the 2nd conductor portion 4 with resin portion 3
Touching.In addition, circuit board 1 is applied to the example of wire bonding mode by following explanation, but circuit board 1 can be also applied to
Flip-chip bond mode.
<manufacturing method of circuit board>
Hereinafter, illustrating the one of the manufacturing method of the circuit board 1 of embodiment referring to the schematic cross sectional views of Fig. 2~Fig. 5
Example.Firstly, as shown in Fig. 2, preparing the resin base material 300 with insulating properties and the conductor in the one side of resin base material 300
The layered structure 500 of layer 400.Resin base material 300 is able to use such as polyimides, and conductor layer 400 is able to use such as copper.
Then, as shown in figure 3, forming opening 7 by a part for removing resin base material 300.Here, with for Fig. 1
Shown in the corresponding part in region of multiple 1st conductor portions 6 configuration form opening 7, resin base material 300 becomes shown in FIG. 1
Resin portion 3.In the exposure conductor layer 400 of opening 7.The removal of a part of resin base material 300 can be carried out for example, by etching etc..
Then, as shown in figure 4, forming opening portion 5 by a part for removing conductor layer 400.Here, 5 shape of opening portion
A part as remaining conductor layer 400 is in contact with a part of resin base material 300.Conductor layer 400 is not removed
Part becomes multiple 2nd conductor portions 4 shown in FIG. 1.The removal of a part of conductor layer 400 can for example, by etching etc. into
Row.
Then, the 1st conductor portion 6 is formed on each surface for being exposed to opening 7 of conductor layer 400 shown in Fig. 4, thus
Produce the circuit board of embodiment shown in FIG. 1.1st conductor portion 6 for example can be by the way that copper to be plated in conductor layer 400
Etc. modes formed.
In addition, metal layer 8 can also be formed in the 2nd conductor portion 4 as shown in the schematic cross sectional views of Fig. 5.Metal layer 8
Such as it can be by the way that by the laminated body plating of nickel and gold, modes are formed in the 2nd conductor portion 4 etc..Metal layer 8 can be for example
It is formed as improved the internuncial purpose being connected with by the lead of wire bonding.
In addition, as shown in figure 5, can also to the 1st conductor portion 6 the back side (the 1st conductor portion 6 with where the 2nd conductor portion 4
The face of that opposite side of side) implement the processing of external connection to form protective film 18.Protective film 18 can for example pass through by
The laminated body or tin plating of nickel and gold are formed in the 2nd conductor portion 4, or by utilizing organic protective film by the 1st conductor portion 6
The back side covering and formed.Protective film 18 can be for such as wetability of the raising solder relative to the back side of the 1st conductor portion 6
And/or inhibits the purpose of the oxidation at the back side of the 1st conductor portion 6 and formed.
<electronic component>
Fig. 6 indicates the schematic cross sectional views of the electronic component of embodiment.Embodiment shown in fig. 6 without pin-type
Multiple 2nd conductor portions 4 of the circuit board 101 of embodiment used in electronic component have the core for engaging with chip 12
Chip bonding portion the 2nd conductor portion 4 of center (Fig. 6) and for engage with lead 11 wire bond (Fig. 6 in addition to central
The 2nd conductor portion 4 except 2nd conductor portion 4).In addition, in the following description, in an electronic component equipped with a core
The structure of piece is illustrated, but also can carry multiple chips in an electronic component.
That is, as shown in fig. 6, the electronic component of embodiment includes the circuit board 101 of embodiment；Chip 12, is borrowed
In multiple 2nd conductor portions 4 for the circuit board 101 that the assistant director of a film or play is electrical or dielectric adhesives 13 is electrically connected to embodiment
The 2nd conductor portion 4 of a part (the 2nd conductor portion 4 in the center of Fig. 6)；Lead 11, by metal layer 8 by the electrode of chip 12
With 4 (the 2nd conductor other than the 2nd conductor portion 4 in center of Fig. 6 of the 2nd conductor portion of another part of multiple 2nd conductor portions 4
Portion 4) electrical connection；And the sealing material 10 of insulating properties, lead 11 and chip 12 are sealed.Lead 11 and chip 12 distinguish energy
Enough use known lead and chip.Sealing material 10 is able to use such as epoxy resin.If adhesives 13 is for example
It is conductive, then it is able to use the conductive pastes such as silver paste.
In addition, being equipped with notch 9 between the chip bonding portion and wire bond of the 2nd conductor portion 4.In this way, by core
Notch 9 is set between chip bonding portion and wire bond, can be blocked using notch 9 and use 13 joint chip of adhesives
The adhesives 13 that 12 outside of chip is flowed out to when 12 can prevent adhesives 13 from flowing out to than the position of notch 9 in the outer part.
In addition, during notch 9 can be set as shown in the schematic plan of aftermentioned Figure 11 will not making under vertical view visual angle
The electrically separated shape of 2nd conductor layer 4 of centre.If being set as such shape, can with use that Fig. 4 illustrates, removal conductor
A part of layer 400 forms notch 9 come the identical process of process for forming opening portion 5.In addition, electronic component shown in Fig. 6
In, it also can substitute circuit board 101 and be constituted using Fig. 1 of not set notch 9 or circuit board shown in fig. 51.
<manufacturing method of electronic component>
Hereinafter, illustrating the one of the manufacturing method of the electronic component of embodiment referring to the schematic cross sectional views of Fig. 7~Fig. 9
Example.Firstly, preparing circuit board 101 shown in fig. 6.In circuit board 101 shown in Fig. 6, becoming wire bond
There is metal layer 8 in 2nd conductor portion 4, and there is protective film 18 on the back side of the 1st conductor portion 6, in the core of the 2nd conductor portion 4
There is notch 9, in addition to this, circuit board 101 has and embodiment shown in FIG. 1 between chip bonding portion and wire bond
The identical construction of circuit board 1.
Then, as shown in fig. 7, chip 12 to be bonded on to the wiring base of embodiment shown in fig. 6 by adhesives 13
On the 2nd conductor portion 4 as chip bonding portion of plate 101.Here, chip 12 be bonded on two notches 9 relative to each other it
Between the 2nd conductor portion 4 as chip bonding portion on.
Then, as shown in figure 8, the wire bonding by using lead 11 by the electrode of chip 12 and becomes wire bond
The 2nd conductor portion 4 on metal layer 8 be electrically connected.
Then, as shown in figure 9, by the way that chip 12 and lead 11 are sealed using sealing material 10, so as to produce
The electronic component of embodiment shown in fig. 6.
In addition it is also possible to use cross-sectional configuration such as Figure 10 of the circuit board 101 of embodiment as shown in Figure 6
Shown in schematic plan like that respectively vertical and horizontal continuously configure it is multiple made of embodiment circuit board
1001, to manufacture the electronic component of embodiment shown in fig. 6.In the circuit board 1001 of embodiment shown in Fig. 10,
Respectively there is construction identical with circuit board 101 shown in fig. 6 by the quadrangle that the dotted line of Figure 10 surrounds, which exists respectively
Vertical and horizontal are formed by connecting as duplicate construction.That is, one of quadrangle enclosed by the dotted line of Figure 10 and other each four sides
At least the 1st conductor portion 6 of shape is identical with the pattern of the 2nd conductor portion 4, which repeats in machine and transverse direction respectively.
By using circuit board 1001 shown in Fig. 10, embodiment shown in fig. 6 can be more efficiently manufactured
Electronic component.That is, chip 12 to be bonded on to multiple 2nd conductors as chip bonding portion of circuit board 1001 shown in Fig. 10
On portion 4 is respective, after chip 12 is carried out wire bonding with the 2nd conductor portion 4 for becoming wire bond using lead 11, benefit
Multiple chips 12 and the unification of lead 11 are sealed with sealing material 10.Then, by circuit board 1001 together with sealing material 10 1
It rises and cuts off and monolithic turns to individual electronic component, so as to once manufacture multiple electronic components.
Figure 11 indicates the schematic plan of the electronic component of embodiment shown in fig. 6.In addition, Figure 12 indicates Figure 11's
1st layer of schematic plan of the circuit board of the part surrounded by dotted line 111.The electronics zero of embodiment shown in Figure 11
The setting position of the chip bonding portion 4a of 2nd electric conductor 4 of part is corresponding with the position of Figure 12 surrounded by dotted line 4a.In addition,
The wire bond 4b of 2nd electric conductor 4 of the electronic component of embodiment shown in Figure 11 setting position and Figure 12 by void
The position that line 4b is surrounded is corresponding.In addition, for ease of description, merely illustrating setting for a wire bond 4b in Figure 12
Set position.
As is illustrated by figs. 11 and 12, the chip bonding portion 4a of the 2nd electric conductor 4 of the electronic component of embodiment and lead connect
Conjunction portion 4b is in contact with the 1st layer of circuit board of the 1st electric conductor 6 respectively, and is also in contact with resin portion 3.
<function and effect>
In the present embodiment, terminal can be imperceptibly formed into for example, by etching of resin base material 300 etc.
It the part (in the 1st rectangular-shaped conductor portion 6 that the periphery of Figure 12 configures spaced apartly) of 1st conductor portion 6 therefore can be with
The spacing (interval adjacent terminal between be less than 0.4mm) narrower than previous QFN forms terminal.As a result, in the present embodiment,
Number of terminals can be increased compared with previous QFN, can be realized more pins, therefore, can be realized the electronics zero of no pin-type
The miniaturization of part and high performance.
In addition, by being equivalent to interior 51 He of pin shown in Figure 11 using the circuit board setting for being patterned in embodiment
The part of outer pin 52 from without lead 11 is engaged in outer pin 52, but is engaged in the closer lead of off-chip piece 12 and connects
Conjunction portion 4b.Thereby, it is possible to shorten the length of lead 11, it therefore, can be improved the reliability of wire bonding, realize without pin
The high-quality of the electronic component of type.
In addition, such as shown in the schematic cross sectional views of Figure 13 like that, becoming the 2nd electric conductor 4 of chip bonding portion just
When lower section is resin portion 3, it is very difficult that the heat that chip 12 issues, which is released by resin portion 3 to outside,.But at this
In embodiment, such as shown in FIG. 6, becoming being arranged right below and the 2nd for the 2nd electric conductor 4 of chip bonding portion
The 1st electric conductor 6 that electric conductor 4 is in contact.Thus, in the present embodiment, the heat that can easily make chip 12 issue is passed through
The 2nd electric conductor 4 as chip bonding portion is released with the 1st electric conductor 6 immediately below it to outside, and therefore, this point facilitates
Realize the high-quality of electronic component.
In addition, such as Figure 13~as shown in Figure 15, the underface for becoming the 2nd electric conductor 4 of wire bond is to open
When mouth 7, since the 2nd electric conductor 4 when lead 11 carries out wire bonding as wire bond bounces, cause under zygosity
Drop.But in the present embodiment, such as shown in Figure 16, become wire bond the 2nd electric conductor 4 just under
Side is equipped with the 1st electric conductor 6 being in contact with the 2nd electric conductor 4.Thus, it is possible to be led using the 1st of the underface of the 2nd electric conductor 4 the
Electric body 6 reinforces the intensity of the 2nd electric conductor 4, thus, it is also possible to by inhibiting the generation when lead 11 carries out wire bonding
2nd electric conductor 4 bounces, to inhibit the decline of zygosity.
In addition, such as Figure 13~as shown in Figure 15, the underface for becoming the 2nd electric conductor 4 of wire bond is to open
It is larger to the damage for the 2nd electric conductor 4 application for becoming wire bond when lead 11 carries out wire bonding when mouth 7.But
In the present embodiment, such as shown in Figure 16, becoming being arranged right below and being somebody's turn to do for the 2nd electric conductor 4 of wire bond
The 1st electric conductor 6 that 2nd electric conductor 4 is in contact.Thus, it is possible to be added using the 1st electric conductor 6 of the underface of the 2nd electric conductor 4
Therefore the intensity of strong 2nd electric conductor 4 can be reduced when lead 11 carries out wire bonding to caused by the 2nd electric conductor 4
Damage.
In addition, such as Figure 13~as shown in Figure 15, the underface for becoming the 2nd electric conductor 4 of wire bond is to open
When mouth 7, solder void is generated in the secondary installing of electronic component sometimes and causes to install bad.Further, since the 2nd electric conductor
4 underface is opening 7, and therefore, in secondary installing, solder enters opening 7 sometimes, can not be properly formed fillet, cause
Installation strength decline.But in the present embodiment, such as shown in FIG. 6, by becoming the 2nd of wire bond
The secondary installing for being arranged right below the 1st electric conductor 6 being in contact with the 2nd electric conductor 4, being able to suppress at them of electric conductor 4
When lead to the problem of.
(a1) of Figure 17~(a3) indicates to carry out graphic schematic sectional to the manufacturing method of the framework of previous QFN
Figure, (b1)~(b5) of Figure 17 indicate to carry out an example of the manufacturing method of the circuit board of present embodiment graphic schematic
Cross-sectional view.In addition, framework is also referred to as leadframe.
In previous QFN, a part of framework 40 shown in (a1) of Figure 17 is set as shown in (a2) of Figure 17
After setting opening portion 5, as shown in (a3) of Figure 17, being formed on the surface of a part of framework 40 includes silver-colored metal layer 8.Cause
This, in previous QFN, there are the surface of framework 40 be exposed to atmosphere and occur aoxidize so that cause the service life of framework 40 to shorten
The problem of.On the other hand, in the present embodiment, as shown in (b5) of Figure 17, by covering the 1st conductor 6 using protective film 18
The back side, so that the oxidation of the 1st conductor 6 can be effectively inhibited compared with previous QFN.In addition, in previous QFN,
When opening portion 5 is set as shown in (a2) of Figure 17, it is formed in framework 40 for mechanically connected linking part, to prevent frame
Each structural element of body 40 separates.
In addition, needing to process the framework 40 thicker than the circuit board of embodiment, fine processing in previous QFN
More difficult, therefore, it is impossible to increase number of terminals, more pins are restricted.On the other hand, in the present embodiment, can pass through
It processes relatively thin resin base material 300 and conductor layer 400 respectively to form terminal, therefore, is able to carry out finer processing, with
Previous QFN is compared, and can increase number of terminals.In addition, (b1) of Figure 17~(b3) and (b5) are corresponding with Fig. 2~Fig. 5 respectively,
(b4) of Figure 17 is corresponding with Fig. 1, therefore omits the explanation of (b1)~(b5) of Figure 17.
(a6) of (a1) of Figure 18~(a5) and Figure 19~(a8) indicates to carry out the assembling procedure of previous QFN graphic
Schematic cross sectional views, (b1), (b2), (b4) and (b5) of Figure 18 and (b8) of Figure 19 indicate the electronics zero to present embodiment
An example of the manufacturing method of part carries out graphic schematic cross sectional views.
In addition, (b8) of (b1) of Figure 18, (b2), (b4) and (b5) and Figure 19 respectively indicate the electronics zero of embodiment
(a1), (a2), (a4) in the manufacturing process of an example of the manufacturing method of part, with Figure 18 of the assembling procedure of previous QFN
The corresponding process of (a8) of (a5) and Figure 19.
In the assembling procedure of previous QFN, as shown in (a1) of Figure 18,12 chip of chip is connect by adhesives 13
Together in framework 40, then as shown in (a2) of Figure 18, wire bonding is carried out to lead 11.But in the assembling work of previous QFN
In sequence, the top of terminal is not secured to other components, therefore there is a problem of that zygosity is bad.On the other hand, in this embodiment party
In formula, a part for becoming the 2nd electric conductor 4 of terminal is in contact with resin portion 3, therefore wire bonding is stablized, and zygosity improves.
As a result, in the present embodiment, the electronic component without pin-type of high-quality can be produced.
In addition, as shown in (a3) of Figure 18, being needed using QFN component band 41 in the assembling procedure of previous QFN.
On the other hand, in the present embodiment, it is not necessary to use QFN component band 41, therefore can reduce work hours, and can reduce with
The comparable fee of material of expense of QFN component band 41.As a result, in the present embodiment, with the assembling procedure phase of previous QFN
Than with simple process and the electronic component without pin-type can be manufactured with low cost out.
In addition, as shown in (a4) of Figure 18, being sealed using sealing material 10 in the assembling procedure of previous QFN
After process, as shown in (a5) of Figure 18, process is marked to sealing material 10, but for relatively thin QFN component band
41, there are problems that sealing resin leaks in the sealing process shown in (a4) of Figure 18.On the other hand, in present embodiment
In, due to the circuit board with embodiment, such problems will not be generated.
In addition, in the assembling procedure of previous QFN, as shown in (a6) of Figure 19, need QFN with component band 41 from frame
Body 40 is removed, and as shown in (a7) of Figure 19, needs in the covering of the back side of framework 40 to include the protective film 180 of tin.On the other hand, exist
In present embodiment, it is not necessary to carry out these processes, therefore can reduce work hours.
In addition, as shown in (a8) of Figure 19, turn to by cutting monolithic in the assembling procedure of previous QFN
The process of individual electronic component, but since the width for the framework 40 cut becomes larger, therefore, it is necessary to one side to be ground framework 40 1
Side carries out singualtion.As a result, overlap can be generated in the cut-off parts of framework 40 sometimes, lead to the quality of electronic component not
It is good.On the other hand, in the present embodiment, fine processing, therefore energy can be carried out to the 1st conductor portion 6 and the 2nd conductor portion 4
Enough reduce the width of the 1st conductor portion 6 and the 2nd conductor portion 4 at cut-off parts.As a result, turning to individual electronics in monolithic
The 1st conductor portion 6 and the 2nd conductor portion 4 need not be ground, can be cut by pressurizeing when part, therefore can reduced winged
The generation on side.As a result, in the present embodiment, compared with the assembling procedure of previous QFN, high-quality can be produced
Electronic component without pin-type.
It remarks additionally herein.In previous QFN, as described above, the linking part that can be mechanically attached is set
In framework 40, to prevent each structural element of framework 40 from separating.The linking part be formed in the dotted line of such as Figure 10 shown in
Divide comparable position.Also, in the operation of the manufacturing process of electronic component, it is desirable that the degree that each structural element will not separate
Mechanical strength, therefore the wider width of linking part.The wider width is cut by using the cutting mode of cutter
Linking part, therefore it is easy to produce overlap.In addition, the service life for the consumables of cutting such as cutter also shortens.
On the other hand, in the present embodiment, do not need substantially for mechanically connected linking part.In addition, making
With Fig. 5 illustrate opening 7 formed the 1st conductor portion using plating in the case where, can be in each circuit board 101 of such as Figure 10
Boundary section and outer peripheral portion (part shown in dotted lines in Figure 10) form the linking part that is formed by conductive layer 400, will be more
The conductive layer 400 of the part of a outer pin 52 as Figure 11 is electrically connected.In this case, the width of linking part is can be electroplated
Degree conducting, therefore can be relatively narrow.Thus, even if cutting off the width by using the cutting mode of cutter
Relatively narrow linking part is not easy to produce overlap compared with previous QFN.In addition, cutter etc. are used for compared with previous QFN
The service life of the consumables of cutting extends.
As above, according to the present embodiment, compared with previous QFN, number of terminals can be increased.In addition, with previous
QFN compare, with simple process and the electronic component of high-quality can be manufactured with low cost out.In addition, with previous QFN phase
Than the electronic component of high-quality can be easily manufactured by.
Embodiment is illustrated as above, but also plans the structure of appropriately combined the respective embodiments described above at the beginning.
It is believed that all aspects of embodiment of disclosure are all illustrations, rather than restrictive content.This hair
Bright range is embodied by claims rather than above description, it is intended to encompass in the meaning and model with claims equalization
Being had altered in enclosing.
Description of symbols
1,101,1001, circuit board；3, resin portion；4, the 2nd conductor portion；4a, chip bonding portion；4b, wire bond；
5, opening portion；6, the 1st conductor portion；7, it is open；8, metal layer；9, notch；10, sealing material；11, lead；12, chip；13, it glues
Connect material；18, protective film；40, framework；41, QFN component band；51, interior pin；52, outer pin；100, the 1st layer；111, empty
Line；200, the 2nd layer；300, resin base material；400, conductor layer；500, layered structure.
Claims (11)
1. a kind of circuit board, wherein
The circuit board includes
1st layer；And
2nd layer, on described 1st layer of a face,
Described 1st layer there are multiple 1st conductor portions and configuration to lead between the multiple 1st conductor portion and by the multiple 1st
The electrically separated resin portion in body portion,
Described 2nd layer has and is in contact respectively with the multiple 1st conductor portion and multiple 2nd conductor portions electrically separated from each other,
The multiple 2nd conductor portion is respectively with a part in the face by the 1st layer of side of the 2nd conductor portion and the resin
Portion is in contact.
2. circuit board according to claim 1, wherein
2nd conductor portion is with the chip bonding portion for engaging with chip and for the wire bond with wire bonding.
3. circuit board according to claim 2, wherein
Also there is metal layer on the wire bond.
4. circuit board according to claim 1, wherein
Also there is protective film on the face of that side opposite with side where the 2nd conductor portion of the 1st conductor portion.
5. circuit board according to claim 1, wherein
The circuit board is made of the pattern of multiple 1st conductor portions and the pattern arrangement of multiple 2nd conductor portions.
6. a kind of manufacturing method of circuit board, wherein
The manufacturing method of the circuit board includes following process:
By a part of the resin base material of the layered structure with the conductor layer on resin base material and the resin base material
Removal；
By removing a part of the conductor layer, it is in contact with a part of the resin base material and electricity point each other to be formed
From multiple 2nd conductor portions；And
It is formed and is in contact respectively with the multiple 2nd conductor portion and electrically separated from each other at the position for eliminating the resin base material
Multiple 1st conductor portions.
7. the manufacturing method of circuit board according to claim 6, wherein
The manufacturing method of the circuit board further includes the process that metal layer is formed in the 2nd conductor portion.
8. the manufacturing method of circuit board according to claim 6 or 7, wherein
The manufacturing method of the circuit board further includes implementing external connection at least part of the multiple 1st conductor portion
The process of processing.
9. a kind of electronic component, wherein
The electronic component includes
Circuit board according to any one of claims 1 to 5；
Chip, on described 2nd layer；
Lead is electrically connected with the chip；And
Sealing material, by the chip and the lead-in wire sealing,
The chip is engaged in the 2nd conductor portion of a part in the multiple 2nd conductor portion,
The chip is electrically connected by the lead with the 2nd conductor portion of another part in the multiple 2nd conductor portion.
10. a kind of manufacturing method of electronic component, wherein
The manufacturing method of the electronic component includes following process:
Prepare circuit board according to any one of claims 1 to 4；
Chip is engaged in the 2nd conductor portion of a part in the multiple 2nd conductor portion；
The chip is electrically connected with the 2nd conductor portion of another part in the multiple 2nd conductor portion using lead；And
Using sealing material by the chip and the lead-in wire sealing.
11. the manufacturing method of electronic component according to claim 10, wherein
The manufacturing method of the electronic component further includes the process for cutting off the circuit board to carry out singualtion.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016-136037 | 2016-07-08 | ||
| JP2016136037A JP6333894B2 (en) | 2016-07-08 | 2016-07-08 | Wiring board, wiring board manufacturing method, electronic component, and electronic component manufacturing method |
| PCT/JP2017/014101 WO2018008214A1 (en) | 2016-07-08 | 2017-04-04 | Wiring board, method for manufacturing wiring board, electronic component, and method for manufacturing electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109478536A true CN109478536A (en) | 2019-03-15 |
Family
ID=60912065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201780042267.9A Pending CN109478536A (en) | 2016-07-08 | 2017-04-04 | Circuit board, the manufacturing method of circuit board, the manufacturing method of electronic component and electronic component |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JP6333894B2 (en) |
| KR (1) | KR102254999B1 (en) |
| CN (1) | CN109478536A (en) |
| MY (1) | MY192589A (en) |
| TW (1) | TWI650051B (en) |
| WO (1) | WO2018008214A1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005116909A (en) * | 2003-10-10 | 2005-04-28 | Hitachi Cable Ltd | Electronic device and wiring board used therefor |
| CN1748308A (en) * | 2003-02-10 | 2006-03-15 | 斯盖沃克斯瑟路申斯公司 | Semiconductor die package with reduced inductance and reduced die attach flow out |
| JP2011029518A (en) * | 2009-07-28 | 2011-02-10 | Shindo Denshi Kogyo Kk | Flexible printed wiring board, semiconductor device, and method for manufacturing the same |
| CN103227275A (en) * | 2012-01-25 | 2013-07-31 | 新光电气工业株式会社 | Wiring substrate, light emitting device, and manufacturing method of wiring substrate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003303859A (en) * | 2002-04-10 | 2003-10-24 | Hitachi Cable Ltd | Tape carrier for semiconductor device and its manufacturing method |
-
2016
- 2016-07-08 JP JP2016136037A patent/JP6333894B2/en active Active
-
2017
- 2017-04-04 CN CN201780042267.9A patent/CN109478536A/en active Pending
- 2017-04-04 MY MYPI2019000001A patent/MY192589A/en unknown
- 2017-04-04 KR KR1020187036756A patent/KR102254999B1/en active IP Right Grant
- 2017-04-04 WO PCT/JP2017/014101 patent/WO2018008214A1/en active Application Filing
- 2017-04-10 TW TW106111861A patent/TWI650051B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1748308A (en) * | 2003-02-10 | 2006-03-15 | 斯盖沃克斯瑟路申斯公司 | Semiconductor die package with reduced inductance and reduced die attach flow out |
| JP2005116909A (en) * | 2003-10-10 | 2005-04-28 | Hitachi Cable Ltd | Electronic device and wiring board used therefor |
| JP2011029518A (en) * | 2009-07-28 | 2011-02-10 | Shindo Denshi Kogyo Kk | Flexible printed wiring board, semiconductor device, and method for manufacturing the same |
| CN103227275A (en) * | 2012-01-25 | 2013-07-31 | 新光电气工业株式会社 | Wiring substrate, light emitting device, and manufacturing method of wiring substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2018006702A (en) | 2018-01-11 |
| JP6333894B2 (en) | 2018-05-30 |
| WO2018008214A1 (en) | 2018-01-11 |
| KR20190025835A (en) | 2019-03-12 |
| TW201804881A (en) | 2018-02-01 |
| KR102254999B1 (en) | 2021-05-24 |
| MY192589A (en) | 2022-08-29 |
| TWI650051B (en) | 2019-02-01 |
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Application publication date: 20190315 |