JP2005116909A - Electronic device and wiring board used therefor - Google Patents

Electronic device and wiring board used therefor Download PDF

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JP2005116909A
JP2005116909A JP2003351493A JP2003351493A JP2005116909A JP 2005116909 A JP2005116909 A JP 2005116909A JP 2003351493 A JP2003351493 A JP 2003351493A JP 2003351493 A JP2003351493 A JP 2003351493A JP 2005116909 A JP2005116909 A JP 2005116909A
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wiring board
main surface
insulating substrate
electronic device
tin
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Satoshi Chinda
聡 珍田
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA

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  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To enable an electronic device where an electronic part is mounted on a wiring board to be reduced in thickness and to be restrained from increasing in manufacturing cost. <P>SOLUTION: The electronic device is equipped with the wiring board where a conductor pattern is formed on its first main surface, the chip-shaped electronic part mounted on the first main surface of the wiring board, and connection conductors which electrically connect the conductor pattern formed on the wiring board to the electrodes of the chip-shaped electronic part. Openings are provided to the insulating board leaving opening ends on its first main surface and rear surface (hereafter referred to as a second main surface), the opening ends on the first main surface are stopped up with the conductor pattern, and the openings are filled up with conductive members formed of one of copper, nickel, gold, silver, tin, their alloys and conductive paste. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、電子装置及び電子装置に用いる配線板に関し、特に、高周波で動作する電子装置に適用して有効な技術に関するものである。   The present invention relates to an electronic device and a wiring board used for the electronic device, and more particularly to a technique effective when applied to an electronic device operating at a high frequency.

従来、絶縁基板の表面に導体パターンを設けた配線板（インターポーザ）上に、チップ状の電子部品を実装した電子装置がある。前記チップ状の電子部品には、例えば、ＩＣ（Integrated Circuit）やＬＳＩ（Large Scale Integrated Circuit）のような半導体チップ、コンデンサや抵抗のような受動素子等がある。また、前記電子装置で用いる配線板（インターポーザ）には、大きく分けて、片面配線板と両面配線板の２種類の配線板がある。   2. Description of the Related Art Conventionally, there is an electronic device in which chip-shaped electronic components are mounted on a wiring board (interposer) provided with a conductor pattern on the surface of an insulating substrate. Examples of the chip-shaped electronic component include a semiconductor chip such as an IC (Integrated Circuit) and an LSI (Large Scale Integrated Circuit), a passive element such as a capacitor and a resistor. Further, the wiring boards (interposers) used in the electronic device are roughly classified into two types of wiring boards, a single-sided wiring board and a double-sided wiring board.

前記片面配線板は、前記絶縁基板の第１主面、例えば、前記電子部品を実装する面に導体パターンが設けられている。また、前記絶縁基板には、前記第１主面とその裏面（以下、第２主面と称する）に開口端を有し、前記第１主面側の開口端が前記導体パターンでふさがれた開口部（ブラインドビアホール）が設けられている。前記片面配線板は、前記電子装置のうち、例えば、ＢＧＡ（Ball Grid Array）やＣＳＰ（Chip Size/Scale Package）と呼ばれる形態の半導体装置で多く用いられる。前記片面配線板を用いて前記ＢＧＡあるいはＣＳＰと呼ばれる半導体装置を製造するときには、前記絶縁基板の第１主面上に前記電子部品を実装し、前記第２主面側から、前記開口部を通して前記導体パターンと電気的に接続されるボール状の外部端子を形成する。   The single-sided wiring board is provided with a conductor pattern on a first main surface of the insulating substrate, for example, a surface on which the electronic component is mounted. Further, the insulating substrate has an opening end on the first main surface and the back surface thereof (hereinafter referred to as a second main surface), and the opening end on the first main surface side is covered with the conductor pattern. An opening (blind via hole) is provided. The single-sided wiring board is often used in a semiconductor device of a form called BGA (Ball Grid Array) or CSP (Chip Size / Scale Package) among the electronic devices. When manufacturing the semiconductor device called the BGA or CSP using the single-sided wiring board, the electronic component is mounted on the first main surface of the insulating substrate, and the second main surface side is passed through the opening. A ball-like external terminal electrically connected to the conductor pattern is formed.

また、前記両面配線板は、前記絶縁基板の第１主面及び第２主面に導体パターンが設けられている。このとき、前記第１主面の導体パターンと前記第２主面の導体パターンは、スルーホールやビアにより電気的に接続されている。前記両面配線板は、前記電子装置のうち、例えば、ＬＧＡ（Land Grid Array）と呼ばれる形態の半導体装置や、前記受動素子を用いた電子装置で多く用いられる。前記両面配線板を用いて前記ＬＧＡと呼ばれる半導体装置、あるいは前記受動素子を用いた電子装置を製造するときには、例えば、前記絶縁基板の第１主面上に前記電子部品を実装する。このとき、前記絶縁基板の第２主面に設けられた導体パターンは、そのまま外部端子（ランド）として用いられる。また、前記両面配線板の場合、前記絶縁基板の第２主面に設けられた導体パターン上に、ボール状の外部端子を設けて、前記ＢＧＡやＣＳＰと呼ばれる半導体装置にすることもある。   In the double-sided wiring board, conductor patterns are provided on the first main surface and the second main surface of the insulating substrate. At this time, the conductor pattern on the first main surface and the conductor pattern on the second main surface are electrically connected by a through hole or a via. Of the electronic devices, the double-sided wiring board is often used in, for example, a semiconductor device called an LGA (Land Grid Array) or an electronic device using the passive element. When manufacturing the semiconductor device called the LGA or the electronic device using the passive element using the double-sided wiring board, for example, the electronic component is mounted on the first main surface of the insulating substrate. At this time, the conductor pattern provided on the second main surface of the insulating substrate is used as it is as an external terminal (land). In the case of the double-sided wiring board, a ball-shaped external terminal may be provided on a conductor pattern provided on the second main surface of the insulating substrate to form a semiconductor device called the BGA or CSP.

また、前記コンデンサ素子等の受動素子を用いた電子装置では、例えば、前記絶縁基板の前記コンデンサ素子を実装する面に段差を設けた立体的な両面配線板を用いられることが多い（例えば、特許文献１、特許文献２を参照。）。   In addition, in an electronic device using a passive element such as the capacitor element, for example, a three-dimensional double-sided wiring board in which a step is provided on a surface of the insulating substrate on which the capacitor element is mounted is often used (for example, patents). (Refer to Literature 1 and Patent Literature 2).

しかしながら、前記片面配線板を用いた前記ＢＧＡやＣＳＰと呼ばれる半導体装置（電子装置）は、マザーボード等のプリント配線板に実装したときに、前記ボール状の外部端子の分だけ厚くなってしまうという問題がある。   However, the semiconductor device (electronic device) called BGA or CSP using the single-sided wiring board becomes thicker by the amount of the ball-shaped external terminal when mounted on a printed wiring board such as a mother board. There is.

また、前記両面配線板を用いた前記ＬＧＡと呼ばれる半導体装置や、前記受動素子を用いた電子装置の場合、前記絶縁基板の第１主面及び第２主面の両面に導体パターンを形成するので、前記配線板の製造工程が増え、製造コストが上昇するという問題があった。   In the case of a semiconductor device called LGA using the double-sided wiring board and an electronic device using the passive element, conductor patterns are formed on both the first main surface and the second main surface of the insulating substrate. There is a problem that the manufacturing process of the wiring board is increased and the manufacturing cost is increased.

また、前記電子装置の配線板に用いる絶縁基板には、従来、ポリイミドテープやガラス布基材エポキシ樹脂基板のような材料が用いられている。しかしながら、近年では、前記電子装置の動作の高速化（高周波化）が進んでおり、前記ポリイミドテープや前記ガラス布基材エポキシ樹脂基板を用いた配線板では、動作周波数が数GHz（ギガヘルツ）から数十GHzの高周波領域で電気特性が劣化しやすいという問題があった。   Conventionally, materials such as a polyimide tape and a glass cloth base epoxy resin substrate are used for the insulating substrate used for the wiring board of the electronic device. However, in recent years, the operation of the electronic device has been accelerated (high frequency), and the operation frequency of the wiring board using the polyimide tape or the glass cloth base epoxy resin substrate is from several GHz (gigahertz). There is a problem that electrical characteristics are likely to deteriorate in a high frequency range of several tens of GHz.

前記従来の配線板において、高周波領域での電気特性の劣化を防ぐ方法としては、例えば、マイクロストリップのように、絶縁基板の第１主面に信号伝送用の配線（導体パターン）を設け、第２主面にグラウンドプレーンを設ける方法がある。しかしながら、前記マイクロストリップを有する配線板は、前記両面配線板と同様で、配線板の製造工程が増え、製造コストが上昇する。また、前記絶縁基板の第２主面側は、電源電位やグラウンド電位等の均一な電位にする必要があり、前記外部端子等が設けられていると、その周囲で高周波特性が劣化する。そのため、前記外部端子の配列の高密度化が難しく、前記電子装置の小型化が難しいという問題があった。   In the conventional wiring board, as a method for preventing deterioration of electrical characteristics in a high frequency region, for example, a signal transmission wiring (conductor pattern) is provided on the first main surface of the insulating substrate, such as a microstrip, There is a method of providing a ground plane on two main surfaces. However, the wiring board having the microstrip is the same as the double-sided wiring board, and the manufacturing process of the wiring board increases and the manufacturing cost increases. Further, the second main surface side of the insulating substrate needs to have a uniform potential such as a power supply potential or a ground potential, and if the external terminal or the like is provided, the high frequency characteristics are deteriorated around the external terminal. Therefore, there is a problem that it is difficult to increase the density of the arrangement of the external terminals and it is difficult to reduce the size of the electronic device.

また、前記コンデンサや抵抗等の受動素子を用いた電子装置の場合、前記受動素子自体が非常に小型なので、前記配線板のスルーホールやビアを設けるための開口部の直径も非常に小さい。また、前記特許文献１や特許文献２に記載された配線板のように、コンデンサ素子の陽極と電気的に接続する導体パターン下のスルーホールと、前記コンデンサ素子の陰極と電気的に接続する導体パターン下のスルーホールの深さが異なる場合が多い。そのため、前記スルーホールやビアを形成する工程で、前記開口部内に、導電性部材を密に充填することが難しく、前記導電性部材の充填不良による導通不良が起こりやすいので、製造歩留まりが低くなるという問題があった。
特開平８−１４８３８６号公報 特開２００１−３０７９４６号公報 In the case of an electronic device using a passive element such as a capacitor or a resistor, the passive element itself is very small, so that the diameter of the opening for providing the through hole or via of the wiring board is very small. Moreover, like the wiring board described in the said patent document 1 or the patent document 2, the through-hole under the conductor pattern electrically connected with the anode of a capacitor element, and the conductor electrically connected with the cathode of the said capacitor element The depth of the through hole under the pattern is often different. For this reason, in the step of forming the through hole or via, it is difficult to densely fill the opening with the conductive member, and poor conduction due to poor filling of the conductive member is likely to occur, resulting in a low manufacturing yield. There was a problem.
JP-A-8-148386 JP 2001-307946 A

本発明が解決しようとする問題点は、前記背景技術で説明したように、前記配線板上に電子部品を実装した電子装置を薄型化するためには、前記両面配線板を用いなければならず、製造コストが上昇するという点である。   As described in the background art, the problem to be solved by the present invention is that the double-sided wiring board must be used in order to reduce the thickness of an electronic device having electronic components mounted on the wiring board. The manufacturing cost is increased.

また、他の問題点は、従来の前記配線板上に電子部品を実装した電子装置では、動作周波数が数GHzから数十GHzの高周波領域で、電気特性が劣化しやすいという点である。   Another problem is that in the conventional electronic device in which electronic components are mounted on the wiring board, the electrical characteristics are likely to deteriorate in the high frequency region of several GHz to several tens of GHz.

また、他の問題点は、前記電子部品として、前記コンデンサや抵抗等の受動素子を用いた電子装置では、小型化が難しいという点である。   Another problem is that it is difficult to reduce the size of an electronic device using a passive element such as a capacitor or a resistor as the electronic component.

本発明の目的は、配線板上に電子部品を実装した電子装置の薄型化が可能で、且つ製造コストの上昇を抑えることが可能な技術を提供することにある。   An object of the present invention is to provide a technique capable of reducing the thickness of an electronic device in which an electronic component is mounted on a wiring board and suppressing an increase in manufacturing cost.

また、本発明の他の目的は、前記配線板上に電子部品を実装した電子装置の高周波特性の劣化を防ぐことが可能な技術を提供することにある。   Another object of the present invention is to provide a technique capable of preventing deterioration of high frequency characteristics of an electronic device in which an electronic component is mounted on the wiring board.

また、本発明の他の目的は、前記電子部品として、前記コンデンサや抵抗等の小型の受動素子を用いた電子装置の製造歩留まりを向上させることが可能な技術を提供することにある。   Another object of the present invention is to provide a technique capable of improving the manufacturing yield of electronic devices using small passive elements such as capacitors and resistors as the electronic components.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明の概略を説明すれば、以下の通りである。   The outline of the invention disclosed in the present application will be described as follows.

（１）絶縁基板の第１主面に導体パターンが設けられた配線板と、前記配線板の第１主面側に設けられたチップ状の電子部品と、前記配線板の導体パターンと前記チップ状の電子部品の電極とを電気的に接続する接続導体とを備える電子装置であって、前記絶縁基板は、前記第１主面及びその裏面（以下、第２主面と称する）に開口端を有し、前記第１主面側の開口端が前記導体パターンでふさがれた開口部が設けられており、前記開口部に、銅，ニッケル，金，銀，すずあるいはそれらの合金、もしくは導電性ペーストのいずれかでなる導電性部材が充填されている電子装置である。   (1) A wiring board provided with a conductor pattern on the first main surface of the insulating substrate, a chip-shaped electronic component provided on the first main surface side of the wiring board, and the conductor pattern and the chip of the wiring board An electronic device comprising a connection conductor for electrically connecting an electrode of a shaped electronic component, wherein the insulating substrate has an open end on the first main surface and its back surface (hereinafter referred to as a second main surface). And the opening end of the first main surface side is covered with the conductor pattern, and copper, nickel, gold, silver, tin, or an alloy thereof, or a conductive material is provided in the opening. The electronic device is filled with a conductive member made of any of the conductive pastes.

（２）前記（１）の手段において、前記絶縁基板は、液晶ポリマーでなる。   (2) In the means of (1), the insulating substrate is made of a liquid crystal polymer.

（３）絶縁基板の第１主面上のあらかじめ定められた領域内に導体パターンが設けられ、前記導体パターンを設けた領域が繰り返し設けられた配線板であって、前記絶縁基板は、前記第１主面及びその裏面（以下、第２主面と称する）に開口端を有し、前記第１主面側の開口端が前記導体パターンでふさがれた開口部が設けられており、前記開口部に、銅，ニッケル，金，銀，すずあるいはそれらの合金、もしくは導電性ペーストのいずれかでなる導電性部材が充填されている配線板である。   (3) A wiring board in which a conductor pattern is provided in a predetermined region on the first main surface of the insulating substrate, and the region in which the conductor pattern is provided is repeatedly provided. An opening having an opening end on one main surface and its back surface (hereinafter referred to as a second main surface), wherein the opening end on the first main surface side is covered with the conductor pattern, is provided. The wiring board is filled with a conductive member made of copper, nickel, gold, silver, tin, an alloy thereof, or a conductive paste.

（４）前記（３）の手段において、前記絶縁基板は、液晶ポリマーでなる。   (4) In the means of (3), the insulating substrate is made of a liquid crystal polymer.

（５）前記（３）または（４）の手段において、前記開口部は、前記絶縁基板の第１領域、及び前記第１領域と隣接する第２領域をまたいで設けられている。   (5) In the means of (3) or (4), the opening is provided across the first region of the insulating substrate and the second region adjacent to the first region.

本発明の電子装置は、前記（１）の手段のように、前記絶縁基板の第１主面に導体パターンが設けられ、前記絶縁基板の開口部に導電性部材が充填された配線板を用いる。このとき、前記導電性部材が前記絶縁基板の第２主面側で露出していれば、前記導電性部材を、前記電子装置をマザーボード等のプリント配線板に実装するときの外部端子として利用することができる。そのため、配線板の薄型化、すなわち電子装置の薄型化が容易になる。   The electronic device according to the present invention uses a wiring board in which a conductor pattern is provided on the first main surface of the insulating substrate, and an opening of the insulating substrate is filled with a conductive member, as in the means (1). . At this time, if the conductive member is exposed on the second main surface side of the insulating substrate, the conductive member is used as an external terminal when the electronic device is mounted on a printed wiring board such as a mother board. be able to. Therefore, it is easy to reduce the thickness of the wiring board, that is, to reduce the thickness of the electronic device.

また、前記（２）の手段のように、前記絶縁基板として液晶ポリマー基板を用いることで、絶縁基板の有する比誘電率、誘電正接を小さくすることができ、数GHzから数十GHzの高周波領域での電気特性の劣化を防ぐことができる。   Further, as in the means (2), by using a liquid crystal polymer substrate as the insulating substrate, the dielectric constant and dielectric loss tangent of the insulating substrate can be reduced, and a high frequency region of several GHz to several tens GHz. It is possible to prevent the deterioration of the electrical characteristics at.

また、前記電子装置では、前記導電性部材は、前記絶縁基板の第２主面側の表面に、すず，すず−銀合金，すず−銅合金，すず−ビスマス合金，すず−亜鉛合金，金，銀，パラジウムのいずれかのめっきが設けられていることが好ましい。   In the electronic device, the conductive member is formed on the surface of the second main surface side of the insulating substrate, such as tin, tin-silver alloy, tin-copper alloy, tin-bismuth alloy, tin-zinc alloy, gold, It is preferable that either silver or palladium plating is provided.

また、前記電子装置では、前記導電性部材は、前記絶縁基板の第２主面側の表面に、ボール状の接合材が設けられていてもよい。   In the electronic device, the conductive member may be provided with a ball-shaped bonding material on a surface on the second main surface side of the insulating substrate.

また、本発明の電子装置で用いる配線板は、例えば、前記（３）の手段のように、絶縁基板の第１主面に導体パターンが設けられ、前記絶縁基板の開口部に、電子装置の外部端子として利用することができる導電性部材が充填されている。そのため、前記（３）の手段の配線板を用いることで、電子装置の薄型化が容易である。また、前記（３）の手段の配線板は、従来の両面配線板と比べて、少ない工程数で製造することができる。そのため、製造コストの上昇も抑えることができる。   In addition, the wiring board used in the electronic device of the present invention is provided with a conductor pattern on the first main surface of the insulating substrate, for example, as in the means (3), and the opening of the insulating substrate A conductive member that can be used as an external terminal is filled. Therefore, it is easy to make the electronic device thinner by using the wiring board of the means (3). Further, the wiring board of the means (3) can be manufactured with a smaller number of processes than the conventional double-sided wiring board. Therefore, an increase in manufacturing cost can be suppressed.

また、前記（４）の手段のように、前記絶縁基板として液晶ポリマーを用いた場合、高周波領域での電気特性の劣化を防ぐことができる。また、液晶ポリマーを用いた場合、従来のポリイミドテープ等を用いて配線板を製造するときと同様の手順で配線板を製造することができる。   Further, when the liquid crystal polymer is used as the insulating substrate as in the means (4), it is possible to prevent deterioration of electrical characteristics in the high frequency region. Moreover, when a liquid crystal polymer is used, a wiring board can be manufactured in the same procedure as when manufacturing a wiring board using a conventional polyimide tape or the like.

また、前記（５）の手段のように、前記絶縁基板の第１領域及び第２領域をまたぐ開口部が設けられていれば、前記配線板を用いて電子装置を製造し、前記第１領域と第２領域を切断したときに、前記開口部に充填した導電性部材も切断、分離される。そのため、１つの開口部で、前記第１領域の外部端子と前記第２領域の外部端子の２つを形成することができる。このとき、前記開口部の穴径は、外部端子を個々に形成するときの穴径と比べて十分に大きくすることができる。そのため、コンデンサや抵抗等の小型の電子部品を実装する配線板でも、前記導電性部材の充填不良が起こりにくく、製造歩留まりを向上させることができる。   Further, as in the above means (5), if an opening is provided across the first region and the second region of the insulating substrate, an electronic device is manufactured using the wiring board, and the first region When the second region is cut, the conductive member filled in the opening is also cut and separated. Therefore, two openings, that is, the external terminal of the first region and the external terminal of the second region can be formed with one opening. At this time, the hole diameter of the opening can be made sufficiently larger than the hole diameter when the external terminals are individually formed. Therefore, even with a wiring board on which small electronic components such as capacitors and resistors are mounted, the filling failure of the conductive member hardly occurs, and the manufacturing yield can be improved.

また、前記（３）から（５）の配線板において、前記導電性部材は、前記絶縁基板の第２主面側の表面が、前記絶縁基板の第１主面と第２主面の間に存在してもよいし、前記第２主面と同じ高さにあってもよい。またさらに、前記導電性部材が前記第２主面から突出していてもよい。   In the wiring boards of (3) to (5), the conductive member has a surface on the second main surface side of the insulating substrate between the first main surface and the second main surface of the insulating substrate. It may exist and may be at the same height as the second main surface. Furthermore, the conductive member may protrude from the second main surface.

以下、本発明について、図面を参照して実施の形態（実施例）とともに詳細に説明する。   Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.

なお、実施例を説明するための全図において、同一機能を有するものは、同一符号を付け、その繰り返しの説明は省略する。   In all the drawings for explaining the embodiments, parts having the same function are given the same reference numerals and their repeated explanation is omitted.

本発明の電子装置では、絶縁基板の第１主面に導体パターンを設け、前記絶縁基板の第２主面側が開口した開口部（ブラインドビアホール）に導電性部材が充填された配線板を用いることで前記配線板の薄型化を実現する。またこのとき、前記絶縁基板に、液晶ポリマーを用いることで、動作周波数が数GHzから数十GHzの高周波領域で、電気特性が劣化するのを防ぐ。   In the electronic device of the present invention, a wiring board is used in which a conductive pattern is provided on the first main surface of the insulating substrate, and an opening (blind via hole) in which the second main surface side of the insulating substrate is opened is filled with a conductive member. Thus, the wiring board is made thinner. At this time, by using a liquid crystal polymer for the insulating substrate, the electrical characteristics are prevented from deteriorating in a high frequency region of several GHz to several tens GHz.

図１及び図２は、本発明による実施例１の電子装置の概略構成を示す模式図であり、図１（ａ）は電子装置の平面図、図１（ｂ）は図１（ａ）のＡ−Ａ’線での断面図、図２（ａ）は電子装置に用いる配線板の平面図、図２（ｂ）は図２（ａ）のＢ−Ｂ’線での断面図である。   1 and 2 are schematic views showing a schematic configuration of an electronic device according to a first embodiment of the present invention. FIG. 1A is a plan view of the electronic device, and FIG. 1B is a plan view of FIG. 2A is a cross-sectional view taken along line AA ′, FIG. 2A is a plan view of a wiring board used in the electronic device, and FIG. 2B is a cross-sectional view taken along line BB ′ in FIG.

図１及び図２の各図において、１は絶縁基板（液晶ポリマー基板）、１Ａは絶縁基板の第１主面、１Ｂは絶縁基板の第２主面、１Ｃは絶縁基板の開口部（貫通穴）、２ａは導体パターン、２ｂは導電性部材、３ａは電子部品（半導体チップ）、３０１ａは半導体チップの外部電極、４ａはボンディングワイヤ、５ａ，５ｂはめっき、６は保護膜、７は絶縁性接着材、８は絶縁性樹脂（モールドレジン）である。   1 and 2, 1 is an insulating substrate (liquid crystal polymer substrate), 1A is a first main surface of the insulating substrate, 1B is a second main surface of the insulating substrate, and 1C is an opening (through hole) of the insulating substrate. 2a is a conductive pattern, 2b is a conductive member, 3a is an electronic component (semiconductor chip), 301a is an external electrode of the semiconductor chip, 4a is a bonding wire, 5a and 5b are plating, 6 is a protective film, and 7 is insulating. An adhesive material 8 is an insulating resin (mold resin).

本実施例１の電子装置は、図１（ａ）及び図１（ｂ）に示すように、絶縁基板１の第１主面１Ａに導体パターン２ａが設けられた配線板と、前記配線板（絶縁基板１）の第１主面１Ａ側に設けられたチップ状の電子部品３ａと、前記導体パターン２ａと前記電子部品３ａの外部電極３０１ａとを電気的に接続するボンディングワイヤ４ａとを備える。   As shown in FIGS. 1A and 1B, the electronic device according to the first embodiment includes a wiring board in which a conductor pattern 2a is provided on the first main surface 1A of the insulating substrate 1, and the wiring board ( A chip-shaped electronic component 3a provided on the first main surface 1A side of the insulating substrate 1) and a bonding wire 4a for electrically connecting the conductor pattern 2a and the external electrode 301a of the electronic component 3a are provided.

このとき、前記配線板の絶縁基板１は、図２（ａ）及び図２（ｂ）に示すように、前記第１主面１Ａとその裏面（以下、第２主面と称する）１Ｂが開口しており、前記第１主面１Ａ側の開口端が前記導体パターン２ａでふさがれている開口部１Ｃが設けられている。またこのとき、前記開口部１Ｃには、前記電子装置をマザーボード等のプリント配線板に実装するときの外部端子として用いる導電性部材２ｂが充填されている。前記導電性部材２ｂは、例えば、銅，ニッケル，金，銀，すず、あるいはそれらの合金のめっき、もしくは銀ペースト等の導電性ペーストのいずれかでなるとする。また、前記導電性部材２ｂは、例えば、図２（ｂ）に示したように、前記絶縁基板１の第２主面１Ｂとほぼ同じ高さまで充填する。   At this time, as shown in FIGS. 2A and 2B, the insulating substrate 1 of the wiring board has an opening in the first main surface 1A and its back surface (hereinafter referred to as a second main surface) 1B. An opening 1C is provided in which the opening end on the first main surface 1A side is blocked by the conductor pattern 2a. At this time, the opening 1C is filled with a conductive member 2b used as an external terminal when the electronic device is mounted on a printed wiring board such as a mother board. The conductive member 2b is made of, for example, copper, nickel, gold, silver, tin, or an alloy thereof, or a conductive paste such as a silver paste. In addition, the conductive member 2b is filled up to almost the same height as the second main surface 1B of the insulating substrate 1, for example, as shown in FIG.

また、前記導体パターン２ａの表面及び前記導電性部材２ｂの表面にはそれぞれ、めっき５ａ，５ｂが設けられている。このとき、前記導電性部材２ｂの表面のめっき５ｂは、例えば、すず，すず−銀合金，すず−銅合金，すず−ビスマス合金，すず−亜鉛合金，金，銀，パラジウムのいずれかでなるとする。また、前記導体パターン２ａの表面のめっき５ａは、前記導電性部材２ｂの表面のめっき５ｂと同じ金属材料のめっきでも、異なる金属材料のめっきでもよいが、前記ボンディングワイヤ４ａとの接続信頼性をよくするためには、金，銀，パラジウムのいずれかのめっきを設けることが好ましい。   Further, plating 5a and 5b are provided on the surface of the conductor pattern 2a and the surface of the conductive member 2b, respectively. At this time, the plating 5b on the surface of the conductive member 2b is made of, for example, any one of tin, tin-silver alloy, tin-copper alloy, tin-bismuth alloy, tin-zinc alloy, gold, silver, and palladium. . The plating 5a on the surface of the conductive pattern 2a may be the same metal material as the plating 5b on the surface of the conductive member 2b or a different metal material, but the connection reliability with the bonding wire 4a is improved. In order to improve, it is preferable to provide any one of gold, silver and palladium.

また、本実施例１の電子装置で用いる配線板では、図２（ｂ）に示したように、前記絶縁基板１の第１主面１Ａの、前記導体パターン２ａと重なる領域の外側に、はんだ保護膜（ソルダレジスト）等の保護膜６が設けられている。   Further, in the wiring board used in the electronic device of the first embodiment, as shown in FIG. 2B, the solder is formed outside the region of the first main surface 1A of the insulating substrate 1 that overlaps the conductor pattern 2a. A protective film 6 such as a protective film (solder resist) is provided.

また、本実施例１の電子装置に用いる配線板では、前記絶縁基板は、液晶ポリマーでなるとする。   In the wiring board used for the electronic device of the first embodiment, the insulating substrate is made of a liquid crystal polymer.

また、本実施例１の電子装置では、前記チップ状の電子部品３ａは、例えば、ＩＣやＬＳＩのような集積回路を持つ部品であり、シリコン（Ｓｉ）やガリウムヒ素（ＧａＡｓ）等の半導体基板を用いて形成した部品であるとする。以下、本実施例１の電子装置に用いる電子部品３ａを半導体チップと称する。またこのとき、前記半導体チップ３ａは、例えば、ＤＲＡＭのようなメモリー機能を備えるチップでもよいし、ＣＰＵのような演算機能を備えるチップ、あるいは複数種類の機能を備えるチップでもよい。   In the electronic device of the first embodiment, the chip-shaped electronic component 3a is a component having an integrated circuit such as an IC or LSI, and is a semiconductor substrate such as silicon (Si) or gallium arsenide (GaAs). It is assumed that the part is formed using Hereinafter, the electronic component 3a used in the electronic device of the first embodiment is referred to as a semiconductor chip. At this time, the semiconductor chip 3a may be a chip having a memory function such as a DRAM, a chip having a calculation function such as a CPU, or a chip having a plurality of types of functions.

また、前記配線板と前記半導体チップ３ａは、例えば、エポキシ樹脂等の絶縁性接着材７で接着されている。また、前記半導体チップ３ａ及び前記ボンディングワイヤ４ａの接続部の周囲は、絶縁性樹脂（モールドレジン）８で封止されている。   The wiring board and the semiconductor chip 3a are bonded to each other with an insulating adhesive material 7 such as an epoxy resin. Further, the periphery of the connecting portion between the semiconductor chip 3a and the bonding wire 4a is sealed with an insulating resin (mold resin) 8.

図３は、本実施例１の電子装置に用いる配線板の製造方法を説明するための模式図であり、図３（ａ），図３（ｂ），図３（ｃ），図３（ｄ），図３（ｅ）の各図は配線板の各製造工程における断面図である。   FIG. 3 is a schematic diagram for explaining a method of manufacturing a wiring board used in the electronic apparatus of the first embodiment, and FIGS. 3 (a), 3 (b), 3 (c), and 3 (d). ) And FIG. 3E are cross-sectional views in each manufacturing process of the wiring board.

本実施例１の電子装置に用いる配線板は、図２（ａ）及び図２（ｂ）に示したように、前記絶縁基板１の第１主面１Ａに導体パターン２ａが設けられ、前記絶縁基板１の第２主面１Ｂ側には、前記絶縁基板１に設けられた開口部（ブラインドビアホール）１Ｃに充填された導電性部材２ｂが露出している。このような配線板は、従来の半導体装置で用いられる配線板（インターポーザ）と同様の製造方法、例えば、リール方式で製造するのが好ましい。前記リール方式では、一方向に長尺なテープ状の絶縁基板を用意し、前記絶縁基板上に、図２（ａ）及び図２（ｂ）に示したような領域を繰り返し形成する。   As shown in FIGS. 2A and 2B, the wiring board used in the electronic device of Example 1 is provided with a conductor pattern 2a on the first main surface 1A of the insulating substrate 1, and the insulating board 1 On the second main surface 1B side of the substrate 1, a conductive member 2b filled in an opening (blind via hole) 1C provided in the insulating substrate 1 is exposed. Such a wiring board is preferably manufactured by a manufacturing method similar to a wiring board (interposer) used in a conventional semiconductor device, for example, a reel method. In the reel method, a tape-shaped insulating substrate that is long in one direction is prepared, and regions as shown in FIGS. 2A and 2B are repeatedly formed on the insulating substrate.

本実施例１の電子装置で用いる配線板を製造するときには、前記テープ状の絶縁基板１として、例えば、液晶ポリマー材料をテープ状に成型して半硬化状態にした液晶ポリマー基板、あるいはテープ状に成型して完全硬化させた後、第１主面１Ａに接着材層を設けた接着材付き液晶ポリマー基板を用いる。以下、前記液晶ポリマー基板、あるいは前記接着材付き液晶ポリマー基板を用いた配線板の製造方法の一例を説明する。   When manufacturing a wiring board used in the electronic device of the first embodiment, as the tape-like insulating substrate 1, for example, a liquid crystal polymer substrate obtained by molding a liquid crystal polymer material into a tape shape to be in a semi-cured state, or a tape shape. After being molded and completely cured, a liquid crystal polymer substrate with an adhesive provided with an adhesive layer on the first main surface 1A is used. Hereinafter, an example of a method for manufacturing a wiring board using the liquid crystal polymer substrate or the liquid crystal polymer substrate with an adhesive will be described.

前記液晶ポリマー基板あるいは接着剤付き液晶ポリマー基板でなる絶縁基板１を用いて配線板を製造するときには、まず、例えば、図３（ａ）に示すように、前記絶縁基板１に、第１主面１Ａ及び第２主面１Ｂが開口した貫通穴１Ｃを形成する。前記貫通穴１Ｃは、金型による打ち抜き加工で形成する。   When manufacturing a wiring board using the insulating substrate 1 made of the liquid crystal polymer substrate or the liquid crystal polymer substrate with an adhesive, first, for example, as shown in FIG. A through hole 1C is formed in which 1A and the second main surface 1B are open. The through hole 1C is formed by punching with a mold.

次に、図３（ｂ）に示すように、前記貫通穴１Ｃを形成した絶縁基板１の第１主面１Ａに、銅箔等の導体膜２を貼り合わせる。このとき、前記絶縁基板１が半硬化状態の液晶ポリマー基板であれば、前記導体膜２を重ねた後、前記液晶ポリマー基板を完全硬化させることで、前記導体膜２が前記絶縁基板１に接着される。また、前記絶縁基板１が接着材付き液晶ポリマー基板の場合は、前記接着材層を利用して前記導体膜２を前記絶縁基板１に接着する。   Next, as shown in FIG. 3B, a conductor film 2 such as a copper foil is bonded to the first main surface 1A of the insulating substrate 1 in which the through hole 1C is formed. At this time, if the insulating substrate 1 is a semi-cured liquid crystal polymer substrate, the conductor film 2 is adhered to the insulating substrate 1 by completely curing the liquid crystal polymer substrate after the conductor film 2 is overlaid. Is done. When the insulating substrate 1 is a liquid crystal polymer substrate with an adhesive, the conductor film 2 is bonded to the insulating substrate 1 using the adhesive layer.

次に、図３（ｃ）に示すように、前記絶縁基板１の開口部１Ｃに導電性部材２ｂを充填する。前記導電性部材２ｂとして、銅，ニッケル，金，銀，すず、またはそれらの合金を充填する場合には、例えば、前記導体膜２を電極とした電解めっきを行う。また、電解めっきの代わりに無電解めっきを行ってもよい。また、前記導電性部材２ｂとして、銀ペーストなどの導電性ペーストを充填するときには、印刷法で前記導電性ペーストを前記開口部１Ｃに刷り込んだ後、前記導電性ペーストを硬化させる。   Next, as shown in FIG. 3C, the conductive member 2b is filled in the opening 1C of the insulating substrate 1. When the conductive member 2b is filled with copper, nickel, gold, silver, tin, or an alloy thereof, for example, electrolytic plating using the conductor film 2 as an electrode is performed. Further, electroless plating may be performed instead of electrolytic plating. When the conductive member 2b is filled with a conductive paste such as a silver paste, the conductive paste is cured after printing the conductive paste into the opening 1C by a printing method.

次に、図３（ｄ）に示すように、前記導体膜２の不要な部分をエッチングで除去して、導体パターン２ａを形成する。前記導体パターン２ａは、アディティブ法やサブトラクティブ法で形成する。   Next, as shown in FIG. 3D, unnecessary portions of the conductor film 2 are removed by etching to form a conductor pattern 2a. The conductor pattern 2a is formed by an additive method or a subtractive method.

その後、例えば、図３（ｅ）に示すように、前記絶縁基板１の第１主面１Ａの、前記導体パターン２ａと重なる領域の外側の領域に、はんだ保護膜等の保護膜６を形成する。そして、前記導体パターン２ａの表面及び前記導電性部材２ｂの表面のそれぞれにめっき５ａ，５ｂを形成すると、図２（ａ）及び図２（ｂ）に示したような配線板が得られる。このとき、前記導電性部材２ｂの表面のめっき５ｂは、例えば、すず，すず−銀合金，すず−銅合金，すず−ビスマス合金，すず−亜鉛合金，金，銀，パラジウムのいずれかのめっきを、電解めっきまたは無電解めっきで形成する。また、前記導体パターン２ａの表面に形成するめっき５ａは、前記導電性部材２ｂの表面のめっき５ｂと同じ金属材料のめっきでも、異なる金属材料のめっきでもよい。なお、図示は省略するが、前記めっき５ａ，５ｂを電解めっきで形成する場合には、前記導体パターン２ａを形成するときに、電解めっき用の給電ラインを同時に形成しておく。   Thereafter, for example, as shown in FIG. 3E, a protective film 6 such as a solder protective film is formed on the first main surface 1A of the insulating substrate 1 in a region outside the region overlapping the conductor pattern 2a. . When platings 5a and 5b are formed on the surface of the conductor pattern 2a and the surface of the conductive member 2b, a wiring board as shown in FIGS. 2A and 2B is obtained. At this time, the plating 5b on the surface of the conductive member 2b is, for example, any one of tin, tin-silver alloy, tin-copper alloy, tin-bismuth alloy, tin-zinc alloy, gold, silver and palladium. It is formed by electrolytic plating or electroless plating. The plating 5a formed on the surface of the conductor pattern 2a may be the same metal material as the plating 5b on the surface of the conductive member 2b or a different metal material. In addition, although illustration is abbreviate | omitted, when forming the said plating 5a and 5b by electrolytic plating, when forming the said conductor pattern 2a, the electric power feeding line for electrolytic plating is formed simultaneously.

なお、本実施例１では、図３（ａ）及び図３（ｂ）に示したように、前記絶縁基板１に貫通穴１Ｃを形成した後、前記導体膜２を貼り合わせたが、この逆で、前記絶縁基板１に導体膜２を貼り合わせた後、レーザー加工等で前記絶縁基板１に開口部（ブラインドビアホール）１Ｃを形成してもよい。また、前記保護膜６を形成する工程も、図３（ｅ）に示したように、前記めっき５ａ，５ｂを形成する工程の前に限らず、前記めっき５ａ，５ｂを形成する工程の後で行ってもよい。   In Example 1, as shown in FIGS. 3A and 3B, after the through hole 1C was formed in the insulating substrate 1, the conductor film 2 was bonded. Then, after the conductive film 2 is bonded to the insulating substrate 1, an opening (blind via hole) 1C may be formed in the insulating substrate 1 by laser processing or the like. Further, the process of forming the protective film 6 is not limited to the process of forming the platings 5a and 5b, as shown in FIG. 3E, but after the process of forming the platings 5a and 5b. You may go.

前記手順に沿って製造した配線板を用いて電子装置（半導体装置）を製造するときには、まず、例えば、図１（ａ）及び図１（ｂ）に示したように、前記配線板（絶縁基板１）の第１主面１Ａ上に、エポキシ樹脂等の絶縁性接着材７を用いて半導体チップ３ａを接着し、前記配線板の導体パターン２ａと前記半導体チップ３ａの外部電極３０１ａをボンディングワイヤ４ａで電気的に接続する。そしてその後、前記半導体チップ３ａ及びボンディングワイヤ４ａの周囲を絶縁性樹脂８で封止する。また、前記リール方式で製造した配線板の場合、前記絶縁基板１には、図１（ａ）及び図１（ｂ）に示した領域が繰り返し存在するので、あらかじめ定められた領域を切り出して個片化することで、電子装置（半導体装置）が得られる。   When an electronic device (semiconductor device) is manufactured using a wiring board manufactured according to the above procedure, first, for example, as shown in FIGS. 1 (a) and 1 (b), the wiring board (insulating substrate) is used. 1) On the first main surface 1A of 1), the semiconductor chip 3a is bonded using an insulating adhesive material 7 such as epoxy resin, and the conductor pattern 2a of the wiring board and the external electrode 301a of the semiconductor chip 3a are bonded to the bonding wire 4a. Connect it electrically. Then, the periphery of the semiconductor chip 3a and the bonding wire 4a is sealed with an insulating resin 8. Further, in the case of the wiring board manufactured by the reel method, since the regions shown in FIGS. 1 (a) and 1 (b) exist repeatedly on the insulating substrate 1, a predetermined region is cut out to be individual. An electronic device (semiconductor device) can be obtained by singulation.

本実施例１の電子装置に用いる配線板では、前記絶縁基板１として液晶ポリマー基板を用いている。前記液晶ポリマー基板は、比誘電率（ε）が３程度であり、従来の配線板で用いられているポリイミドテープの比誘電率（５から６程度）よりも小さい。また、前記液晶ポリマーは、例えば、数GHzから数十GHzの高周波領域での誘電正接（tanδ）も０．００２から０．００３程度であり、前記ポリイミドテープの誘電正接よりも小さい。すなわち、本実施例１の電子装置は、従来の配線板を用いた電子装置と比べて、高周波領域での優れた電気特性を有する。   In the wiring board used in the electronic device of Example 1, a liquid crystal polymer substrate is used as the insulating substrate 1. The liquid crystal polymer substrate has a relative dielectric constant (ε) of about 3, which is smaller than the relative dielectric constant (about 5 to 6) of a polyimide tape used in a conventional wiring board. The liquid crystal polymer also has a dielectric loss tangent (tan δ) in a high frequency region of several GHz to several tens GHz, for example, of about 0.002 to 0.003, which is smaller than the dielectric loss tangent of the polyimide tape. That is, the electronic device according to the first embodiment has excellent electrical characteristics in a high frequency region as compared with an electronic device using a conventional wiring board.

また、前記液晶ポリマー基板は、前記ポリイミドフィルムと比べて、低吸水率であり、吸湿に対する寸法安定性も高い。また、熱膨張係数の制御も容易である。そのため、前記電子装置を製造する過程や前記電子装置を動作させたときの熱履歴、あるいは周囲の湿度の変化による、前記導体パターン２ａや導電性部材２ｂのはがれ等を低減することができる。   Further, the liquid crystal polymer substrate has a low water absorption rate and high dimensional stability against moisture absorption as compared with the polyimide film. Also, the control of the thermal expansion coefficient is easy. Therefore, peeling of the conductive pattern 2a and the conductive member 2b due to a process of manufacturing the electronic device, a thermal history when the electronic device is operated, or a change in ambient humidity can be reduced.

以上説明したように、本実施例１の電子装置によれば、前記絶縁基板１の第１主面１Ａに導体パターン２ａを設け、前記絶縁基板１に設けた開口部１Ｃに導電性部材２ｂを充填した配線板を用い、前記導電性部材２ｂを外部端子として利用することで、前記ＢＧＡやＣＳＰと呼ばれる形態の半導体装置のようなボール状の外部端子が不要となり、電子装置（半導体装置）を薄型化することができる。   As described above, according to the electronic apparatus of the first embodiment, the conductive pattern 2a is provided on the first main surface 1A of the insulating substrate 1, and the conductive member 2b is provided in the opening 1C provided on the insulating substrate 1. By using the filled wiring board and using the conductive member 2b as an external terminal, a ball-shaped external terminal such as a semiconductor device called BGA or CSP is unnecessary, and an electronic device (semiconductor device) can be used. Thinning can be achieved.

また、前記外部端子として利用する前記導電性部材２ｂは、前記絶縁基板１の第２主面１Ｂとほぼ同じ高さまで充填しておけばよいので、従来のＬＧＡと呼ばれる形態の半導体装置のように、前記絶縁基板１の第２主面上に導体パターン（ランド）が設けられた電子装置と比べても、前記電子装置（半導体装置）の薄型化することができる。   Further, since the conductive member 2b used as the external terminal only needs to be filled up to the same height as the second main surface 1B of the insulating substrate 1, as in a conventional semiconductor device called LGA. The electronic device (semiconductor device) can be made thinner than an electronic device in which a conductor pattern (land) is provided on the second main surface of the insulating substrate 1.

また、本実施例１の電子装置に用いる配線板は、従来の、両面配線板の製造工程よりも少ない工程で、短時間に製造することができる。そのため、前記両面配線板を用いたＬＧＡ型の半導体装置に比べて、前記配線板及び前記配線板を用いた電子装置の製造コスト低減することができる。   Moreover, the wiring board used for the electronic device of the first embodiment can be manufactured in a short time with fewer steps than a conventional double-sided wiring board manufacturing process. Therefore, compared with the LGA type semiconductor device using the double-sided wiring board, the manufacturing cost of the electronic device using the wiring board and the wiring board can be reduced.

また、本実施例１では、図１（ａ）及び図１（ｂ）に示したように、前記配線板の導体パターン２ａと前記半導体チップ３ａの外部電極３０１ａをボンディングワイヤ４ａで接続した電子装置を例に挙げたが、これに限らず、前記半導体チップ３ａをフリップチップ実装した電子装置であってもよい。その場合、図示は省略するが、例えば、前記半導体チップ３ａの外部電極３０１ａ上に、金バンプ等の突起状導体を形成しておき、前記外部電極３０１ａが設けられた面を前記配線板と向かい合わせて、前記突起状導体と前記配線板の導体パターン２ａとを接続（接合）する。   In the first embodiment, as shown in FIGS. 1A and 1B, an electronic device in which the conductor pattern 2a of the wiring board and the external electrode 301a of the semiconductor chip 3a are connected by a bonding wire 4a. However, the present invention is not limited to this, and an electronic device in which the semiconductor chip 3a is flip-chip mounted may be used. In that case, although illustration is omitted, for example, a protruding conductor such as a gold bump is formed on the external electrode 301a of the semiconductor chip 3a, and the surface on which the external electrode 301a is provided faces the wiring board. In addition, the protruding conductor and the conductor pattern 2a of the wiring board are connected (joined).

図４は、前記実施例１の変形例を説明するための模式図であり、電子装置に用いる配線板の概略構成を示す模式断面図である。   FIG. 4 is a schematic diagram for explaining a modification of the first embodiment, and is a schematic cross-sectional view showing a schematic configuration of a wiring board used in the electronic device.

前記実施例１の配線板では、図２（ｂ）に示したように、前記絶縁基板１の第１主面１Ａの、前記導体パターン２ａと重なる領域の外側のみに前記保護膜６が設けられているが、これに限らず、例えば、図４に示すように、前記導体パターン２ａのうち、前記ボンディングワイヤ４ａや前記突起状導体を接続する領域の周辺のみが露出するように前記保護膜６を形成してもよい。   In the wiring board of the first embodiment, as shown in FIG. 2B, the protective film 6 is provided only outside the region of the first main surface 1A of the insulating substrate 1 that overlaps the conductor pattern 2a. However, the present invention is not limited to this. For example, as shown in FIG. 4, the protective film 6 is exposed so that only the periphery of the region connecting the bonding wire 4 a and the protruding conductor is exposed in the conductor pattern 2 a. May be formed.

図５は、前記実施例１の応用例を説明するための模式図であり、図５（ａ）は配線板の概略構成を示す断面図、図５（ｂ）は図５（ａ）の配線板を用いた電子装置の概略構成を示す断面図である。   FIG. 5 is a schematic diagram for explaining an application example of the first embodiment. FIG. 5A is a cross-sectional view showing a schematic configuration of the wiring board, and FIG. 5B is a wiring diagram of FIG. It is sectional drawing which shows schematic structure of the electronic device using a board.

前記実施例１の電子装置に用いる配線板では、前記導電性部材２ｂは、図２（ｂ）に示したように、前記絶縁基板１の第２主面１Ｂとほぼ同じ高さまで充填しているが、これに限らず、例えば、図５（ａ）に示すように、前記開口部１Ｃを前記導電性部材２ｂで完全に充填せずに、前記絶縁基板の第２主面１Ｂに、前記導電性部材２ｂもしくはその表面のめっき５ｂを底面とする凹部が設けられていてもよい。このような配線板を用いて電子装置を製造するときには、例えば、図５（ｂ）に示すように、前記凹部にボール状の外部端子９を形成する。   In the wiring board used in the electronic device of the first embodiment, the conductive member 2b is filled up to almost the same height as the second main surface 1B of the insulating substrate 1 as shown in FIG. However, the present invention is not limited to this, for example, as shown in FIG. 5A, the opening 1C is not completely filled with the conductive member 2b, and the second main surface 1B of the insulating substrate is filled with the conductive material. A recess having the bottom surface of the conductive member 2b or the plating 5b on the surface thereof may be provided. When an electronic device is manufactured using such a wiring board, for example, as shown in FIG. 5B, ball-shaped external terminals 9 are formed in the recesses.

図５（ａ）に示したような、前記絶縁基板１の第２主面１Ｂ側に、前記導電性部材２ｂを底面とする凹部が設けられている配線板では、前記凹部の深さは、前記絶縁基板１の厚さよりも浅くなっている。そのため、前記ボール状の外部端子９の直径、言い換えると体積を小さくしても、前記ボール状の外部端子９と前記導電性部材２ｂの電気的接続を確保することができる。また、前記絶縁基板１の開口部１Ｃの穴径が小さくても、前記導電性部材２ｂが充填されていることで、前記凹部のアスペクト比は小さくなり、前記外部端子９と前記導電性部材２ｂの電気的接続を確保しやすい。そのため、前記ボール状の外部端子９を設けた場合でも、従来のＢＧＡやＣＳＰと呼ばれる形態の電子装置（半導体装置）と比べて薄型化が可能である。このとき、前記絶縁基板１の凹部の深さは、前記絶縁基板１の厚さの３分の１から３分の２程度であることが好ましい。すなわち、前記導電性部材２ｂの充填量を、前記実施例１で説明した場合の３分の２から３分の１程度にすることができる。この場合、前記導電性部材２ｂは電気めっきで充填（形成）することになるが、充填に要する時間が短縮されるので、製造コストの上昇を抑えることができる。   As shown in FIG. 5A, in the wiring board in which the concave portion having the bottom surface of the conductive member 2b is provided on the second main surface 1B side of the insulating substrate 1, the depth of the concave portion is It is shallower than the thickness of the insulating substrate 1. Therefore, even if the diameter of the ball-shaped external terminal 9, in other words, the volume is reduced, the electrical connection between the ball-shaped external terminal 9 and the conductive member 2 b can be ensured. Further, even if the hole diameter of the opening 1C of the insulating substrate 1 is small, the aspect ratio of the recess is reduced by filling the conductive member 2b, and the external terminal 9 and the conductive member 2b are reduced. Easy to ensure electrical connection. Therefore, even when the ball-shaped external terminals 9 are provided, the thickness can be reduced as compared with a conventional electronic device (semiconductor device) called BGA or CSP. At this time, the depth of the concave portion of the insulating substrate 1 is preferably about one third to two thirds of the thickness of the insulating substrate 1. That is, the filling amount of the conductive member 2b can be reduced from about two-thirds to one-third of the case described in the first embodiment. In this case, the conductive member 2b is filled (formed) by electroplating, but since the time required for filling is shortened, an increase in manufacturing cost can be suppressed.

図６及び図７は、本発明による実施例２の電子装置の概略構成を示す模式図であり、図６（ａ）は電子装置の平面図、図６（ｂ）は図６（ａ）のＣ−Ｃ’線での断面図、図７（ａ）は電子装置に用いる配線板の平面図、図７（ｂ）は図７（ａ）のＤ−Ｄ’線での断面図である。   6 and 7 are schematic views showing a schematic configuration of the electronic device according to the second embodiment of the present invention. FIG. 6A is a plan view of the electronic device, and FIG. 6B is a plan view of FIG. FIG. 7A is a plan view of a wiring board used in the electronic device, and FIG. 7B is a cross-sectional view taken along the line DD ′ of FIG. 7A.

図６及び図７の各図において、１は絶縁基板（液晶ポリマー基板）、１Ａは絶縁基板の第１主面、１Ｂは絶縁基板の第２主面、１Ｃは絶縁基板の開口部（貫通穴）、２ａは導体パターン、２ｂは導電性部材、３ｂは電子部品（コンデンサ素子）、３０１ｂはコンデンサ素子の陽極、３０２ｂはコンデンサ素子の陰極、３０３ｂはコンデンサ素子の誘電体、４ｂは柱状導体、４ｃは導電性接着材、５ａ，５ｂはめっき、６は保護膜、８は絶縁性樹脂（モールドレジン）である。   6 and 7, reference numeral 1 denotes an insulating substrate (liquid crystal polymer substrate), 1A denotes a first main surface of the insulating substrate, 1B denotes a second main surface of the insulating substrate, and 1C denotes an opening (through hole) of the insulating substrate. 2a is a conductive pattern, 2b is a conductive member, 3b is an electronic component (capacitor element), 301b is an anode of the capacitor element, 302b is a cathode of the capacitor element, 303b is a dielectric of the capacitor element, 4b is a columnar conductor, 4c Is a conductive adhesive, 5a and 5b are plating, 6 is a protective film, and 8 is an insulating resin (mold resin).

本実施例２の電子装置は、図６（ａ）及び図６（ｂ）に示すように、絶縁基板１の第１主面１Ａに導体パターン２ａが設けられた配線板と、前記配線板（絶縁基板１）の第１主面１Ａ側に設けられたチップ状の電子部品３ｂと、前記導体パターン２ａと前記電子部品３ｂの電極３０１ｂ，３０２ｂとを電気的に接続する導電性部材４ｂ，４ｃとを備える。   As shown in FIGS. 6A and 6B, the electronic device according to the second embodiment includes a wiring board in which a conductor pattern 2a is provided on the first main surface 1A of the insulating substrate 1, and the wiring board ( Conductive members 4b and 4c that electrically connect the chip-shaped electronic component 3b provided on the first main surface 1A side of the insulating substrate 1) and the conductor pattern 2a and the electrodes 301b and 302b of the electronic component 3b. With.

本実施例２の電子装置において、前記チップ状の電子部品３ｂは、コンデンサ素子であり、図６（ｂ）に示したように、陽極３０１ｂ、陰極３０２ｂ、誘電体３０３ｂを備える。前記チップ状のコンデンサ素子３ｂには、例えば、タンタル固体電解コンデンサがある。前記タンタル固体電解コンデンサは、前記陽極３０１ｂが高純度のタンタル粉末を高温、高真空中で焼結した多孔質焼結体である。また、前記陰極３０２ｂは、例えば、二酸化マンガンまたは導電性高分子等の抵抗値が低い固体電解質，カーボン層，銀層により構成されている。また、前記誘電体３０３ｂは、例えば、酸性液中で電気化学的に化成した五酸化タンタルからなる。   In the electronic device of the second embodiment, the chip-shaped electronic component 3b is a capacitor element, and includes an anode 301b, a cathode 302b, and a dielectric 303b as shown in FIG. 6B. An example of the chip-like capacitor element 3b is a tantalum solid electrolytic capacitor. In the tantalum solid electrolytic capacitor, the anode 301b is a porous sintered body obtained by sintering high-purity tantalum powder in high temperature and high vacuum. The cathode 302b is made of, for example, a solid electrolyte, a carbon layer, or a silver layer having a low resistance value such as manganese dioxide or a conductive polymer. The dielectric 303b is made of, for example, tantalum pentoxide electrochemically formed in an acidic solution.

前記タンタル固体電解コンデンサは、多孔質の陽極３０１ｂを用いているため電極面積が大きく、部品の小型化、大容量化に適している。また、陰極３０２ｂが固体電解質であり、交流特性がよく、信頼性が高い。そのため、前記タンタル固体電解コンデンサを用いた電子装置は、携帯電話などの移動体通信機器や、ノートブック型コンピュータ，ＰＤＡ等の携帯型電子機器のように、小型化、薄型化、高周波化、高消費電流が要求される電子機器の容量部品として多く用いられている。   Since the tantalum solid electrolytic capacitor uses the porous anode 301b, the electrode area is large, and it is suitable for downsizing and increasing the capacity of parts. Further, the cathode 302b is a solid electrolyte, has good AC characteristics and high reliability. Therefore, an electronic device using the tantalum solid electrolytic capacitor is smaller, thinner, higher in frequency, higher in a mobile communication device such as a mobile phone and a portable electronic device such as a notebook computer or PDA. It is often used as a capacitive component of electronic equipment that requires current consumption.

また、前記配線板の絶縁基板１は、図６（ａ）及び図６（ｂ）に示すように、前記第１主面１Ａ及び第２主面１Ｂ、ならびに前記第１主面１Ａ及び第２主面１Ｂと直交する面１Ｄの三方が開口した開口部１Ｃが２カ所設けられている。またこのとき、前記各開口部１Ｃには、前記電子装置をマザーボード等のプリント配線板に実装するときの外部端子として用いる導電性部材２ｂが充填されている。また、前記各開口部１Ｃは、前記導体パターン２ａのいずれかにより、前記第１主面１Ａ側の開口端がふさがれており、前記導体パターン２ａと前記導電性部材が電気的に接続されている。前記導電性部材２ｂは、前記実施例１で説明したように、例えば、銅，ニッケル，金，銀，すず、あるいはそれらの合金のめっき、もしくは銀ペースト等の導電性ペーストのいずれかでなるとする。   In addition, as shown in FIGS. 6A and 6B, the insulating substrate 1 of the wiring board includes the first main surface 1A and the second main surface 1B, and the first main surface 1A and the second main surface. Two openings 1C are provided in which three sides of the surface 1D orthogonal to the main surface 1B are opened. At this time, each opening 1C is filled with a conductive member 2b used as an external terminal when the electronic device is mounted on a printed wiring board such as a mother board. Each opening 1C has an opening end on the first main surface 1A side blocked by one of the conductor patterns 2a, and the conductor pattern 2a and the conductive member are electrically connected. Yes. As described in the first embodiment, the conductive member 2b is made of, for example, copper, nickel, gold, silver, tin, or an alloy thereof, or a conductive paste such as a silver paste. .

また、前記導体パターン２ａの表面及び前記導電性部材２ｂの表面にはそれぞれ、めっき５ａ，５ｂが設けられている。このとき、前記導電性部材２ｂの表面のめっきは、例えば、すず，すず−銀合金，すず−銅合金，すず−ビスマス合金，すず−亜鉛合金，金，銀，パラジウムのいずれかでなるとする。また、前記導体パターン２ａの表面のめっき５ａは、前記導電性部材２ｂの表面のめっき５ｂと同じ金属材料のめっきでも、異なる金属材料のめっきでもよいが、前記ボンディングワイヤ４ａとの接続信頼性をよくするためには、金，銀，パラジウムのいずれかのめっきを設けることが好ましい。なお、本実施例２の電子装置では、図６（ｂ）に示したように、前記導体パターン２ａ及び前記導電性部材２ｂの表面のうち、前記絶縁基板１の第２主面１Ｂと直交する面１Ｄ側の表面には、前記めっき５ａ，５ｂが設けられていない。   Further, plating 5a and 5b are provided on the surface of the conductor pattern 2a and the surface of the conductive member 2b, respectively. At this time, the plating on the surface of the conductive member 2b is made of, for example, tin, tin-silver alloy, tin-copper alloy, tin-bismuth alloy, tin-zinc alloy, gold, silver, or palladium. The plating 5a on the surface of the conductive pattern 2a may be the same metal material as the plating 5b on the surface of the conductive member 2b or a different metal material, but the connection reliability with the bonding wire 4a is improved. In order to improve, it is preferable to provide any one of gold, silver and palladium. In the electronic device according to the second embodiment, as illustrated in FIG. 6B, the surface of the conductor pattern 2 a and the conductive member 2 b is orthogonal to the second main surface 1 B of the insulating substrate 1. The plating 5a, 5b is not provided on the surface on the surface 1D side.

また、本実施例２の電子装置では、前記導体パターン２ａと前記コンデンサ素子３ｂの陽極３０１ｂは、柱状導体４ｂで電気的に接続されており、前記導体パターン２ａと前記コンデンサ素子３ｂの陰極３０２ｂは、銀ペースト等の導電性接着材４ｃで電気的に接続されている。また、前記コンデンサ素子３ｂ、前記柱状導体４ｂ、及び前記導電性接着材４ｃの周囲は、絶縁性樹脂（モールドレジン）で封止されている。   In the electronic device of the second embodiment, the conductor pattern 2a and the anode 301b of the capacitor element 3b are electrically connected by a columnar conductor 4b, and the conductor pattern 2a and the cathode 302b of the capacitor element 3b are They are electrically connected by a conductive adhesive 4c such as silver paste. The periphery of the capacitor element 3b, the columnar conductor 4b, and the conductive adhesive 4c is sealed with an insulating resin (mold resin).

また、本実施例２の電子装置に用いる配線板でも、前記絶縁基板１は、液晶ポリマーでなるとする。   In the wiring board used in the electronic device of the second embodiment, the insulating substrate 1 is made of a liquid crystal polymer.

本実施例２の電子装置で用いる配線板は、前記実施例１で説明した配線板と同様で、一般に、一方向に長尺な絶縁基板１を用いたリール方式で製造される。このとき、前記絶縁基板１上には、図７（ａ）及び図７（ｂ）に示すように、１個の電子装置を製造するために必要な領域ＡＲに設けられた前記導体パターン２ａや前記導電性部材２ｂの構成や形状と同じ構成の領域が、繰り返し設けられている。   The wiring board used in the electronic device of the second embodiment is similar to the wiring board described in the first embodiment, and is generally manufactured by a reel method using the insulating substrate 1 that is long in one direction. At this time, on the insulating substrate 1, as shown in FIGS. 7A and 7B, the conductor pattern 2a provided in the region AR necessary for manufacturing one electronic device is formed. A region having the same configuration as the configuration and shape of the conductive member 2b is repeatedly provided.

また、本実施例２の電子装置で用いる配線板では、図７（ａ）及び図７（ｂ）に示したように、前記導体パターン２ａは、前記絶縁基板１の第１領域ＡＲ１から、前記第１領域ＡＲ１と隣接する第２領域ＡＲ２にかけて一体的に設けられている。また、前記絶縁基板１の開口部１Ｃも、前記絶縁基板１の第１主面１Ａ及び第２主面１Ｂの開口端が、前記第１領域ＡＲ１及び前記第２領域ＡＲ２をまたぐように設けられており、前記第１領域ＡＲ１の導電性部材２ｂと前記第２領域ＡＲ２の導電性部材２ｂが一体的に設けられている。   Further, in the wiring board used in the electronic device of the second embodiment, as shown in FIGS. 7A and 7B, the conductor pattern 2a extends from the first area AR1 of the insulating substrate 1 to the first area AR1. The first area AR1 and the second area AR2 adjacent to the first area AR1 are integrally provided. The opening 1C of the insulating substrate 1 is also provided so that the opening ends of the first main surface 1A and the second main surface 1B of the insulating substrate 1 straddle the first region AR1 and the second region AR2. The conductive member 2b in the first area AR1 and the conductive member 2b in the second area AR2 are integrally provided.

図８及び図９は、本実施例２の電子装置の製造方法を説明するための模式図であり、図８（ａ），図８（ｂ），図８（ｃ）は配線板を製造する各工程の断面図、図９（ａ），図９（ｂ），図９（ｃ）は前記配線板を用いて電子装置を製造する各工程の断面図である。   8 and 9 are schematic views for explaining a method of manufacturing the electronic device according to the second embodiment. FIGS. 8A, 8B, and 8C are for manufacturing a wiring board. 9A, 9B, and 9C are cross-sectional views of each process for manufacturing an electronic device using the wiring board.

本実施例２の電子装置を製造するときには、まず、図７（ａ）及び図７（ｂ）に示したような配線板を用意する。前記配線板は、例えば、前記実施例１で説明したように、一方向に長尺な絶縁基板１を用い、リール方式で製造する。このとき、前記絶縁基板１には、フィルム状に成型して半硬化状態にした液晶ポリマー基板、あるいはフィルム状に成型して完全硬化させた後、第１主面１Ａに接着材層を設けた接着材付き液晶ポリマー基板を用いる。   When manufacturing the electronic device according to the second embodiment, first, a wiring board as shown in FIGS. 7A and 7B is prepared. For example, as described in the first embodiment, the wiring board is manufactured by a reel method using the insulating substrate 1 that is long in one direction. At this time, the insulating substrate 1 is provided with an adhesive layer on the first main surface 1A after the liquid crystal polymer substrate formed into a film shape and made into a semi-cured state, or after being formed into a film shape and completely cured. A liquid crystal polymer substrate with an adhesive is used.

前記液晶ポリマー基板あるいは接着材付き液晶ポリマー基板でなる絶縁基板１を用いて配線板を製造するときには、まず、図８（ａ）に示すように、前記絶縁基板１の第１主面１Ａに導体膜２を貼り合わせるとともに、前記絶縁基板１上の第１領域ＡＲ１及び第２領域ＡＲ２にまたがる開口部１Ｃを形成する。このとき、前記導体膜２を貼り合わせる工程と、前記開口部１Ｃを形成する工程は、どちらが先であってもよい。   When manufacturing a wiring board using the liquid crystal polymer substrate or the insulating substrate 1 made of an adhesive-attached liquid crystal polymer substrate, first, as shown in FIG. 8 (a), a conductor is formed on the first main surface 1A of the insulating substrate 1. The film 2 is bonded, and an opening 1C that extends over the first region AR1 and the second region AR2 on the insulating substrate 1 is formed. At this time, either of the step of bonding the conductor film 2 and the step of forming the opening 1C may be first.

次に、図８（ｂ）に示すように、前記絶縁基板１に形成した開口部１Ｃに導電性部材２ｂを充填する。前記導電性部材２ｂを充填するときには、例えば、銅，ニッケル，金，銀，すず、またはそれらの合金を電解めっきや無電解めっきで形成する。また、前記めっきの代わりに、銀ペーストなどの導電性ペーストを充填して硬化させてもよい。またこのとき、前記導電性部材２ｂは、例えば、図８（ｂ）に示したように、前記絶縁基板１の第２主面１Ｂとほぼ同じ高さまで充填する。   Next, as shown in FIG. 8B, a conductive member 2b is filled into the opening 1C formed in the insulating substrate 1. When filling the conductive member 2b, for example, copper, nickel, gold, silver, tin, or an alloy thereof is formed by electrolytic plating or electroless plating. Further, instead of the plating, a conductive paste such as a silver paste may be filled and cured. At this time, the conductive member 2b is filled to the same height as the second main surface 1B of the insulating substrate 1, for example, as shown in FIG.

次に、図８（ｃ）に示すように、前記導体膜２の不要な部分をエッチングで除去して、導体パターン２ａを形成する。前記導体パターン２ａは、アディティブ法やサブトラクティブ法で形成する。またこのとき、前記導体パターン２ａは、例えば、第１領域ＡＲ１の導体パターン２ａと第２領域ＡＲ２の導体パターン２ａを一体的に形成する。   Next, as shown in FIG. 8C, unnecessary portions of the conductor film 2 are removed by etching to form a conductor pattern 2a. The conductor pattern 2a is formed by an additive method or a subtractive method. At this time, for example, the conductor pattern 2a integrally forms the conductor pattern 2a of the first area AR1 and the conductor pattern 2a of the second area AR2.

その後、図示は省略するが、前記絶縁基板１の第１主面１Ａ上の、あらかじめ定められた領域に保護膜６を形成し、前記導体パターン２ａの表面及び前記導電性部材２ｂの表面のそれぞれにめっき５ａ，５ｂを形成すると、図７（ａ）及び図７（ｂ）に示したような配線板が得られる。このとき、前記導電性部材５ｂの表面のめっき５ｂは、例えば、すず，すず−銀合金，すず−銅合金，すず−ビスマス合金，すず−亜鉛合金，金，銀，パラジウムのいずれかのめっきを、電解めっきまたは無電解めっきで形成する。また、前記導体パターン２ａの表面に形成するめっき５ａは、前記導電性部材２ｂの表面のめっき５ｂと同じ金属材料のめっきでも、異なる金属材料のめっきでもよい。なお、図示は省略するが、前記めっき５ａ，５ｂを電解めっきで形成する場合には、前記導体パターン２ａを形成するときに、電解めっき用の給電ラインを同時に形成しておく。   Thereafter, although not shown, a protective film 6 is formed in a predetermined region on the first main surface 1A of the insulating substrate 1, and the surface of the conductor pattern 2a and the surface of the conductive member 2b are respectively When the plating 5a, 5b is formed on the wiring board, a wiring board as shown in FIGS. 7A and 7B is obtained. At this time, the plating 5b on the surface of the conductive member 5b is, for example, any one of tin, tin-silver alloy, tin-copper alloy, tin-bismuth alloy, tin-zinc alloy, gold, silver and palladium. It is formed by electrolytic plating or electroless plating. The plating 5a formed on the surface of the conductor pattern 2a may be the same metal material as the plating 5b on the surface of the conductive member 2b or a different metal material. In addition, although illustration is abbreviate | omitted, when forming the said plating 5a and 5b by electrolytic plating, when forming the said conductor pattern 2a, the electric power feeding line for electrolytic plating is formed simultaneously.

前記手順に沿って形成した配線板を用いて電子装置を製造するときには、まず、図９（ａ）に示すように、前記導体パターン２ａのうち、コンデンサ素子３ｂの陽極３０１ａと電気的に接続される領域に、柱状導体４ｂを形成する。前記柱状導体４ｂは、例えば、銀ペースト等の導電性ペーストを印刷、あるいは塗布して形成する。   When an electronic device is manufactured using a wiring board formed according to the above procedure, first, as shown in FIG. 9A, the conductor pattern 2a is electrically connected to the anode 301a of the capacitor element 3b. The columnar conductor 4b is formed in the region. The columnar conductor 4b is formed by printing or applying a conductive paste such as a silver paste, for example.

次に、図９（ｂ）に示すように、例えば、前記導体パターン２ａのうち、前記コンデンサ素子３ｂの陰極３０２ｂと電気的に接続される領域に、銀ペースト等の導電性接着材４ｃを塗布し、前記コンデンサ素子３ｂを載せた後、前記柱状導体４ｂ及び前記導電性接着材４ｃを硬化させる。   Next, as shown in FIG. 9B, for example, a conductive adhesive 4c such as silver paste is applied to a region of the conductor pattern 2a that is electrically connected to the cathode 302b of the capacitor element 3b. Then, after placing the capacitor element 3b, the columnar conductor 4b and the conductive adhesive 4c are cured.

その後、図９（ｃ）に示すように、前記絶縁基板１の第１主面１Ａ上に、前記コンデンサ素子３ｂが埋まる厚さの絶縁性樹脂（モールドレジン）８を形成する。このとき、前記絶縁基板１上には、前記領域ＡＲが繰り返し設けられているので、各領域ＡＲを切り出して個片化することで、図６（ａ）及び図６（ｂ）に示したような電子装置が得られる。またこのとき、前記配線板において、前記第１領域ＡＲ１から第２領域ＡＲ２にかけて連続的に設けられていた前記導体パターン２ａ及び前記導電性部材２ｂは、前記個片化をする際に切断され、各電子装置の導体パターン２ａ及び導電性部材２ｂとなる。   Thereafter, as shown in FIG. 9C, an insulating resin (mold resin) 8 having a thickness for embedding the capacitor element 3 b is formed on the first main surface 1 </ b> A of the insulating substrate 1. At this time, since the region AR is repeatedly provided on the insulating substrate 1, the regions AR are cut out and separated into pieces, as shown in FIGS. 6A and 6B. Can be obtained. At this time, in the wiring board, the conductive pattern 2a and the conductive member 2b that are continuously provided from the first area AR1 to the second area AR2 are cut when the individualization is performed, It becomes the conductor pattern 2a and the conductive member 2b of each electronic device.

本実施例２の電子装置でも、前記実施例１の電子装置と同様に、前記配線板の絶縁基板１として液晶ポリマーを用いているので、従来のポリイミドテープを用いた配線板に比べて、数GHzから数十GHzの高周波領域での電気特性がよい。また、前記液晶ポリマーは、前記ポリイミドテープと比べて、吸水率が低く、吸湿に対する寸法安定性も高い。また、熱膨張係数の制御も容易である。そのため、前記電子装置を製造する過程や前記電子装置を動作させたときの熱履歴、あるいは周囲の湿度の変化による、前記導体パターン２ａや導電性部材２ｂのはがれ等を低減することができる。   Since the liquid crystal polymer is used as the insulating substrate 1 of the wiring board in the electronic device of the second embodiment as well as the electronic device of the first embodiment, the number is smaller than that of the wiring board using the conventional polyimide tape. Good electrical characteristics in the high frequency range from GHz to several tens of GHz. Further, the liquid crystal polymer has a low water absorption rate and high dimensional stability against moisture absorption as compared with the polyimide tape. Also, the control of the thermal expansion coefficient is easy. Therefore, peeling of the conductive pattern 2a and the conductive member 2b due to a process of manufacturing the electronic device, a thermal history when the electronic device is operated, or a change in ambient humidity can be reduced.

以上説明したように、本実施例２の電子装置によれば、前記絶縁基板１の第１主面１Ａに導体パターン２ａを設け、前記絶縁基板１に設けた開口部１Ｃに導電性部材２ｂを充填した配線板を用い、前記導電性部材２ｂを外部端子として利用することで、前記コンデンサ素子３ｂを用いた電子装置の薄型化が容易になる。   As described above, according to the electronic device of the second embodiment, the conductive pattern 2a is provided on the first main surface 1A of the insulating substrate 1, and the conductive member 2b is provided in the opening 1C provided on the insulating substrate 1. By using the filled wiring board and using the conductive member 2b as an external terminal, the electronic device using the capacitor element 3b can be easily thinned.

また、前記配線板の開口部１Ｃは、従来のコンデンサ素子３ｂを用いた電子装置の配線板において、絶縁基板の第１主面の導体パターンと第２主面の導体パターンを電気的に接続するスルーホールやビアを形成する開口部の穴径よりも十分に大きい。そのため、前記開口部１Ｃの導電性部材２ｂは、充填不良による導通不良が起こりにくく、製造歩留まりが向上する。   Also, the opening 1C of the wiring board electrically connects the conductor pattern on the first main surface and the conductor pattern on the second main surface of the insulating substrate in the wiring board of the electronic device using the conventional capacitor element 3b. It is sufficiently larger than the hole diameter of the opening for forming the through hole or via. Therefore, the conductive member 2b in the opening 1C is less likely to cause poor conduction due to poor filling, and the manufacturing yield is improved.

また、本実施例２の電子装置で用いる配線板は、従来の、両面配線板の製造工程よりも少ない工程で、短時間に製造することができるので、製造コストの上昇を抑えることもできる。   Further, since the wiring board used in the electronic device of the second embodiment can be manufactured in a short time with fewer steps than the conventional double-sided wiring board manufacturing process, an increase in manufacturing cost can be suppressed.

図１０乃至図１２は、前記実施例２の変形例を説明するための模式図であり、図１０（ａ）は第１の変形例の平面図、図１０（ｂ）は図１０（ａ）のＥ−Ｅ’線での断面図、図１１は第２の変形例の断面図、図１２は第３の変形例の平面図である。   10 to 12 are schematic views for explaining a modification of the second embodiment. FIG. 10 (a) is a plan view of the first modification, and FIG. 10 (b) is FIG. 10 (a). FIG. 11 is a sectional view of the second modification, and FIG. 12 is a plan view of the third modification.

前記実施例２の電子装置を製造するときに用いた配線板は、図７（ａ）及び図７（ｂ）に示したように、前記絶縁基板１の第１領域ＡＲ１と第２領域ＡＲ２の２つの領域にまたがる開口部１Ｃを形成し、その開口部１Ｃに前記導電性部材２ｂを充填している。そのため、前記配線板を用いて電子装置を製造したときには、前記導電性部材２ｂを切断しなければならない。このとき、前記導電性部材２ｂとして、例えば、銅やニッケルを用いていると、切断時の衝撃で、前記導電性部材２ｂが前記絶縁基板１からはがれてしまうことがある。   As shown in FIGS. 7A and 7B, the wiring board used when manufacturing the electronic device of Example 2 is provided in the first area AR1 and the second area AR2 of the insulating substrate 1. An opening 1C that extends over two regions is formed, and the opening 1C is filled with the conductive member 2b. Therefore, when an electronic device is manufactured using the wiring board, the conductive member 2b must be cut. At this time, if, for example, copper or nickel is used as the conductive member 2b, the conductive member 2b may be peeled off from the insulating substrate 1 due to an impact at the time of cutting.

そのため、前記導電性部材２ｂを充填する開口部は、例えば、図１０（ａ）及び図１０（ｂ）に示すように、各領域ＡＲ内で独立した開口部１Ｃであってもよい。この場合、前記配線板を用いて電子装置を製造し、前記各領域ＡＲを切り出すときに、前記導電性部材２ｂを切断することはないので、前記導電性部材２ｂが前記絶縁基板１からはがれるのを防ぐことができる。なお、前記各領域ＡＲ内に独立した開口部１Ｃを形成した場合でも、前記開口部１Ｃの穴径は、前記導電性部材２ｂが外部端子として十分に利用できる大きさであり、従来の電子装置で用いる配線板のスルーホール等の穴径に比べて十分に大きい。そのため、導電性部材２ｂの充填不良は起こりにくい。   Therefore, the opening that fills the conductive member 2b may be, for example, an opening 1C that is independent in each region AR, as shown in FIGS. 10 (a) and 10 (b). In this case, when the electronic device is manufactured using the wiring board and the respective regions AR are cut out, the conductive member 2b is not cut, so that the conductive member 2b is peeled off from the insulating substrate 1. Can be prevented. Even when independent openings 1C are formed in each area AR, the hole diameter of the openings 1C is large enough to allow the conductive member 2b to be used as an external terminal. It is sufficiently larger than the hole diameter of the through hole etc. of the wiring board used in. Therefore, poor filling of the conductive member 2b is unlikely to occur.

また、図１０（ａ）及び図１０（ｂ）に示したような配線板を用いて電子装置を製造したときには、前記実施例２の電子装置と異なり、前記絶縁基板１の第２主面１Ｂと直交する面１Ｄから前記導電性部材２ｂが露出することはない。そのため、前記導電性部材２ｂが、銅等の酸化しやすい金属材料であっても、酸化による動作特性の劣化を防ぐことができる。   Further, when an electronic device is manufactured using the wiring board as shown in FIGS. 10A and 10B, unlike the electronic device of the second embodiment, the second main surface 1B of the insulating substrate 1 is used. The conductive member 2b is not exposed from the surface 1D perpendicular to the surface. Therefore, even if the conductive member 2b is a metal material that is easily oxidized, such as copper, it is possible to prevent deterioration in operating characteristics due to oxidation.

またこのとき、前記導電性部材２ｂは、図１０（ｂ）に示したように、前記導電性部材２ｂの表面のめっき５ｂと前記絶縁基板１の第２主面１Ｂがほぼ同じ高さになるように充填してもよいし、図１１に示すように、前記導電性部材２ｂが前記絶縁基板１の第２主面１Ｂとほぼ同じ高さで、前記導電性部材２ｂの表面のめっき５ｂが前記絶縁基板１の第２主面１Ｂから突出するように充填してもよい。   At this time, in the conductive member 2b, as shown in FIG. 10B, the plating 5b on the surface of the conductive member 2b and the second main surface 1B of the insulating substrate 1 have substantially the same height. As shown in FIG. 11, the conductive member 2b is almost the same height as the second main surface 1B of the insulating substrate 1, and the plating 5b on the surface of the conductive member 2b is formed. The insulating substrate 1 may be filled so as to protrude from the second main surface 1B.

また、前記実施例２の電子装置に用いる配線板では、前記導体パターン２ａも、前記第１領域ＡＲ１から第２領域ＡＲ２にかけて一体的に形成しておき、電子装置を製造する最後の工程で切断、分離している。そのため、前記導体パターン２ａが前記絶縁基板の第２主面１Ｂと直交する面１Ｄから露出する。前記導体パターン２ａは、一般に、銅を用いて形成しているので、前記導体パターン２ａの露出面が酸化しやすく、動作特性が劣化しやすい。そのため、前記導体パターン２ａも、前記各領域ＡＲ内で独立するように形成してもよい。   In the wiring board used for the electronic device of the second embodiment, the conductor pattern 2a is also formed integrally from the first area AR1 to the second area AR2, and is cut in the last step of manufacturing the electronic apparatus. Separated. Therefore, the conductor pattern 2a is exposed from the surface 1D orthogonal to the second main surface 1B of the insulating substrate. Since the conductor pattern 2a is generally formed using copper, the exposed surface of the conductor pattern 2a is likely to be oxidized, and the operating characteristics are likely to deteriorate. Therefore, the conductor pattern 2a may also be formed independently in each area AR.

以上、本発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において、種々変更可能であることはもちろんである。   The present invention has been specifically described above based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. is there.

本発明による実施例１の電子装置の概略構成を示す模式図であり、図１（ａ）は電子装置の平面図、図１（ｂ）は図１（ａ）のＡ−Ａ’線での断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic diagram which shows schematic structure of the electronic device of Example 1 by this invention, Fig.1 (a) is a top view of an electronic device, FIG.1 (b) is the AA 'line of Fig.1 (a). It is sectional drawing. 本発明による実施例１の電子装置の概略構成を示す模式図であり、図２（ａ）は電子装置に用いる配線板の平面図、図２（ｂ）は図２（ａ）のＢ−Ｂ’線での断面図である。FIG. 2A is a schematic diagram illustrating a schematic configuration of an electronic device according to a first embodiment of the present invention, FIG. 2A is a plan view of a wiring board used in the electronic device, and FIG. 2B is a BB of FIG. It is sectional drawing in a line. 本実施例１の電子装置に用いる配線板の製造方法を説明するための模式図であり、図３（ａ），図３（ｂ），図３（ｃ），図３（ｄ），図３（ｅ）の各図は配線板の各製造工程における断面図である。FIG. 3 is a schematic diagram for explaining a method of manufacturing a wiring board used in the electronic device of the first embodiment, which is illustrated in FIGS. 3 (a), 3 (b), 3 (c), 3 (d), and 3. Each figure of (e) is sectional drawing in each manufacturing process of a wiring board. 前記実施例１の変形例を説明するための模式図であり、電子装置に用いる配線板の概略構成を示す模式断面図である。It is a schematic diagram for demonstrating the modification of the said Example 1, and is a schematic cross section which shows schematic structure of the wiring board used for an electronic device. 前記実施例１の応用例を説明するための模式図であり、図５（ａ）は配線板の概略構成を示す断面図、図５（ｂ）は図５（ａ）の配線板を用いた電子装置の概略構成を示す断面図である。FIG. 5A is a schematic diagram for explaining an application example of the first embodiment, FIG. 5A is a cross-sectional view illustrating a schematic configuration of a wiring board, and FIG. 5B is a wiring board of FIG. 5A. It is sectional drawing which shows schematic structure of an electronic device. 本発明による実施例２の電子装置の概略構成を示す模式図であり、図６（ａ）は電子装置の平面図、図６（ｂ）は図６（ａ）のＣ−Ｃ’線での断面図である。FIG. 6A is a schematic diagram illustrating a schematic configuration of an electronic device according to a second embodiment of the present invention, FIG. 6A is a plan view of the electronic device, and FIG. 6B is a CC ′ line in FIG. It is sectional drawing. 本発明による実施例２の電子装置の概略構成を示す模式図であり、図７（ａ）は電子装置に用いる配線板の平面図、図７（ｂ）は図７（ａ）のＤ−Ｄ’線での断面図である。FIG. 7A is a schematic diagram illustrating a schematic configuration of an electronic device according to a second embodiment of the present invention, FIG. 7A is a plan view of a wiring board used in the electronic device, and FIG. 7B is a DD of FIG. It is sectional drawing in a line. 本実施例２の電子装置の製造方法を説明するための模式図であり、図８（ａ），図８（ｂ），図８（ｃ）は配線板を製造する各工程の断面図である。FIGS. 8A, 8B, and 8C are cross-sectional views of each process for manufacturing a wiring board. FIGS. 8A, 8B, and 8C are schematic views for explaining a method for manufacturing the electronic device according to the second embodiment. . 本実施例２の電子装置の製造方法を説明するための模式図であり、図９（ａ），図９（ｂ），図９（ｃ）は前記配線板を用いて電子装置を製造する各工程の断面図である。FIGS. 9A, 9B, and 9C are schematic diagrams for explaining a method for manufacturing an electronic device according to the second embodiment. FIGS. 9A, 9B, and 9C are diagrams for manufacturing an electronic device using the wiring board. It is sectional drawing of a process. 前記実施例２の変形例を説明するための模式図であり、図１０（ａ）は第１の変形例の平面図、図１０（ｂ）は図１０（ａ）のＥ−Ｅ’線での断面図である。FIG. 10A is a schematic diagram for explaining a modification of the second embodiment, FIG. 10A is a plan view of the first modification, and FIG. 10B is a line EE ′ of FIG. FIG. 前記実施例２の変形例を説明するための模式図であり、第２の変形例の断面図である。It is a schematic diagram for demonstrating the modification of the said Example 2, and is sectional drawing of a 2nd modification. 前記実施例２の変形例を説明するための模式図であり、第３の変形例の平面図である。It is a schematic diagram for demonstrating the modification of the said Example 2, and is a top view of a 3rd modification.

符号の説明Explanation of symbols

１ 絶縁基板（液晶ポリマー基板）
１Ａ 絶縁基板の第１主面
１Ｂ 絶縁基板の第２主面
１Ｃ 絶縁基板の開口部（貫通穴）
２ 導体膜
２ａ 導体パターン
２ｂ 導電性部材
３ａ 電子部品（半導体チップ）
３０１ａ 半導体チップの外部電極
３ｂ 電子部品（コンデンサ素子）
３０１ｂ コンデンサ素子の陽極
３０２ｂ コンデンサ素子の陰極
３０３ｂ コンデンサ素子の誘電体
４ａ ボンディングワイヤ
４ｂ 柱状導体
４ｃ 導電性接着材
５ａ，５ｂ めっき
６ 保護膜
７ 絶縁性接着材
８ 絶縁性樹脂（モールドレジン）
９ ボール状の外部端子 1 Insulating substrate (liquid crystal polymer substrate)
1A First main surface of insulating substrate 1B Second main surface of insulating substrate 1C Insulating substrate opening (through hole)
2 Conductor film 2a Conductor pattern 2b Conductive member 3a Electronic component (semiconductor chip)
301a External electrode of semiconductor chip 3b Electronic component (capacitor element)
301b Capacitor element anode 302b Capacitor element cathode 303b Capacitor element dielectric 4a Bonding wire 4b Columnar conductor 4c Conductive adhesive 5a, 5b Plating 6 Protective film 7 Insulating adhesive 8 Insulating resin (mold resin)
9 Ball-shaped external terminals

Claims (9)

絶縁基板の第１主面に導体パターンが設けられた配線板と、前記配線板の第１主面側に設けられたチップ状の電子部品と、前記配線板の導体パターンと前記チップ状の電子部品の電極とを電気的に接続する接続導体とを備える電子装置であって、
前記絶縁基板は、前記第１主面及びその裏面（以下、第２主面と称する）に開口端を有し、前記第１主面側の開口端が前記導体パターンでふさがれた開口部が設けられており、
前記開口部に、銅，ニッケル，金，銀，すずあるいはそれらの合金、もしくは導電性ペーストのいずれかでなる導電性部材が充填されていることを特徴とする電子装置。 A wiring board provided with a conductor pattern on the first main surface of the insulating substrate, a chip-like electronic component provided on the first main surface side of the wiring board, a conductor pattern of the wiring board, and the chip-like electronic An electronic device comprising a connection conductor that electrically connects an electrode of a component,
The insulating substrate has an opening end on the first main surface and its back surface (hereinafter referred to as a second main surface), and an opening portion in which the opening end on the first main surface side is blocked by the conductor pattern. Provided,
An electronic device, wherein the opening is filled with a conductive member made of copper, nickel, gold, silver, tin, an alloy thereof, or a conductive paste. 前記絶縁基板は、液晶ポリマーでなることを特徴とする請求項１に記載の電子装置。   The electronic device according to claim 1, wherein the insulating substrate is made of a liquid crystal polymer. 前記導電性部材は、前記絶縁基板の第２主面側の表面に、すず，すず−銀合金，すず−銅合金，すず−ビスマス合金，すず−亜鉛合金，金，銀，パラジウムのいずれかのめっきが設けられていることを特徴とする請求項１または請求項２に記載の電子装置。   The conductive member is formed of any one of tin, tin-silver alloy, tin-copper alloy, tin-bismuth alloy, tin-zinc alloy, gold, silver, and palladium on the surface on the second main surface side of the insulating substrate. The electronic device according to claim 1, wherein plating is provided. 前記絶縁基板の第２主面側に、前記導電性部材もしくはその表面のめっきを底面とする凹部が設けられており、前記凹部に、ボール状の接合材が設けられていることを特徴とする請求項１乃至請求項３のいずれか１項に記載の電子装置。   The second main surface side of the insulating substrate is provided with a concave portion whose bottom surface is the conductive member or plating of the surface thereof, and a ball-shaped bonding material is provided in the concave portion. The electronic device according to claim 1. 絶縁基板の第１主面上のあらかじめ定められた領域内に導体パターンが設けられ、前記導体パターンを設けた領域が繰り返し設けられた配線板であって、
前記絶縁基板は、前記第１主面及びその裏面（以下、第２主面と称する）に開口端を有し、前記第１主面側の開口端が前記導体パターンでふさがれた開口部が設けられており、
前記開口部に、銅，ニッケル，金，銀，すずあるいはそれらの合金、もしくは導電性ペーストのいずれかでなる導電性部材が充填されていることを特徴とする配線板。 A wiring board in which a conductor pattern is provided in a predetermined region on the first main surface of the insulating substrate, and the region provided with the conductor pattern is repeatedly provided,
The insulating substrate has an opening end on the first main surface and its back surface (hereinafter referred to as a second main surface), and an opening portion in which the opening end on the first main surface side is blocked by the conductor pattern. Provided,
A wiring board, wherein the opening is filled with a conductive member made of copper, nickel, gold, silver, tin, an alloy thereof, or a conductive paste. 前記絶縁基板は、液晶ポリマーでなることを特徴とする請求項５に記載の配線板。   The wiring board according to claim 5, wherein the insulating substrate is made of a liquid crystal polymer. 前記導電性部材は、前記絶縁基板の第２主面側の表面に、すず，すず−銀合金，すず−銅合金，すず−ビスマス合金，すず−亜鉛合金，金，銀，パラジウムのいずれかのめっきが設けられていることを特徴とする請求項５または請求項６に記載の配線板。   The conductive member is formed of any one of tin, tin-silver alloy, tin-copper alloy, tin-bismuth alloy, tin-zinc alloy, gold, silver, and palladium on the surface on the second main surface side of the insulating substrate. The wiring board according to claim 5, wherein plating is provided. 前記絶縁基板の第２主面側に、前記導電性部材もしくはその表面のめっきを底面とする凹部が設けられていることを特徴とする請求項５乃至請求項７のいずれか１項に記載の配線板。   The recessed part which makes the bottom surface the said electroconductive member or the plating of the surface is provided in the 2nd main surface side of the said insulated substrate, The any one of Claim 5 thru | or 7 characterized by the above-mentioned. Wiring board. 前記開口部は、前記絶縁基板の第１領域、及び前記第１領域と隣接する第２領域をまたいで設けられていることを特徴とする請求項５乃至請求項８のいずれか１項に記載の配線板。   The said opening part is provided ranging over the 1st area | region of the said insulating substrate, and the 2nd area | region adjacent to the said 1st area | region, The any one of Claim 5 thru | or 8 characterized by the above-mentioned. Wiring board.
JP2003351493A 2003-10-10 2003-10-10 Electronic device and wiring board used therefor Pending JP2005116909A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007150099A (en) * 2005-11-29 2007-06-14 Hitachi Cable Ltd Wiring board and its manufacturing method, and manufacturing method of electronic components using wiring board and its device
JP2008263125A (en) * 2007-04-13 2008-10-30 Shinko Electric Ind Co Ltd Method of manufacturing wiring substrate, method of manufacturing semiconductor device, and wiring substrate
CN106486427A (en) * 2016-11-21 2017-03-08 成都嘉纳海威科技有限责任公司 A kind of package casing based on LCP substrate and preparation method
JP2018006702A (en) * 2016-07-08 2018-01-11 Ｔｏｗａ株式会社 Wiring board, manufacturing method of wiring board, electronic component, and manufacturing method of electronic component

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007150099A (en) * 2005-11-29 2007-06-14 Hitachi Cable Ltd Wiring board and its manufacturing method, and manufacturing method of electronic components using wiring board and its device
JP2008263125A (en) * 2007-04-13 2008-10-30 Shinko Electric Ind Co Ltd Method of manufacturing wiring substrate, method of manufacturing semiconductor device, and wiring substrate
US8237270B2 (en) 2007-04-13 2012-08-07 Shinko Electric Industries Co., Ltd. Wiring board manufacturing method, semiconductor device manufacturing method and wiring board
JP2018006702A (en) * 2016-07-08 2018-01-11 Ｔｏｗａ株式会社 Wiring board, manufacturing method of wiring board, electronic component, and manufacturing method of electronic component
WO2018008214A1 (en) * 2016-07-08 2018-01-11 Ｔｏｗａ株式会社 Wiring board, method for manufacturing wiring board, electronic component, and method for manufacturing electronic component
KR20190025835A (en) * 2016-07-08 2019-03-12 토와 가부시기가이샤 Wiring board, manufacturing method of wiring board, electronic component, and manufacturing method of electronic component
CN109478536A (en) * 2016-07-08 2019-03-15 东和株式会社 Circuit board, the manufacturing method of circuit board, the manufacturing method of electronic component and electronic component
KR102254999B1 (en) * 2016-07-08 2021-05-24 토와 가부시기가이샤 A wiring board, a method for manufacturing a wiring board, an electronic component, and a method for manufacturing an electronic component
CN106486427A (en) * 2016-11-21 2017-03-08 成都嘉纳海威科技有限责任公司 A kind of package casing based on LCP substrate and preparation method

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