CN109474795A - A kind of low-noise pixel circuit structure based on transconductance cell - Google Patents
A kind of low-noise pixel circuit structure based on transconductance cell Download PDFInfo
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- CN109474795A CN109474795A CN201811282037.2A CN201811282037A CN109474795A CN 109474795 A CN109474795 A CN 109474795A CN 201811282037 A CN201811282037 A CN 201811282037A CN 109474795 A CN109474795 A CN 109474795A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
The present invention discloses a kind of low-noise pixel circuit structure based on transconductance cell, including transistor M1-M4, transistor M1 drain terminal connect with transistor M2 source, and transistor M1 source connects with the one end photodiode PPD, and transistor M2 drain terminal meets FD node reset level Vres, transistor M3 grid connects in FD node and source terminates at power supply VDDOne Gm unit of upper formation;Transistor M1 is TG pipe, transfer of the control exposure charge to FD node, transistor M2 is the reset transistor of FD node, transistor M3 leaks termination transistor M4 source, transistor M4 is line EAC SEL, grid connects switching signal, and transistor M4 drain terminal connects one end of switch SH, and another termination of switch SH samples holding capacitor CsOne end, sample holding capacitor CsOther end ground connection, and capacitor reset level V is connect by switch RSTRST, voltage output V is connect by switch READpix.One aspect of the present invention realizes Pixel-level amplification, can reduce input reference noise, on the other hand can also be achieved gain regulation.
Description
Technical field
The present invention relates to cmos image sensor technical field of integrated circuits, and in particular to a kind of based on the low of transconductance cell
Noise pixel circuit structure.
Background technique
In cmos image sensor field, the source level follower (source follower, SF) of pixel, column grade are related double
Sampling (correlated double sampling, CDS), column grade analog-digital converter have contributed much overall noise, therefore
It will limit the imaging performance of sensor.In order to solve this problem, high-gain column grade amplifier or minimum are primarily now used
Change the capacitor of floating diffusion (floating diffusion, FD) node in pixel to realize.However in voltage domain or charge-domain
The middle deterioration that dynamic range is inevitably led to using fixed high-gain amplifier.
Summary of the invention
The purpose of the present invention is being directed to input reference noise existing for cmos image sensor in the prior art, and provide one
Low-noise pixel circuit structure of the kind based on transconductance cell.
The technical solution adopted to achieve the purpose of the present invention is:
A kind of low-noise pixel circuit structure based on transconductance cell, comprising:
The source phase of the drain terminal of transistor M1, transistor M2, transistor M3, transistor M4, transistor M1 and transistor M2
It connects, the source of transistor M1 connects with one end of photodiode PPD, photodiode PPD other end ground connection, transistor M2's
Drain terminal meets FD node reset level Vres, the grid of transistor M3 connects in FD node and source terminates at power supply VDDOn, form a Gm
Unit;Transistor M1 is TG pipe, and transfer of the control exposure charge to FD node, transistor M2 is the reset transistor of FD node,
The leakage of transistor M3 terminates at the source of transistor M4, and transistor M4 is line EAC SEL, and grid meets switching signal, transistor M4
Leakage terminates at one end of switch SH, and another termination of switch SH samples holding capacitor CsOne end, sample holding capacitor CsIt is another
One end ground connection, and capacitor reset level V is connect by switch RSTRST, voltage output V is connect by switch READpix。
The transistor M1 and transistor M2 is NMOS tube, and the transistor M3 and transistor M4 are PMOS tube.
Low-noise pixel circuit structure proposed by the present invention based on transconductance cell, is reduced using amplification method in pixel
It inputs reference noise, and can also realize variable gain.
On the one hand low-noise pixel structure proposed by the present invention realizes Pixel-level amplification, can reduce input reference noise, separately
On the one hand it can also be achieved gain regulation.
Detailed description of the invention
Fig. 1 is the schematic diagram of the low-noise pixel circuit structure based on transconductance cell;
Fig. 2 is that the principle schematic diagram after CDS is integrated in the low-noise pixel structure based on Gm unit.
Specific embodiment
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.It should be appreciated that described herein
Specific embodiment be only used to explain the present invention, be not intended to limit the present invention.
Referring to shown in Fig. 1-2, a kind of low-noise pixel circuit structure based on transconductance cell, including transistor M1-M4, electricity
Hold Cs, photodiode PPD, current source Ibias, switch SH, READ, RST, M1-M4 and photodiode PPD constitute pixel list
Member, wherein transistor M1-M2 is NMOS tube, and M3-M4 is PMOS tube.The source of one end access transistor M1 of photodiode PPD
End, transistor M1 are TG pipe, transfer of the control exposure charge to FD node, the source phase of the drain terminal and transistor M2 of transistor M1
It connects, transistor M2 is the reset transistor of FD node, and the drain terminal of transistor M2 meets FD point reset level Vres, the grid of transistor M3
Pole connects in FD node, and source terminates at power supply VDDOn, a Gm unit is formed, the leakage of transistor M3 terminates at the source of transistor M4
End, transistor M4 are line EAC SEL, and grid connects switching signal, and transistor M4 leaks the one end for terminating at switch SH, the other end of SH
Meet sampling holding capacitor Cs, and capacitor reset level V is connect by switch RSTRST, voltage output V is connect by switch READpix。
The course of work are as follows: when the pixel is selected, line EAC conducting, Gm unit is activated, and generates and FD node voltage
VFDProportional electric current, the short time turn on the switch RST after turn off, will sample holding capacitor CsVoltage amplitude be VRST, next
Turn on the switch SH, electric current is from original levels VRSTStart to CsCharging, charging time Tch, by adjust the charging time, it can be achieved that
Variable gain, charging finish, and turn on the switch READ, by CsOn voltage read, wherein IbiasIt is pixel for column bias current sources
Output line provides electric current, can be realized by current-mirror structure.
Dot structure proposed by the present invention is based on Gm unit, Gm unit and sampling holding capacitor CsGm-C integrator is formed,
The voltage signal of pixel FD node is mainly converted into current signal using Gm unit to export, the output current integration of Gm unit
Holding capacitor C is sampled in column gradesUpper generation voltage output.Ignore the non-ideal effects of circuit, time domain output voltage is writeable are as follows:
Wherein, gmIt is the transconductance value of Gm unit, CsIt is sampling holding capacitor, n is integer, TchIt is to sample filling for holding capacitor
Electric time, TsIt is the sampling period, t is CsThe time of integration, q is CsCharge, I is the output signal electric current of Gm unit, and dt is micro-
Divide symbol, VFDIt is the voltage of FD node.
In the following, the CDS function to pixel circuit of the invention is illustrated:
1, in order to ensure not related between two neighbouring sample operations, by connecting RST before next new sampling
Carry out reset samples holding capacitor.
2 provide enough Gm for Pixel-level, need relatively large-sized transistor M3.
3, the sampling holding capacitor device in each column will consider time constant and gain requirement, while be ensured that relevant
KT/C noise is not dominant.
Fig. 2 shows CDS (column grade correlated-double-sampling is integrated in the low-noise pixel structure based on Gm unit
(correlated double sampling, CDS)) function schematic diagram.
As shown in Fig. 2, the reset signal of pixel reads as V by reset signal accessreset+VRST, pixel exposure signal is logical
Overexposure photo-signal channel reads as Vsignal+VRST, two voltages are subtracted each other by voltage subtraction, obtain signal output Vpix=
Vsignal-Vreset, partial noise can also be reduced by CDS function.
Low-noise pixel structure proposed by the present invention based on Gm unit replaces the SF of conventional pixel by using Gm unit
For structure, it can be achieved that enlarging function inside pixel, reducing input reference noise will not be in pixel without changing reading out structure
Inside introduces extra resistance and capacitor;In addition, by adjusting capacitor charging time Tch, variable gain may be implemented.
The above is only a preferred embodiment of the present invention, it is noted that for the common skill of the art
For art personnel, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications
Also it should be regarded as protection scope of the present invention.
Claims (4)
1. a kind of low-noise pixel circuit structure based on transconductance cell characterized by comprising
The drain terminal of transistor M1, transistor M2, transistor M3, transistor M4, transistor M1 connect with the source of transistor M2, brilliant
The source of body pipe M1 connects with one end of photodiode PPD, photodiode PPD other end ground connection, the drain terminal of transistor M2
Meet FD node reset level Vres, the grid of transistor M3 connects in FD node and source terminates at power supply VDDOn, it is mono- to form a Gm
Member;Transistor M1 is TG pipe, and transfer of the control exposure charge to FD node, transistor M2 is the reset transistor of FD node, brilliant
The leakage of body pipe M3 terminates at the source of transistor M4, and transistor M4 is line EAC SEL, and grid connects switching signal, transistor M4 leakage
One end of switch SH is terminated at, another termination of switch SH samples holding capacitor CsOne end, sample holding capacitor CsIt is another
End ground connection, and capacitor reset level V is connect by switch RSTRST, voltage output V is connect by switch READpix。
2. the low-noise pixel circuit structure based on transconductance cell according to claim 1, which is characterized in that the crystal
Pipe M1 and transistor M2 is NMOS tube, and the transistor M3 and transistor M4 are PMOS tube.
3. a kind of low-noise pixel circuit structure based on transconductance cell characterized by comprising transistor M1, transistor M2,
The drain terminal of transistor M3, transistor M4, transistor M1 connect with the source of transistor M2, the source of transistor M1 and two pole of photoelectricity
One end of pipe PPD connects, and photodiode PPD other end ground connection, the drain terminal of transistor M2 meets FD node reset level Vres, brilliant
The grid of body pipe M3 connects in FD node and source terminates at power supply VDDOn, form a Gm unit;Transistor M1 is TG pipe, and control exposes
Transfer of the optical charge to FD node, transistor M2 are the reset transistor of FD node, and the leakage of transistor M3 terminates at transistor M4
Source, transistor M4 is line EAC SEL, and grid connects switching signal, and transistor M4 leakage terminates at reset signal access and exposure
One end of signal path;Reset signal access is identical as the circuit of exposure signal access, one end of other end voltage subtraction circuit
Another termination voltage output V of subtraction circuit is most pressed in connectionpix, reset signal access and exposure signal access include and crystal
Another termination of the one end for the switch SH that the source of pipe M4 connects, switch SH samples holding capacitor CsOne end, sampling keep electricity
Hold CsOther end ground connection, and capacitor reset level V is connect by switch RSTRST, voltage subtraction circuit is connect by switch READ
One end.
4. the low-noise pixel circuit structure based on transconductance cell according to claim 3, which is characterized in that the crystal
Pipe M1 and transistor M2 is NMOS tube, and the transistor M3 and transistor M4 are PMOS tube.
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CN110108919A (en) * | 2019-04-16 | 2019-08-09 | 天津大学 | The measurement method of PPD pinning voltage in a kind of pixel |
CN112399109A (en) * | 2019-08-15 | 2021-02-23 | 天津大学青岛海洋技术研究院 | Variable conversion gain low noise pixel structure |
CN112399099A (en) * | 2019-08-12 | 2021-02-23 | 天津大学青岛海洋技术研究院 | Charge domain sampling low-noise pixel structure |
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