CN110108919A - The measurement method of PPD pinning voltage in a kind of pixel - Google Patents
The measurement method of PPD pinning voltage in a kind of pixel Download PDFInfo
- Publication number
- CN110108919A CN110108919A CN201910303977.3A CN201910303977A CN110108919A CN 110108919 A CN110108919 A CN 110108919A CN 201910303977 A CN201910303977 A CN 201910303977A CN 110108919 A CN110108919 A CN 110108919A
- Authority
- CN
- China
- Prior art keywords
- voltage
- pipe
- node
- pixel
- inj
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000691 measurement method Methods 0.000 title claims abstract description 7
- 238000002347 injection Methods 0.000 claims abstract description 15
- 239000007924 injection Substances 0.000 claims abstract description 15
- 238000005259 measurement Methods 0.000 claims abstract description 4
- 239000000284 extract Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 abstract description 14
- 238000012360 testing method Methods 0.000 abstract description 12
- 238000012546 transfer Methods 0.000 description 8
- 230000005611 electricity Effects 0.000 description 5
- 238000010998 test method Methods 0.000 description 3
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 2
- 240000002853 Nelumbo nucifera Species 0.000 description 2
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The present invention discloses a kind of measurement method of PPD pinning voltage in pixel, it is realized on 4T dot structure, it adulterates in pixel PPD far from FD node side TD node location n+ to change the distribution of pixel built-in potential, M1 pipe is set as charge and injects gate tube, during pinning voltage tester, in charge injection stage, M1 pipe gating, by injecting charge in TD node, injecting voltage V is adjustedinjMeasure output voltage Vout, obtain Vout‑VinjCurve simultaneously therefrom extracts pinning voltage, passes through injecting voltage VinjRealize measurement pinnig voltage Vpin.The present invention overcomes JFET PPD test structure there are the problem of, during pinnig voltage tester, inject charge in TD node to extract pinning voltage, injected compared to from FD node, not will receive TG voltage influence in test process.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of measurement of PPD pinning voltage in pixel
Method.
Background technique
Pinning voltage is normally defined maximum electrical potential of the PPD in completely depleted situation in pixel PPD, is to embody
One of the important parameter of cmos image sensor pixel performance.Extracting pinnig voltage is that correct adjust transmits gate potential, FD section
Point provides reference to optimize full-well capacity and charge transfer effciency.
The existing method for extracting pinnig voltage is mainly tested structure including the use of the JFET PPD of isolation and is saved from FD
Test method in the pixel of point injection charge.JFET PPD test method uses isolation test structure, but the structure and practical picture
Plain structure difference is larger, reduces the reliability of test result；From the method for FD node injection charge, test result is vulnerable to TG
The influence of voltage.
Summary of the invention
In view of the technical drawbacks of the prior art, it is an object of the present invention to provide PPD in a kind of pixel
The measurement method of pinning voltage, the test method not will receive the influence of TG voltage in charge injection process, and design
Timing under, which can work as normal 4T pixel.
The technical solution adopted to achieve the purpose of the present invention is:
The measurement method of PPD pinning voltage, is realized on 4T dot structure in a kind of pixel, separate in pixel PPD
To change the distribution of pixel built-in potential, setting M1 pipe injects gate tube, M2 as charge for FD node side TD node location n+ doping
Pipe is that reset transistor RST, the M3 pipe of FD node is source level follower SF, and M4 pipe is pixel gate tube SEL；The source of M1 pipe connects TD section
Point, drain terminal meet VDDPower supply；The source of M2 pipe connects FD node and M3 tube grid, and drain terminal meets supply voltage VDD, the drain terminal of M3 pipe connects electricity
Source VDD, source connect the drain terminal of M4 pipe；
During pinning voltage tester, in charge injection stage, M1 pipe gating is adjusted by injecting charge in TD node
Save injecting voltage VinjMeasure output voltage Vout, obtain Vout-VinjCurve simultaneously therefrom extracts pinning voltage, passes through injection electricity
Press VinjRealize measurement pinnig voltage Vpin。
As output voltage VoutExactly 0 when corresponding injecting voltage VinjAs pinnig voltage Vpin。
Compared with prior art, the beneficial effects of the present invention are:
The present invention overcomes JFET PPD test structure there are the problem of；And during pinnig voltage tester, remote
TD node from FD node side carries out charge injection, by adjusting injecting voltage VinjAnd corresponding output is measured, obtain Vout-
VinjCurve, and pinning voltage is therefrom extracted, compared to the method injected from FD node, which is being surveyed
The influence of TG voltage is not will receive during examination.
Detailed description of the invention
Fig. 1 show test pixel structure；
Fig. 2 show Potential Distributing schematic diagram；
Fig. 3 show pinnig voltage tester timing, wherein VinjDuring pinnig voltage tester, charge injects rank
The injecting voltage of section；
Fig. 4 show pixel and works normally timing, wherein Vinj0For in pixel course of normal operation, charge injection stage
Injecting voltage, Vinj0=Vpin；
It is respectively V shown in Fig. 5 a-5cinj>Vpin,Vinj=VpinAnd Vinj<VpinIn the case of, signal charge charge inject,
Charge transmission and signal read the potential schematic diagram of three phases；
Fig. 6 show Vout-VinjCurve, wherein VpinFor VoutIt is by chance corresponding V for 0injValue.
Specific embodiment
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.It should be appreciated that described herein
Specific embodiment be only used to explain the present invention, be not intended to limit the present invention.
The present invention realizes on the basis of 4T dot structure, carries out n+ doping (TD section far from FD node side in pixel PPD
Point) for changing the distribution of pixel built-in potential, the gate tube that is injected as charge of addition M1 pipe, pixel specific structure as shown in Figure 1,
In completely depleted situation, the Potential Distributing in pixel is as shown in Fig. 2, each pipe connection type is as follows in pixel: M1 is switching tube SW,
M2 is that the reset transistor RST, M3 of FD node are source level follower SF, and M4 is pixel gate tube SEL.The source of M1 connects TD node and (surveys
Diode node test diode is tried, which is used to store the injection charge for measuring pinning voltage), drain terminal meets VDD
Power supply, the source of M2 connect FD node and M3 grid, and drain terminal meets supply voltage VDD, the drain terminal of M3 meets power vd D, and source connects the leakage of M4
End.
Pinning voltage tester timing and pixel normal work timing difference are as shown in Figure 3 and Figure 4.During the test,
Charge injection stage M1 pipe gating, by adjusting injecting voltage VinjAnd measure corresponding output voltage Vout, obtain Vout-VinjIt is bent
Line is as shown in fig. 6, work as V in curveoutExactly 0 when, corresponding VinjAs pinnig voltage Vpin。
(1) pinnig voltage tester process:
As shown in Fig. 2, charge injection stage, by VDDIt is reduced to Vinj, M1 pipe gates during this pinnig voltage tester,
Charge is injected into TD node；In the stage of reading, during M4 pipe gating, M2 pipe, M3 pipe are gated respectively by signal in the region FD
Charge is read；In reseting stage, M2 pipe gating resets the region FD, and M1 pipe gating resets the region TD and the region PPD.
During the test, under certain injection length, change Vinj, measure corresponding output voltage.Charge is in pixel
Transmission process be divided into 3 kinds of situations, as illustrated in figs. 5 a-5 c.
Work as Vinj>VpinWhen, as shown in Figure 5 a, TD potential is greater than PPD potential, cannot be introduced into PPD, opened in transfer tube TG
Cheng Zhong, charge can not be from PPD and TD zone-transfer to FD, therefore output voltage is 0；
Work as Vinj=VpinWhen, as shown in Figure 5 b, TD potential is exactly equal to PPD potential, in transfer tube TG opening process, electricity
Lotus can not be transferred to the region FD, therefore output voltage remains as 0；
Work as Vinj<VpinWhen, as shown in Figure 5 c, TD potential is less than PPD maximum electrical potential, in transfer tube TG opening process, electricity
Gesture is less than the charge of the part Vpin from PPD and TD zone-transfer to FD, therefore output voltage is not 0.
Therefore, in Fig. 6, Vout-VinjWork as V in curveoutExactly 0 when corresponding VinjAs pinnig voltage Vpin。
(2) course of normal operation:
As shown in figure 3, charge injection stage, sets VDDFor Vinj0(Vinj0=Vpin), M1 pipe gates in the process, electricity
Lotus is injected into TD node.The region TD is filled up by charge just at this time, and situation is identical as Fig. 5 b.Injection only the most incipient stage into
Row, post-exposure, reading, reseting procedure it is identical as tradition 4T pixel operation process.In the stage of reading, during M4 pipe gating,
M2 pipe, M3 pipe gate read signal charge in the region FD respectively；In reseting stage, M2 pipe gates reset with transfer tube TG simultaneously
PPD and the region FD.
The test pixel structure can work in the case where designing timing as normal pixel, overcome JFET PPD survey
Try structure there are the problem of；And during pinnig voltage tester, charge note is carried out in the TD node far from FD node side
Enter, by adjusting injecting voltage VinjAnd corresponding output is measured, obtain Vout-VinjCurve, and pinning voltage is therefrom extracted,
Compared to the method injected from FD node, which not will receive transfer tube TG voltage during the test
It influences.
The above is only a preferred embodiment of the present invention, it is noted that for the common skill of the art
For art personnel, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications
Also it should be regarded as protection scope of the present invention.
Claims (2)
1. the measurement method of PPD pinning voltage in a kind of pixel, which is characterized in that realized on 4T dot structure, in picture
Plain PPD is adulterated far from FD node side TD node location n+ to change the distribution of pixel built-in potential, and setting M1 pipe is injected as charge
Gate tube, M2 pipe are that reset transistor RST, the M3 pipe of FD node is source level follower SF, and M4 pipe is pixel gate tube SEL；M1 pipe
Source connects TD node, and drain terminal meets VDDPower supply；The source of M2 pipe connects FD node and M3 tube grid, and drain terminal meets supply voltage VDD, M3 pipe
Drain terminal meet power vd D, source connects the drain terminal of M4 pipe；
During pinning voltage tester, in charge injection stage, M1 pipe gating adjusts note by injecting charge in TD node
Enter voltage VinjMeasure output voltage Vout, obtain Vout-VinjCurve simultaneously therefrom extracts pinning voltage, passes through injecting voltage Vinj
Realize measurement pinnig voltage Vpin。
2. the measurement method of PPD pinning voltage in pixel as described in claim 1, which is characterized in that as output voltage Vout
Exactly 0 when corresponding injecting voltage VinjAs pinnig voltage Vpin。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910303977.3A CN110108919A (en) | 2019-04-16 | 2019-04-16 | The measurement method of PPD pinning voltage in a kind of pixel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910303977.3A CN110108919A (en) | 2019-04-16 | 2019-04-16 | The measurement method of PPD pinning voltage in a kind of pixel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110108919A true CN110108919A (en) | 2019-08-09 |
Family
ID=67485466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910303977.3A Pending CN110108919A (en) | 2019-04-16 | 2019-04-16 | The measurement method of PPD pinning voltage in a kind of pixel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110108919A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001047021A1 (en) * | 1999-12-21 | 2001-06-28 | Conexant Systems, Inc. | Method and apparatus for achieving uniform low dark current with cmos photodiodes |
| CN101281918A (en) * | 2006-12-01 | 2008-10-08 | 国际商业机器公司 | Active pixel sensor unit structure and method for forming the structure |
| CN101533767A (en) * | 2008-12-31 | 2009-09-16 | 昆山锐芯微电子有限公司 | Semiconductor device, metal-insulator-metal capacitor and method for manufacturing same |
| CN102595059A (en) * | 2012-02-27 | 2012-07-18 | 天津大学 | Pixel structure and multiple exposure method thereof |
| CN103384999A (en) * | 2011-01-02 | 2013-11-06 | 匹克希姆公司 | Conversion gain modulation using charge sharing pixel |
| CN105120186A (en) * | 2015-09-16 | 2015-12-02 | 上海集成电路研发中心有限公司 | Pixel unit structure with adjustable conversion gain and signal collection method therefor |
| CN105578084A (en) * | 2015-12-28 | 2016-05-11 | 上海集成电路研发中心有限公司 | 3T CMOS (Complementary Metal-Oxide-Semiconductor Transistor) pixel unit structure and signal acquisition method thereof |
| CN205883411U (en) * | 2015-09-23 | 2017-01-11 | 半导体元件工业有限责任公司 | Image sensor pixel and imaging system |
| CN207369146U (en) * | 2016-05-03 | 2018-05-15 | 半导体元件工业有限责任公司 | Image pixel and imaging sensor |
| CN109474795A (en) * | 2018-10-31 | 2019-03-15 | 天津大学 | A kind of low-noise pixel circuit structure based on transconductance cell |
-
2019
- 2019-04-16 CN CN201910303977.3A patent/CN110108919A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001047021A1 (en) * | 1999-12-21 | 2001-06-28 | Conexant Systems, Inc. | Method and apparatus for achieving uniform low dark current with cmos photodiodes |
| CN101281918A (en) * | 2006-12-01 | 2008-10-08 | 国际商业机器公司 | Active pixel sensor unit structure and method for forming the structure |
| CN101533767A (en) * | 2008-12-31 | 2009-09-16 | 昆山锐芯微电子有限公司 | Semiconductor device, metal-insulator-metal capacitor and method for manufacturing same |
| CN103384999A (en) * | 2011-01-02 | 2013-11-06 | 匹克希姆公司 | Conversion gain modulation using charge sharing pixel |
| CN102595059A (en) * | 2012-02-27 | 2012-07-18 | 天津大学 | Pixel structure and multiple exposure method thereof |
| CN105120186A (en) * | 2015-09-16 | 2015-12-02 | 上海集成电路研发中心有限公司 | Pixel unit structure with adjustable conversion gain and signal collection method therefor |
| CN205883411U (en) * | 2015-09-23 | 2017-01-11 | 半导体元件工业有限责任公司 | Image sensor pixel and imaging system |
| CN105578084A (en) * | 2015-12-28 | 2016-05-11 | 上海集成电路研发中心有限公司 | 3T CMOS (Complementary Metal-Oxide-Semiconductor Transistor) pixel unit structure and signal acquisition method thereof |
| CN207369146U (en) * | 2016-05-03 | 2018-05-15 | 半导体元件工业有限责任公司 | Image pixel and imaging sensor |
| CN109474795A (en) * | 2018-10-31 | 2019-03-15 | 天津大学 | A kind of low-noise pixel circuit structure based on transconductance cell |
Non-Patent Citations (1)
| Title |
|---|
| ZHIYUAN GAO等: "Analysis and Modeling of the Light-Dependent Full Well Capacity of the 4-T Pixel in CMOS Image Sensors", 《IEEE》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106124829B (en) | The extracting method of field effect transistor dead resistance and channel parameter | |
| US20130054210A1 (en) | Method for Determining BSIMSOI4 DC Model Parameters | |
| CN105046247A (en) | Surface structure identification unit and circuit, identification method and electronic device | |
| CN102608503B (en) | Method and system for high-accuracy simultaneous observation of long air gap | |
| CN101135716B (en) | Method and apparatus for measuring leakage current | |
| CN103929600B (en) | The shared dot structure of high sensitivity cmos image sensor | |
| CN102843139A (en) | Method and device for digitalizing scintillation pulse | |
| CN102176215B (en) | Modeling method for SPICE model series of SOI (Silicon on Insulator) field effect transistor | |
| CN205404673U (en) | Electrified measuring device of portable line current | |
| CN108318796A (en) | A kind of silicon carbide-based power device interfacial state test method in three ports | |
| Shen et al. | A silicon photomultiplier readout ASIC for time-of-flight applications using a new time-of-recovery method | |
| CN104316855A (en) | Junction temperature testing method of HEMT (High Electron Mobility Transistor) device | |
| CN110108919A (en) | The measurement method of PPD pinning voltage in a kind of pixel | |
| CN102176442A (en) | Test structure and method for measuring HCI (hot carrier injection) reliability of MOS (metal oxide semiconductor) device | |
| CN106482829A (en) | The dynamic and static combined test system of single-photon detector and its method of testing | |
| CN107942220B (en) | Method for testing bias voltage temperature instability applied to MOS device | |
| CN109005374A (en) | Image sensor pixel circuit and its working method | |
| CN104469347B (en) | The testing circuit of video transmission cable and video frequency output chip | |
| CN102799697A (en) | Low-temperature CMOS (Complementary Metal-Oxide-Semiconductor Transistor) modeling method | |
| CN102982847B (en) | A kind of test system and method for the parasitic parameter of SRAM | |
| CN105578084B (en) | A kind of 3T cmos pixel cellular construction and its signal acquisition method | |
| CN203178465U (en) | Electronic transformer output calibration device | |
| CN108287636B (en) | Pressure sensing module, driving method, pressure sensing circuit and display device | |
| CN103389443B (en) | The method of testing of dynamic breakdown voltage of silicon on insulator MOS device | |
| CN103091572A (en) | Signal testing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190809 |