CN202979124U - High gain photoelectric detector unit reading circuit having function of correlated double sampling - Google Patents

Abstract

The utility model relates to a high gain photoelectric detector unit reading circuit having a function of correlated double sampling. The circuit comprises a high gain cascode amplifier, a set of integrator capacitors comprising a capacitor Cint1, Cint2 and a mode gating switch Smod, a sampling capacitor Csh, a sampling switch Ssh, a column selection switch Ssel, a set of integrator switches which comprise a switch set Sint and a switch set Sintd and have the function of correlated double sampling, and a pair of mirror image current sources comprising a transistor M5 and a current source IBIAS, wherein transistors M1, M2, M3 and M4 form the high gain cascode amplifier, VBIASP1 and VBIASP2 respectively provide fixed bias voltages for the M2 and the M3, so injection efficiency of a photoelectric detector can be effectively improved. The special integrator switches have the function of correlated double sampling to facilitate simplification of a circuit structure and saving of a chip area and power consumption. An integrator voltage sampling mode based on charge transfer can effectively reduce influence of column bus parasitic capacitance. The circuit can effectively guarantee stable work of an infrared imaging system.

Description

High-gain photodetector unit reading circuit with the correlated-double-sampling function

Technical field

The utility model relates to a kind of reading circuit, particularly a kind of high-gain photodetector unit reading circuit with the correlated-double-sampling function.

Background technology

Infrared imaging system is comprised of optical lens, detector array, reading circuit and digital imagery algorithm.The effect of reading circuit be with the faint light current signal that Infrared Detectors produces amplify, denoising and analog signal figure conversion.Along with the development of modern infrared technology, the performance of reading circuit has become the deciding factor of infrared imaging system quality.Due to the continuous progress of semiconductor process techniques, infrared focal plane array increases gradually, and size and the power consumption of reading circuit also had higher requirement.And in the unit reading circuit, the element integral device is owing to directly being connected with detector, play photoelectric current pre-amplification and the effect that improves driving force, so its performance directly determined the quality of whole reading circuit system.

The unit reading circuit adopts the form of charge integration usually, collects the detector photogenerated charge and is converted into voltage signal and read.The performance requirement of element integral device mainly contains: element integral device circuit area is limited by pixel cell area, and this just means that the integrator circuit structure usually can not be too complicated, and the number of devices of using is too much unsuitable; Element integral device noise is less than noise of detector; Element integral device working temperature is identical with the detector working temperature, and has good impedance matching; The element integral device should have the good linearity and responsiveness; It is low that element integral device power consumption should be tried one's best, and affects the detector working temperature to avoid the excessive heat radiation of circuit, causes detector performance to descend.

Infrared focal plane array commonly used unit reading circuit mainly comprises: direct detector integration (DDI) structure, directly injecting structure (DI), buffering are directly injected (BDI) structure, grid modulation input (GMI) structure, electric capacity trsanscondutance amplifier (CTIA) structure etc.Wherein, the CTIA structure advantages such as injection efficiency is high owing to having, the linearity is good become unit reading circuit structure desirable under a lot of applied environments.Limit but be subject to the reading circuit cellar area, in the CTIA structure, amplifier adopts the structure of simple common-source amplifier or five pipe differential amplifiers usually, and its voltage gain is usually very low, can't satisfy the application demand to the very high read-out system of linearity.Simultaneously, due to the CTIA structure in the process that integrating capacitor resets, be subjected to the impact of semiconductor process variation, can produce fixed pattern noise (FPN), therefore the rear class at the unit reading circuit that usually needs connects one-level correlated-double-sampling (CDS) circuit, in order to eliminate FPN, the area of whole like this circuit, power consumption and complexity all can improve.

Therefore, provide a kind of simple in structure, dependable performance, the high-gain photodetector unit reading circuit with the correlated-double-sampling function easy and simple to handle is one of these those skilled in the art problem that need address.

The utility model content

The purpose of this utility model is to overcome above-mentioned weak point, and a kind of simple in structure, reasonable in design, dependable performance, the high-gain photodetector unit reading circuit with the correlated-double-sampling function that applicability is strong are provided.

The technical scheme that adopts of the utility model is for achieving the above object: a kind of high-gain photodetector unit reading circuit with the correlated-double-sampling function, it is characterized in that this circuit is by a high-gain common source and common grid amplifier, one group of integrating capacitor, a sampling capacitance, a sampling switch, a column selection switch, one group of integral restrictor and a pair of mirror current source with the correlated-double-sampling function connects to form;

Wherein, one group of integrating capacitor is connected across the common source and common grid amplifier input, exports two ends, and completing the faint light current conversion is the function of integral voltage signal; The integrating capacitor group that is made of capacitor C int1, Cint2 and pattern gating switch Smod is controlled by pattern gating switch Smod, realizes the regulation and control of different charge storage;

Control respectively integral restrictor Sint and Sintd by one group of inversion clock, realize the offset voltage correlated-double-sampling of eliminating and the function that increases the integral voltage output area;

A pair of mirror current source is made of transistor M5 and current source IBIAS;

Sampling switch Ssh is combined with sampling capacitance Csh serial connection mode, coordinates column selection switch S sel to realize the row reading out structure of charge transfer type.

The beneficial effects of the utility model are: the high-gain common source and common grid amplifier that this circuit is provided with can effectively improve the injection efficiency of photodetector.

Unique integral restrictor sequential has the correlated-double-sampling function, is of value to the simplification circuit structure, saving chip area and power consumption.Can effectively reduce the impact of column bus parasitic capacitance based on the integral voltage sampled form of electric charge transfer.

The utility model is simple in structure, reasonable in design, dependable performance, applicability are strong; Be applied to infrared imaging system, the work that the effective guarantee infrared imaging system is stable, effect highly significant.

Description of drawings

Fig. 1 is traditional CT IA element circuit schematic diagram;

Fig. 2 is the utility model CTIA element circuit schematic diagram.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, details are as follows to embodiment, structure, feature that foundation the utility model provides:

At first analyze traditional CTIA element circuit, as shown in Figure 1, traditional CT IA structure it comprise integrating capacitor Cint on feedback control loop of an operational amplifier OPAMP,, reset transistor switch M1 in parallel with integrating capacitor and one-cell switching switch M2.At reseting stage, reset switch M1 is closed, is equivalent to the integrating capacitor shorted on both ends, and to the integrating capacitor discharge, due to the empty short characteristic of operational amplifier, amplifier output voltage resets to Vbias simultaneously.After integration began, constant detector photoelectric current was to the integrating capacitor integration, and amplifier output voltage becomes:

$V_{\mathrm{out}}=V_{\mathrm{bias}}+\frac{A}{1+A}\·\frac{I\×t}{C_{\mathrm{int}}}---\left(1\right)$

Wherein, I is the detector photoelectric current, and t is the time of integration, and Cint is the integrating capacitor value, and A is the amplifier open-loop gain.Can find out from formula, the injection efficiency of CTIA is:

${\mathrm{\η}}_{\mathrm{int},\mathrm{CTIA}}=\frac{A}{1+A}---\left(2\right)$

Therefore, as long as amplifier open-loop gain A is enough large, just can guarantee very high injection efficiency, but a very large problem of CTIA structure is exactly the existence due to amplifier offset voltage Voff, just make the starting voltage of integrator output voltage become Vbias+Voff from Vbias, due to the inconsistency of Voff in pel array, finally can cause FPN, therefore usually to increase one-level CDS circuit after the CTIA circuit, to eliminate FPN.

the CTIA element circuit structure that the utility model proposes, as shown in Figure 2, a kind of high-gain photodetector unit reading circuit with the correlated-double-sampling function, this circuit by a high-gain common source and common grid amplifier (by transistor M1, M2, M3 and M4 consist of, VBIASP1 and VBIASP2 are respectively M2 and the M3 pipe provides fixed bias voltage), one group of integrating capacitor is (by capacitor C int1, Cint2 and pattern gating switch Smod consist of), a sampling capacitance (Csh), a sampling switch (Ssh), a column selection switch (Ssel), one group of integral restrictor with the correlated-double-sampling function (switches set Sint and Sintd) and a pair of mirror current source (being made of transistor M5 and current source IBIAS) form.

Wherein, the common source and common grid amplifier that main amplifier adopts is in series by two PMOS pipes and two NMOS pipes, realizes that gain improves function.

One group of integrating capacitor is connected across amplifier input and output two ends, and completing the faint light current conversion is the function of integral voltage signal.The integrating capacitor group is controlled by pattern gating switch Smod, and (as shown in Figure 2) realizes the regulation and control of different charge storage.

Control respectively integral restrictor Sint and Sintd by one group of inversion clock, realize the offset voltage correlated-double-sampling of eliminating and the function that increases the integral voltage output area; Namely by the alternately gating (as shown in Figure 2) of switches set Sint and Sintd, complete correlated-double-sampling and increase the integral voltage output area.

Sampling switch Ssh is combined with sampling capacitance Csh serial connection mode, and (as shown in Figure 2) coordinates column selection switch S sel to realize the row reading out structure of charge transfer type, can effectively reduce the impact that the column bus parasitic capacitance is read integral voltage.

The utility model has adopted a kind of CTIA structure with inner CDS function, need not extra CDS circuit and just can eliminate the FPN that causes due to the amplifier imbalance.Simultaneously, in order to reduce circuit area, do not adopt traditional differential amplifier structure yet in the design of amplifier, but used the common source and common grid amplifier structure of a high-gain, and in order to reduce noise, the amplifier input pipe has used low noise PMOS pipe.

In circuit, the Smod switch is the gating switch of two kinds of different charge storage patterns, by opening or closing Smod, realizes that the switching of different charge storage is to adapt to different application demands.Compare with traditional CTIA circuit, increased by two groups of integral control switches in the structure that the utility model proposes.Its operation principle is: at reseting stage, the Sint switch is closed, the Sintd switch disconnects, and be not simply with the short circuit at integrating capacitor two ends and be connected across respectively on the input/output terminal of amplifier this moment, but the bottom crown of integrating capacitor is connected on a fixed reference level VREF2; When integration phase begins, the Sint switch disconnects, and the Sintd switch is closed, and constant detector photoelectric current is to the integrating capacitor integration, and amplifier output voltage becomes:

$V_{\mathrm{out}}=V_{\mathrm{REF}2}+\frac{A}{1+A}\·\frac{I\×t}{C_{\mathrm{int}}}---\left(3\right)$

The starting voltage of comparing with formula (1) due to integral output voltage is a fixed reference level VREF2 who has nothing to do with amplifier performance, therefore, can not produce the problem of FPN.Simultaneously, by Rational choice VREF2 value, make it less than the output voltage that resets of amplifier, can also suitably increase the output voltage range of element circuit.In order to guarantee that CTIA has sufficiently high injection efficiency, amplifier circuit adopts high-gain common source and common grid amplifier structure, and its open-loop gain is:

$A=\frac{1}{2}{g}_{m1}(g_{m2}{R}_{\mathrm{ds}1}{R}_{\mathrm{ds}2}//g_{m3}{R}_{\mathrm{ds}3}{R}_{\mathrm{ds}4})---\left(4\right)$

Wherein, gm1, gm2 and gm3 are respectively the mutual conductance of transistor M1, M2 and M3, and Rds1, Rds2, Rds3 and Rds4 are respectively the output impedance of transistor M1, M2, M3 and M4.Than traditional amplifier architecture, its gain can improve nearly 40dB.

The biasing circuit of Unit Amplifier adopts row to share bias structure, and to reduce power consumption, the bias circuit of every row is outside in cell array simultaneously, to save limited cellar area.

The row output circuit adopts the charge transfer type amplifier architecture, to adapt to integral voltage sampled form of the present utility model.

Above-mentionedly with reference to embodiment, this high-gain photodetector unit reading circuit with the correlated-double-sampling function is described in detail; illustrative rather than determinate; therefore in the variation and the modification that do not break away under the utility model general plotting, within should belonging to protection range of the present utility model.

Claims (5)

1. high-gain photodetector unit reading circuit with the correlated-double-sampling function, it is characterized in that this circuit is by a high-gain common source and common grid amplifier, one group of integrating capacitor, a sampling capacitance, a sampling switch, a column selection switch, one group of integral restrictor and a pair of mirror current source with the correlated-double-sampling function connects to form;

Wherein, one group of integrating capacitor is connected across the common source and common grid amplifier input, exports two ends; The integrating capacitor group that is made of capacitor C int1, Cint2 and pattern gating switch Smod is controlled by pattern gating switch Smod;

Control respectively integral restrictor Sint and Sintd by one group of inversion clock, realize the offset voltage correlated-double-sampling of eliminating and the function that increases the integral voltage output area;

A pair of mirror current source is made of transistor M5 and current source IBIAS;

Sampling switch Ssh is combined with sampling capacitance Csh serial connection mode, coordinates column selection switch S sel to realize the row reading out structure of charge transfer type.

2. the high-gain photodetector unit reading circuit with the correlated-double-sampling function according to claim 1, is characterized in that described common source and common grid amplifier is in series by two PMOS pipes and two NMOS pipes.

3. the high-gain photodetector unit reading circuit with the correlated-double-sampling function according to claim 1, is characterized in that the alternately gating by switches set Sint and Sintd, completes correlated-double-sampling and increase the integral voltage output area.

4. the high-gain photodetector unit reading circuit with the correlated-double-sampling function according to claim 1, the connected mode that it is characterized in that described sampling switch and sampling capacitance is the row playback mode that is conducive to realize charge transfer type.

5. the high-gain photodetector unit reading circuit with the correlated-double-sampling function according to claim 1, is characterized in that controlling by the Smod switch selection that realizes different charge storage.

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