CN112399109A - Variable conversion gain low noise pixel structure - Google Patents

Variable conversion gain low noise pixel structure Download PDF

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Publication number
CN112399109A
CN112399109A CN201910752320.5A CN201910752320A CN112399109A CN 112399109 A CN112399109 A CN 112399109A CN 201910752320 A CN201910752320 A CN 201910752320A CN 112399109 A CN112399109 A CN 112399109A
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China
Prior art keywords
signal
transistor
reset
capacitor
selection transistor
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CN201910752320.5A
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Chinese (zh)
Inventor
徐江涛
陈全民
高静
聂凯明
查万斌
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Tianjin University Marine Technology Research Institute
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Tianjin University Marine Technology Research Institute
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Priority to CN201910752320.5A priority Critical patent/CN112399109A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

A variable conversion gain low noise pixel structure comprises a Photodiode (PD), a charge transfer Transistor (TX), a reset transistor (RST), a signal Converter (CA), a selection transistor (SEL), a current source (I), a sampling holding capacitor (C), a capacitor setting tube (SET) and a buffer (buffer); compared with the traditional 4T pixel structure, the conversion gain of the FD node can be changed by controlling the turn-on time of the row selection transistor in the sequential circuit, so that various conversion gains are realized. The high conversion gain mode is used under low light to reduce noise influence, and the low conversion gain mode is used under strong light to realize high full-well capacity, so that the imaging requirements at night and in the daytime can be met.

Description

Variable conversion gain low noise pixel structure
Technical Field
The invention belongs to the field of low-light-level image sensors, and particularly relates to a variable conversion gain low-noise pixel structure.
Background
A CMOS Image Sensor (CIS) that can effectively image under low light conditions is called a low-light image sensor. 1 mil lux is comparable to clear starnight luminance without a moon, while 0.1 mil lux is the luminance of a cloudy day without a moon. Imaging at night on a cloudy day may be desirable in some security settings and higher sensitivity may be desirable for this type of image sensor. Sensitization under very low light conditions generally requires optimization of the image sensor design, especially the ability of the pixel portion to image in the absence of photons. However, noise introduced during readout of image sensor pixel signals can have a significant impact on the overall imaging system, and in severe cases, render the output image useless.
In order to solve the noise problem of the low-light image sensor, the most direct method is to design a low-noise pixel and a readout circuit, or to increase the intensity of a signal before noise is introduced, so that the noise introduced by the readout circuit is equivalently reduced. To reduce noise, buried channel devices may be used to reduce 1/f noise. Reset noise and the like can be reduced using a Correlated Double Sampling (CDS) operation. Increasing the Conversion Gain (CG) of a pixel to increase signal strength is currently an effective method to effectively reduce the effect of noise introduced later.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a variable conversion gain low-noise pixel structure. Compared with the traditional 4T pixel structure, the conversion gain of the FD node can be changed by controlling the turn-on time of the row selection transistor in the sequential circuit, so that various conversion gains are realized. The high conversion gain mode is used under low light to reduce noise influence, and the low conversion gain mode is used under strong light to realize high full-well capacity, so that the imaging requirements at night and in the daytime can be met.
A variable conversion gain low noise pixel structure, as shown in FIG. 1, includes a Photodiode (PD), a charge transfer Transistor (TX), a reset transistor (RST), a signal Converter (CA), a selection transistor (SEL), a current source (I), a sample hold capacitor (C), a capacitor SET transistor (SET), and a buffer (buffer);
the photoelectric diode, the charge transfer transistor, the reset transistor, the signal converter and the selection transistor are realized in a pixel part, the current source, the sampling holding capacitor, the capacitor setting tube and the buffer are realized in a column-level circuit part, the charge transfer transistor and the capacitor setting tube are NMOS, and the reset transistor, the signal converter and the selection transistor are PMOS;
VDD is power voltage, GND is 0 potential, FD node is signal conversion node, VrstA reference voltage that sets the sample-and-hold capacitor.
The photodiode is used for realizing a photoelectric conversion function and absorbing photons to generate charges; a charge transfer transistor for controlling transfer of photo-generated charge to the FD node; the reset transistor is used for resetting the photodiode and the FD node before exposure begins; the signal converter is used for converting the charge signal of the FD node into a current signal and outputting the current signal; the selection transistor is used for controlling the on and off of the pixel part and the column stage circuit; the current source is used for providing bias; the sampling holding capacitor is used for receiving and temporarily storing the signal; the capacitor setting tube is used for resetting the sampling holding capacitor to the voltage Vrst(ii) a The buffer is used for driving a subsequent circuit.
As shown in FIG. 1, the signal converter is a PMOS transistor, and the circuit after the PMOS transistor forms a common source amplifier, which ideally has a DC voltage gain of gmT/C, wherein gmT is the sampling time and C is the size of the sampling holding capacitor.
The working sequence of the variable conversion gain low noise pixel structure of the invention is shown in fig. 2:
the working principle of the variable conversion gain low-noise pixel structure is as follows:
(1) when the pixel is exposed, the photodiode receives photons and converts the photons into charges for storage, after the exposure is finished, the reset transistor is firstly started to reset the FD node, and after the reset is finished, the reset transistor is closed;
(2) before the reading of the reset signal is started, a capacitor setting tube is opened to set the voltage on the sampling holding capacitor to be VrstAnd the selection transistor is turned on in the setting process, and the voltage on the sampling holding capacitor is subjected to VrstClamping and keeping unchanged, when the capacitor set signal set is at low level after the time t, starting to charge the sampling holding capacitor until the selection transistor is switched off, and at the moment, passing through the bufferThe output is a reset signal Vreset；
(3) After the reset signal is read out, the charge transfer transistor is turned on to transfer the charge in the photodiode to the FD node, and optical signal reading is prepared. Before the optical signal reading starts, the capacitor setting tube is opened again to set the voltage on the sampling holding capacitor to be VrstStarting the selection transistor in the setting process, starting to charge the sampling holding capacitor until the selection transistor is turned off when the capacitor setting signal set is at a low level after the time t, and outputting an optical signal V through the buffer at the momentsignal；
(4) And an optical signal VsignalAnd a reset signal VresetPerforming subtraction, namely, eliminating reset noise through related double sampling operation to obtain light intensity information of the pixel point, and outputting a pixel value after processing;
(5) the time t of the invention is the charging time of the sampling holding capacitor, namely the sampling time, different output voltage swings are obtained by controlling the length of the time t, so that the conversion gain is flexibly adjusted, signals in a low-light-intensity environment can be effectively output in a high-gain mode, the influence of noise introduced by a reading circuit is reduced, imaging in the high-light-intensity environment can be realized in the low-gain mode, and the function of expanding in a dynamic range is realized.
Compared with a traditional 4T pixel structure, a common source amplifier structure is adopted in a source follower part in a pixel, so that the gain of an amplifier in the pixel is improved, and higher conversion gain can be realized; the invention can realize flexible adjustment of multi-conversion gain, and can image in a larger light intensity range, thereby having wider application range.
Drawings
FIG. 1 is a schematic circuit diagram of a pixel structure;
FIG. 2 is a timing diagram of the operation of the pixel structure of the present invention.
Detailed Description
The technical scheme of the invention is further clearly and completely described below by combining the attached drawings in the invention:
as shown in fig. 1, a schematic diagram of a variable conversion gain low noise pixel structure includes a Photodiode (PD), a charge transfer Transistor (TX), a reset transistor (RST), a signal Converter (CA), a selection transistor (SEL), a current source (I), a sample-and-hold capacitor (C), a capacitor SET transistor (SET), and a buffer (buffer); the inside of the dotted line frame is a pixel part circuit structure, and the outside of the dotted line frame is realized in a column-level circuit; VDD is power voltage, GND is 0 potential, FD node is signal conversion node, VrstA reference voltage that sets the sample-and-hold capacitor.
The charge transfer transistor and the capacitance setting transistor are NMOS transistors, and the reset transistor, the signal converter and the selection transistor are PMOS transistors;
wherein the cathode of the photodiode is connected to the source of the charge transfer transistor, and the anode of the photodiode is connected with the Ground (GND) and used for absorbing photons to generate photo-generated charges;
the source electrode of the charge transfer transistor is connected with the cathode of the photodiode, the grid electrode of the charge transfer transistor is connected with a charge transfer signal tx, and the drain electrode of the charge transfer transistor is connected with the FD node;
the source electrode of the reset transistor is connected with a power supply, the drain electrode of the reset transistor is connected with the FD node, and the grid electrode of the reset transistor is connected with a reset signal rst for resetting the PD before exposure and the FD node during reading;
the source electrode of the signal converter is connected to a power supply, the drain electrode of the signal converter is connected with the drain electrode of the selection transistor, the grid electrode of the signal converter is connected to the FD node, and a charge signal of the FD node is converted into a current signal to be output during the signal reading period;
the grid electrode of the selection transistor is connected with a selection signal, the drain electrode of the selection transistor is connected with the drain electrode of the signal converter, the source electrode of the selection transistor is connected with the column-level signal line, and when the selection transistor is started, the signal converter controlled by the FD node starts to charge the sampling holding capacitor;
the anode of the current source is connected to the column-level signal line, the cathode of the current source is grounded, and bias current is provided in the process of opening the selection transistor, so that the function of a common source amplifier is realized;
the upper polar plate of the sampling holding capacitor is connected with the column-level signal line, the lower polar plate is grounded, and the voltage of the upper polar plate is output through the buffer after charging;
the source electrode of the capacitor setting tube is connected to the upper polar plate of the sample-hold capacitor, and the drain electrode is connected to the voltage VrstThe grid is connected with an electric capacity set used for recovering the voltage of the upper electrode plate of the sampling holding capacitor to Vrst；
The input end of the buffer is connected to the upper polar plate of the sampling holding capacitor, and the output end of the buffer is used as the pixel output end for driving a subsequent circuit.
The length t of the starting time of the selective transistor determines the charging time under the condition that the capacitor setting tube is at a low level during working, the longer the charging time is, the larger the signal swing amplitude is, and therefore the time t is adjusted to realize flexible control of conversion gain.

Claims (2)

1. A variable conversion gain low noise pixel structure, characterized by: the circuit comprises a photodiode PD, a charge transfer transistor TX, a reset transistor RST, a signal converter CA, a selection transistor SEL, a current source I, a sampling holding capacitor C, a capacitor setting tube SET and a buffer;
the photoelectric diode, the charge transfer transistor, the reset transistor, the signal converter and the selection transistor are realized in a pixel part, the current source, the sampling holding capacitor, the capacitor setting tube and the buffer are realized in a column-level circuit part, the charge transfer transistor and the capacitor setting tube are NMOS, and the reset transistor, the signal converter and the selection transistor are PMOS;
the cathode of the photodiode is connected to the source of the charge transfer transistor, and the anode of the photodiode is connected with the ground GND;
the source electrode of the charge transfer transistor is connected with the cathode of the photodiode, the grid electrode of the charge transfer transistor is connected with a charge transfer signal tx, and the drain electrode of the charge transfer transistor is connected with the FD node;
the source electrode of the reset transistor is connected with a power supply, the drain electrode of the reset transistor is connected with the FD node, and the grid electrode of the reset transistor is connected with a reset signal rst;
the source electrode of the signal converter is connected to a power supply, the drain electrode of the signal converter is connected with the drain electrode of the selection transistor, and the grid electrode of the signal converter is connected to the FD node;
the grid electrode of the selection transistor is connected with a selection signal, the drain electrode of the selection transistor is connected with the drain electrode of the signal converter, and the source electrode of the selection transistor is connected with a column-level signal line;
the anode of the current source is connected to the column-level signal line, and the cathode of the current source is grounded;
the upper polar plate of the sampling holding capacitor is connected with the column-level signal line, and the lower polar plate is grounded;
the source electrode of the capacitor setting tube is connected to the upper polar plate of the sample-hold capacitor, and the drain electrode is connected to the voltage VrstThe grid is connected with a capacitance set signal set;
the input end of the buffer is connected to the upper polar plate of the sampling holding capacitor, and the output end of the buffer is used as the pixel output end.
2. A variable conversion gain low noise pixel structure according to claim 1, wherein: the working principle is as follows:
(1) when a pixel is exposed, a photodiode receives photons and converts the photons into charges for storage, after exposure is finished, a reset transistor is firstly started to reset an FD node, and after reset is finished, the reset transistor is closed;
(2) before the reading of the reset signal is started, a capacitor setting tube is opened to set the voltage on the sampling holding capacitor to be VrstAnd the selection transistor is turned on in the setting process, and the voltage on the sampling holding capacitor is subjected to VrstClamping and keeping unchanged, when the capacitor set signal set is at low level after the time t, starting to charge the sampling holding capacitor until the selection transistor is switched off, and outputting a reset signal V through the bufferreset；
(3) After the reset signal is read out, a charge transfer transistor is started, charges in the photodiode are transferred to an FD node, and optical signal reading is prepared; before the optical signal reading starts, the capacitor setting tube is opened again to set the voltage on the sampling holding capacitor to be VrstStarting the selection transistor in the setting process, starting to charge the sampling holding capacitor until the selection transistor is turned off when the capacitor setting signal set is at a low level after the time t, and outputting an optical signal V through the buffer at the momentsignal；
(4) To optical signal VsignalAnd a reset signal VresetPerforming subtraction, namely, eliminating reset noise through correlated double sampling operation to obtain the pixelProcessing the light intensity information of the point and outputting a pixel value;
(5) the conversion gain requirements under different conditions are different, the time t is the charging time of the sampling holding capacitor, namely the sampling time, different output voltage swing amplitudes are obtained by controlling the length of the time t, so that the conversion gain is flexibly adjusted, signals in a low-light-intensity environment can be effectively output in a high-gain mode, the influence of noise introduced by a reading circuit is reduced, imaging in the high-light-intensity environment can be realized in the low-gain mode, and the function of expansion in a dynamic range is realized.
CN201910752320.5A 2019-08-15 2019-08-15 Variable conversion gain low noise pixel structure Pending CN112399109A (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6975356B1 (en) * 1999-06-28 2005-12-13 Fujitsu Limited Solid-state imaging device with the elimination of thermal noise
US20080218620A1 (en) * 2007-03-08 2008-09-11 Imagerlabs Inc. Ultra low noise cmos imager
JP2011176520A (en) * 2010-02-24 2011-09-08 Nippon Hoso Kyokai <Nhk> Solid-state imaging device and method for driving the same
CN103139499A (en) * 2013-03-21 2013-06-05 北京思比科微电子技术股份有限公司 Imaging sensor active pixel and imaging sensor with variable conversion gain
CN103384999A (en) * 2011-01-02 2013-11-06 匹克希姆公司 Conversion gain modulation using charge sharing pixel
CN104135633A (en) * 2014-08-25 2014-11-05 北京思比科微电子技术股份有限公司 Image sensor pixel with changeable conversion gain and working method thereof
CN108470742A (en) * 2018-03-22 2018-08-31 上海晔芯电子科技有限公司 Hdr image sensor pixel structure and imaging system
CN109474795A (en) * 2018-10-31 2019-03-15 天津大学 A kind of low-noise pixel circuit structure based on transconductance cell

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6975356B1 (en) * 1999-06-28 2005-12-13 Fujitsu Limited Solid-state imaging device with the elimination of thermal noise
US20080218620A1 (en) * 2007-03-08 2008-09-11 Imagerlabs Inc. Ultra low noise cmos imager
JP2011176520A (en) * 2010-02-24 2011-09-08 Nippon Hoso Kyokai <Nhk> Solid-state imaging device and method for driving the same
CN103384999A (en) * 2011-01-02 2013-11-06 匹克希姆公司 Conversion gain modulation using charge sharing pixel
CN103139499A (en) * 2013-03-21 2013-06-05 北京思比科微电子技术股份有限公司 Imaging sensor active pixel and imaging sensor with variable conversion gain
CN104135633A (en) * 2014-08-25 2014-11-05 北京思比科微电子技术股份有限公司 Image sensor pixel with changeable conversion gain and working method thereof
CN108470742A (en) * 2018-03-22 2018-08-31 上海晔芯电子科技有限公司 Hdr image sensor pixel structure and imaging system
CN109474795A (en) * 2018-10-31 2019-03-15 天津大学 A kind of low-noise pixel circuit structure based on transconductance cell

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Application publication date: 20210223