CN115914872B - CTIA readout circuit with high dynamic range for implementing CDS in pixel - Google Patents
CTIA readout circuit with high dynamic range for implementing CDS in pixel Download PDFInfo
- Publication number
- CN115914872B CN115914872B CN202211599385.9A CN202211599385A CN115914872B CN 115914872 B CN115914872 B CN 115914872B CN 202211599385 A CN202211599385 A CN 202211599385A CN 115914872 B CN115914872 B CN 115914872B
- Authority
- CN
- China
- Prior art keywords
- switch
- circuit
- capacitor
- rst
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 66
- 230000010354 integration Effects 0.000 claims abstract description 26
- 238000005070 sampling Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 10
- 101001092905 Haloferax volcanii (strain ATCC 29605 / DSM 3757 / JCM 8879 / NBRC 14742 / NCIMB 2012 / VKM B-1768 / DS2) Small archaeal modifier protein 3 Proteins 0.000 claims description 8
- 101001092912 Haloferax volcanii (strain ATCC 29605 / DSM 3757 / JCM 8879 / NBRC 14742 / NCIMB 2012 / VKM B-1768 / DS2) Small archaeal modifier protein 1 Proteins 0.000 claims description 6
- 101000801088 Homo sapiens Transmembrane protein 201 Proteins 0.000 claims description 6
- 102100033708 Transmembrane protein 201 Human genes 0.000 claims description 6
- 101710176973 Small archaeal modifier protein 2 Proteins 0.000 claims description 4
- 230000002452 interceptive effect Effects 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 10
- 230000001276 controlling effect Effects 0.000 description 5
- 230000002596 correlated effect Effects 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
The invention provides a CTIA readout circuit with a high dynamic range for realizing CDS in a pixel, and belongs to the technical field of image sensor readout circuits. The readout circuit provided by the invention can be independently operated, and can select a proper integration capacitor according to different light source intensities and combining with a self-selection capacitor technology, so that the dynamic range of the readout circuit is enlarged. When the optical signal is weak, a small capacitor is used as an integrating capacitor, and an unused large capacitor is used as a bandwidth limiting capacitor, so that circuit noise can be effectively reduced. When the optical signal is strong, the large capacitance and the small capacitance are connected in parallel to be used as an integrating capacitance, so that the range of the detected photocurrent can be enlarged. In order to be compatible with two working modes of ITR and IWR, the invention adds a path of sampling hold circuit in the traditional CDS structure, which can make the period of each frame approximately equal to the time of signal reading, and the reading speed is greatly accelerated.
Description
Technical Field
The invention relates to the technical field of image sensor readout circuits, in particular to a CTIA readout circuit structure design with high dynamic range, which can realize CDS in pixels.
Background
An infrared focal plane array (Infrared Focal Plane Array, IRFPA) consists essentially of two parts, a two-dimensional detector array and readout circuitry, with the detector array being placed at the focal plane of the imaging optics to detect infrared radiation signals. An infrared focal plane array is essentially a sensor with pre-signal processing, where the readout circuitry is its pre-signal processing circuitry. The readout circuit is a highly integrated circuit integrating various functions in the focal plane into a semiconductor chip, and is an important component of an infrared focal plane device.
The main function of the reading circuit is that the infrared detector receives the optical signal and then converts the optical signal into an electric signal, and then the electric signal is subjected to integral amplification, sampling and holding, and the data is transmitted to an output end and is subjected to on-chip digital processing after the signal is processed through an output buffering and multiplexing system. Among the various types of CMOS readout circuits, capacitive feedback transimpedance amplifier (CTIA) is the main subject of research today for readout circuits due to its high injection efficiency, stable detector bias, good linearity, etc.
The reset noise can be removed by using a correlated double sampling (Correlated Double Sample, CDS) structure in the readout circuit. The CDS actually performs two sample-and-hold operations during the reset and integration processes, respectively, and then performs a difference on the results of the two outputs to obtain an actual effective amplitude of the signal level, thereby eliminating the interference of reset noise in the circuit. The conventional CDS structure has only two holding circuits, which can sample and hold the reset signal and the integral signal respectively, but has the disadvantage that the two working modes of read-after-integration (Integration then read, ITR) and read-while-integration (Integration then read, IWR) cannot be compatible, i.e., the existing structure cannot realize the function of simultaneously performing the two processes of integration and read-out.
The signal current of the short-wave infrared (SWIR) detector is greatly affected by the light source, which causes a great gap between the signal current at night and the signal current at daytime, the signal current at night is much smaller than that at daytime, and the problem of narrow dynamic range easily occurs by using the same integrating capacitor. Thus, the conventional SWIR readout circuit uses two types of integration capacitances, i.e., a large capacitance for daytime and a small capacitance for nighttime, which are globally controlled by external digital processing for all pixels. However, globally controlling the selection of integration capacitance presents a very troublesome problem in that when small capacitance integration is used late at night, the sudden high intensity light source may saturate some parts, making the imaging less effective.
Disclosure of Invention
In order to solve the technical problems that the prior CMOS image sensor is required to design a high-performance readout circuit in a limited area and realize CDS and a wide dynamic range, the invention provides a CTIA readout circuit with a high dynamic range, which can realize CDS in pixels. The readout circuit adopts a self-selection capacitance technology and an improved CDS circuit structure, so that the range of the detected photocurrent is enlarged, and the two working modes of ITR and IWR are compatible.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a CTIA readout circuit with high dynamic range for realizing CDS in pixel comprises CTIA circuit, CDS circuit, and circuit clear switch S CLR A transistor SF, and a row select transistor SEL.
The CTIA circuit comprises a detector PPD, an operational amplifier AMP and a reset switch S rst Small capacitance C used as integral lg Large capacitance C, optionally as limiting bandwidth or integral hg Self-selection gain logic circuit, integration capacitance selection switch S C2 And S is C3 Pre-integral control switch S C1 、S C4 And S is C5 。
Wherein, the anode of the detector PPD is grounded, and the cathode is connected with the switch S C1 Is provided for the first terminal of (a). Switch S C1 Is connected with the inverting input terminal of the operational amplifier AMP and the capacitor C lg Upper pole plate of (S) switch (S) C2 And a reset switch S rst Is provided for the first terminal of (a). Capacitor C lg Lower polar plate connecting switch S C4 Is a first terminal of (a) and a switch S C5 Is connected to the first terminal of the first circuit board; switch S C4 Is connected to the reference voltage V ref . Switch S C2 Is connected to the capacitor C through the second terminal hg Upper plate and switch S of (2) C3 Is connected to the first terminal of the first circuit board; switch S C3 Is grounded. The non-inverting input terminal of the operational amplifier AMP is connected with the reference voltage V com The method comprises the steps of carrying out a first treatment on the surface of the The output end of the operational amplifier AMP is connected with the input end of the self-selection gain logic circuit and the switch S C5 Second terminal of (C) capacitor hg Lower pole plate of (C) and reset switch S rst And is connected to the CDS circuit as an output of the CTIA circuit.
Further, reset switch S rst Controlled by an external input signal RST; switch S C1 And S is C5 Controlled by an external input signal INT; switch S C4 By external input signalsControlling; switch S C2 And S is C3 A pair of opposite signals HG and +.>And (5) controlling.
The CDS circuit comprises three sampling switches S H1 、S H2 And S is H3 Three sample-and-hold capacitors C 1 、C 2 And C 3 And three readout switches S R1 、S R2 And S is R3 . Wherein the output end of the CTIA circuit is connected with a switch S H1 Is a first terminal, switch S H2 Is a first terminal of (a) and a switch S H3 Is provided for the first terminal of (a). Switch S H3 Is connected to the capacitor C through the second terminal 3 Upper plate and switch S of (2) R3 Is connected to the first terminal of the first circuit board; capacitor C 3 The lower electrode plate of the capacitor is grounded. Switch S H2 Is connected to the capacitor C through the second terminal 2 Upper plate and switch S of (2) R2 Is connected to the first terminal of the first circuit board; capacitor C 2 The lower electrode plate of the capacitor is grounded. Switch S H1 Is connected to the capacitor C through the second terminal 1 Upper plate and switch S of (2) R1 Is connected to the first terminal of the first circuit board; capacitor C 1 The lower electrode plate of the capacitor is grounded. Switch S R1 Switch S R2 And switch S R3 Is connected together and serves as an output of the CDS circuit.
Further, switch S H1 、S H2 And S is H3 Switch S controlled by external input signals SAMP1, SAMP2 and SAMP3, respectively R1 、S R2 And S is R3 Controlled by external input signals READ1, READ2 and READ3, respectively。
The circuit zero clearing switch S CLR The first terminal is connected to the reference voltage Vcom, and the second terminal is connected to the gate of the transistor SF. The drain of the transistor SF is connected to the power supply voltage VDD, and the source is connected to the drain of the row selection transistor SEL. The source of the row select transistor SEL serves as an output.
Further, switch S CLR Controlled by an external input signal CLR. The gate of the ROW select transistor SEL is controlled by an external input signal row_sel.
The invention has the beneficial effects that:
1) The readout circuit structure provided by the invention can be independently operated, and can select a proper integration capacitor according to different light source intensities and combining with a self-selection capacitor technology, so that the dynamic range of the readout circuit structure is enlarged. When the optical signal is weak, a small capacitor is used as an integrating capacitor, and an unused large capacitor is used as a bandwidth limiting capacitor, so that circuit noise can be effectively reduced. When the optical signal is strong, the large capacitance and the small capacitance are connected in parallel to be used as an integrating capacitance, so that the range of the detected photocurrent can be enlarged.
2) In order to be compatible with two working modes of ITR and IWR, the invention adds a path of sampling hold circuit in the traditional CDS structure, which can make the period of each frame approximately equal to the time of signal reading, and the reading speed is greatly accelerated.
Drawings
Fig. 1 is a schematic diagram of a CTIA readout circuit architecture with high dynamic range for implementing in-pixel CDS according to the present invention;
FIG. 2 is a schematic block diagram of the operational flow of the CTIA circuit provided by the invention;
FIG. 3 is a schematic diagram of an equivalent circuit of a CTIA pre-integration stage provided by the present invention;
FIG. 4 is a schematic diagram of an equivalent circuit of a CTIA comparison stage according to the present invention;
FIG. 5 is a schematic diagram of an equivalent circuit of a CTIA bandwidth limiting mode provided by the present invention;
FIG. 6 is a schematic diagram of the equivalent structure of the CTIA large capacitance integration mode provided by the invention;
FIG. 7 is a timing diagram of the operation of the CTIA bandwidth limiting mode provided by the present invention;
FIG. 8 is a timing diagram of the operation of the CTIA large capacitance integration mode provided by the present invention;
fig. 9 is a timing diagram of operation of the CDS circuit implementing ITR provided by the present invention;
fig. 10 is a timing diagram of the operation of the CDS circuit implementing IWR according to the present invention.
Detailed Description
In order to make the technical problems solved by the invention, the technical scheme adopted and the technical effects achieved clearer, the invention is further described in detail below with reference to the accompanying drawings and the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the matters related to the present invention are shown in the accompanying drawings.
As shown in FIG. 1, an embodiment of the present invention provides a CTIA readout circuit with high dynamic range for implementing CDS in a pixel, which comprises a CTIA circuit, a CDS circuit, and a circuit zero clearing switch S CLR A transistor SF, and a row select transistor SEL.
The working process of the self-selection capacitance integration is divided into the following three stages, as shown in a flow chart of fig. 2:
the first stage is a pre-integration stage in which the external signal is as shown in FIG. 7, the external input signal RST andINT is low, INT is high, the output signal HG of the self-selected gain logic is low, < ->Is high. Switch S C1 、S C5 Closing, switch S rst 、S C2 、S C3 And S is C4 The equivalent circuit is shown in fig. 3. The circuit can pre-integrate the photocurrent generated by the detector PPD into the capacitor C lg And obtaining a pre-integral voltage delta V at two ends.
The second stage is comparison ofStage, in which external signals are as shown in fig. 7, external input signals RST and INT are low,is high, switch S C4 Closing, switch S rst 、S C1 、S C2 、S C3 And S is C5 The equivalent circuit is broken, as shown in FIG. 4, and the operational amplifier AMP functions as a comparator, with the voltage at the inverting input terminal of the operational amplifier AMP being V ref Subtracting the pre-integrated voltage DeltaV, which is equal to the reference voltage V at the positive input com Comparing, after the processing of the self-selection gain logic circuit, the output signals HG and +.>
The third stage is the main integration stage, based on HG andselecting a corresponding operation mode, integrating the signal current:
if V com <V ref Δv, the circuit enters a bandwidth limited mode, the timing of which is shown in fig. 7. External input signal RSTINT is low, INT is high, the output signal HG of the self-selected gain logic is low, < ->Is high. Switch S C1 、S C3 And S is C5 Closing, switch S rst 、S C2 And S is C4 The equivalent circuit is shown in fig. 5. Capacitor C hg As a band-limited capacitor access circuit, the actual integral capacitor in the circuit is a capacitor C lg ；
If V com >V ref Δv, the circuit enters a capacitive integration mode, the timing of which is shown in fig. 8. External input signal RSTINT is low, INT is high, the output signal HG of the self-selected gain logic is high, < ->Is low. Switch S C1 、S C2 And S is C5 Closing, switch S rst 、S C3 And S is C4 The equivalent circuit is shown in fig. 6. Capacitor C hg To be connected to an integrating circuit, the integral integrating capacitance becomes (C hg +C lg )。
Further, the operational amplifier AMP functions not only as an amplifier in the integrating stage but also as a comparator in the comparing stage, so that there is no need to add an additional operational amplifier to the comparator in the CTIA circuit. The two steps of common operational amplifier can reduce the area of a unit circuit.
Furthermore, the self-selection capacitance technology can independently operate on each pixel according to the magnitude of an input current signal, and the function of improving the dynamic range of the pixel is realized.
The CDS circuit comprises three sampling switches S H1 、S H2 And S is H3 Three sample-and-hold capacitors C 1 、C 2 And C 3 And three readout switches S R1 、S R2 And S is R3 . Wherein the switch S H1 Capacitance C 1 And switch S R1 Forming a first path of sampling readout circuit; switch S H2 Capacitance C 2 And switch S R2 Forming a second path of sampling readout circuit; switch S H3 Capacitance C 3 And switch S R3 And forming a third sampling read-out circuit.
The timing of implementing ITR by the CDS circuit is shown in FIG. 9, in which RST is high at the beginning of the N-th frame, and CLR controls switch S CLR And the gate of the transistor SF is closed to eliminate the charges stored in the gate of the transistor SF, so that the subsequent read signal is prevented from being interfered. After a period of time, S CLR And (5) disconnecting. Thereafter SAMP1 switch control S H1 Closing, the output V of the CTIA circuit at the moment out Stored in capacitor C 1 And (3) upper part. After a period of time when RST is low, SAMP3 switch controls S H3 Closing, the output V of the CTIA circuit at the moment out Stored in capacitor C 3 And (3) upper part. Subsequent READ1 controls switch S R1 The ROW_SEL signal controls the transistor SEL to be on, and the reset voltage of pix_out is obtained. Control switch S following READ3 R3 The ROW _ SEL signal controls the transistor SEL to turn on, resulting in an integrated voltage of pix _ out.
Further, in the above process, the switches not mentioned by the CDS circuit are all in the off state, and the operation timings of the frames are the same. When the ITR reading mode is realized, the first sampling reading circuit is respectively responsible for sampling and reading the reset signal in each frame, and the third sampling reading circuit is responsible for sampling and holding the integrated signal in each frame. The integration time is recorded as RST low level to switch S H3 The period of closure.
The CDS circuit realizes IWR with timing shown in FIG. 10, RST is high level at the beginning of even frame 2M frame, while CLR controls switch S CLR Closing. After a period of time, S CLR And (5) disconnecting. Thereafter SAMP2 switch control S H2 Closing, the output V of the CTIA circuit at the moment out Stored in capacitor C 2 And (3) upper part. After a period of time when RST is low, READ1 controls switch S R1 And closing, and simultaneously controlling a transistor SEL to be conducted by a ROW_SEL signal to obtain the reset voltage of the (2M-1) th frame of the pix_out odd frame. Subsequent READ3 control switch S R3 And closing, and simultaneously controlling a transistor SEL to be conducted by a ROW_SEL signal to obtain the integral voltage of the (2M-1) th frame of the pix_out odd frame. When RST is about to go high, SAMP3 switch controls S H3 Closing, outputting V of even frame of CTIA circuit out Stored in capacitor C 3 And (3) upper part. Correspondingly, at the beginning of the (2M+1) th frame of the odd number frames, RST is high, while CLR controls switch S CLR Closing. After a period of time, S CLR And (5) disconnecting. Thereafter SAMP1 switch control S H1 Closing, the output V of the CTIA circuit at the moment out Stored in capacitor C 1 And (3) upper part. After a period of time when RST is low, READ2 controls switch S R2 Closing while ROW_SELThe signal control transistor SEL is turned on to obtain the reset voltage of the 2M frame of the pix_out even frame. Subsequent READ3 control switch S R3 And closing, and simultaneously controlling a transistor SEL to be conducted by a ROW_SEL signal to obtain the integration voltage of the 2M frame of the pix_out even frame. When RST is about to go high, SAMP3 switch controls S H3 Closing, outputting the odd frame output V of CTIA circuit out Stored in capacitor C 3 And (3) upper part.
Furthermore, when the IWR reading mode is realized, the first path and the second path of sampling and reading circuits are respectively responsible for sampling and reading reset signals in odd frames and even frames; the third sampling readout circuit is responsible for sampling and readout of the integrated signal of each frame. In each frame period, the reset signal and the integrated signal of the previous frame are output to the column bus through the transistor SF in sequence, and the operation of the subsequent circuit is performed. The integration time is recorded as RST low level to switch S H3 The period of closure.
The circuit zero clearing switch S CLR One end is connected with a reference voltage V com The other end of the transistor SF is connected with the grid electrode of the transistor SF, so that the effect of zero clearing of charges is achieved, partial charges stored in the input node of the transistor SF can be eliminated, and the charges stored in the grid electrode of the transistor SF are prevented from interfering reset signals read later.
The drain electrode of the transistor SF is connected with a power supply voltage VDD; the source of the transistor SF is connected to the drain of the row selection transistor SEL. The transistor SF functions as a buffer for driving the column bus line of the subsequent stage.
The source of the row select transistor SEL is connected to the readout circuit, and controls the pixels to output signals to the column bus, and its on and off are controlled by the digital timing generation circuit.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments is modified or some or all of the technical features are replaced equivalently, so that the essence of the corresponding technical scheme does not deviate from the scope of the technical scheme of the embodiments of the present invention.
Claims (5)
1. A CTIA readout circuit with high dynamic range for realizing CDS in pixel is characterized in that the readout circuit comprises a CTIA circuit, a CDS circuit and a circuit zero clearing switch S CLR A transistor SF and a row selection transistor SEL;
the CTIA circuit comprises a detector PPD, an operational amplifier AMP and a reset switch S rst Small capacitance C used as integral lg Large capacitance C, optionally as limiting bandwidth or integral hg Self-selection gain logic circuit, integration capacitance selection switch S C2 And S is C3 Pre-integral control switch S C1 、S C4 And S is C5 The method comprises the steps of carrying out a first treatment on the surface of the Wherein, the anode of the detector PPD is grounded, and the cathode is connected with the switch S C1 Is connected to the first terminal of the first circuit board; switch S C1 Is connected with the inverting input terminal of the operational amplifier AMP and the capacitor C lg Upper pole plate of (S) switch (S) C2 And a reset switch S rst Is connected to the first terminal of the first circuit board; capacitor C lg Lower polar plate connecting switch S C4 Is a first terminal of (a) and a switch S C5 Is connected to the first terminal of the first circuit board; switch S C4 Is connected to the reference voltage V ref The method comprises the steps of carrying out a first treatment on the surface of the Switch S C2 Is connected to the capacitor C through the second terminal hg Upper plate and switch S of (2) C3 Is connected to the first terminal of the first circuit board; switch S C3 Is grounded; the non-inverting input terminal of the operational amplifier AMP is connected with the reference voltage V com The method comprises the steps of carrying out a first treatment on the surface of the The output end of the operational amplifier AMP is connected with the input end of the self-selection gain logic circuit and the switch S C5 Second terminal of (C) capacitor hg Lower pole plate of (C) and reset switch S rst And is connected to the CDS circuit as an output end of the CTIA circuit;
the CDS circuit comprises three sampling switches S H1 、S H2 And S is H3 Three sample-and-hold capacitors C 1 、C 2 And C 3 And three readout switches S R1 、S R2 And S is R3 The method comprises the steps of carrying out a first treatment on the surface of the Wherein the output end of the CTIA circuit is connected with a switch S H1 Is a first terminal, switch S H2 Is a first terminal of (a) and a switch S H3 Is connected to the first terminal of the first circuit board; switch S H3 Is connected to the capacitor C through the second terminal 3 Upper plate and switch S of (2) R3 Is connected to the first terminal of the first circuit board; capacitor C 3 The lower polar plate of the capacitor is grounded; switch S H2 Is connected to the capacitor C through the second terminal 2 Upper plate and switch S of (2) R2 Is connected to the first terminal of the first circuit board; capacitor C 2 The lower polar plate of the capacitor is grounded; switch S H1 Is connected to the capacitor C through the second terminal 1 Upper plate and switch S of (2) R1 Is connected to the first terminal of the first circuit board; capacitor C 1 The lower polar plate of the capacitor is grounded; switch S R1 Switch S R2 And switch S R3 Is connected together and serves as an output terminal of the CDS circuit;
the circuit zero clearing switch S CLR A first terminal connected to the reference voltage Vcom, and a second terminal connected to the gate of the transistor SF; the drain electrode of the transistor SF is connected with the power supply voltage VDD, and the source electrode is connected with the drain electrode of the row selection transistor SEL; a source of the row select transistor SEL as an output;
in the CTIA circuit, a reset switch S rst Controlled by an external input signal RST; switch S C1 And S is C5 Controlled by an external input signal INT; switch S C4 By external input signalsControlling; switch S C2 And S is C3 A pair of opposite signals HG and +.>Controlling;
the working process of the CTIA circuit for realizing the self-selection capacitance integration comprises three stages:
the first stage is a pre-integration stage, and the external input signals RST andINT is low, INT is high, the output signal HG of the self-selected gain logic is low, < ->Is high; switch S C1 、S C5 Closing, switch S rst 、S C2 、S C3 And S is C4 Cut-off, pre-integrate the photocurrent generated by the detector PPD into the capacitor C lg Two ends obtain pre-integral voltage delta V;
the second phase is a comparison phase, the external input signals RST and INT are low,is high, switch S C4 Closing, switch S rst 、S C1 、S C2 、S C3 And S is C5 The open, operational amplifier AMP functions as a comparator, the operational amplifier AMP inverting input voltage V ref Subtracting the pre-integrated voltage DeltaV, which is equal to the reference voltage V at the positive input com Comparing, after the processing of the self-selection gain logic circuit, the output signals HG and +.>
The third stage is the main integration stage, based on HG andselecting a corresponding operation mode, integrating the signal current:
if V com <V ref DeltaV, the circuit enters a bandwidth limited mode, external input signal RST andINT is low, INT is high, the output signal HG of the self-selected gain logic is low, < ->Is high; switch S C1 、S C3 And S is C5 Closing, switch S rst 、S C2 And S is C4 Off, capacitor C hg As a band-limited capacitor access circuit, the actual integral capacitor in the circuit is a capacitor C lg ；
If V com >V ref DeltaV, the circuit enters a capacitive integration mode, external input signal RST andINT is low, INT is high, the output signal HG of the self-selected gain logic is high, < ->Is low; switch S C1 、S C2 And S is C5 Closing, switch S rst 、S C3 And S is C4 Off, capacitor C hg To be connected to an integrating circuit, the integral integrating capacitance becomes (C hg +C lg )。
2. A CTIA readout circuit with high dynamic range implementing in-pixel CDS according to claim 1, characterized in that in the CDS circuit, switch S H1 、S H2 And S is H3 Switch S controlled by external input signals SAMP1, SAMP2 and SAMP3, respectively R1 、S R2 And S is R3 Controlled by external input signals READ1, READ2 and READ3, respectively.
3. A CTIA readout circuit with high dynamic range implementing in-pixel CDS according to claim 2, characterized in that the switch S CLR Controlled by an external input signal CLR; the gate of the ROW select transistor SEL is controlled by an external input signal row_sel.
4. A CTIA readout circuit with high dynamic range for implementing in-pixel CDS according to claim 1, wherein the CDS circuit implements ITR operation mode as follows:
at the beginning of the nth frame, RST is high, while CLR controls switch S CLR Closing, namely eliminating charges stored in the grid electrode of the transistor SF and preventing the charges from interfering a signal read subsequently; after a period of time, S CLR Disconnecting; thereafter SAMP1 switch control S H1 Closing, the output V of the CTIA circuit at the moment out Stored in capacitor C 1 Applying; after a period of time when RST is low, SAMP3 switch controls S H3 Closing, the output V of the CTIA circuit at the moment out Stored in capacitor C 3 Applying; subsequent READ1 controls switch S R1 Closing, and simultaneously controlling a transistor SEL to be conducted by a ROW_SEL signal to obtain the reset voltage of pix_out; control switch S following READ3 R3 The ROW _ SEL signal controls the transistor SEL to turn on, resulting in an integrated voltage of pix _ out.
5. A CTIA readout circuit with high dynamic range for implementing in-pixel CDS according to claim 1, wherein the CDS circuit implements an IWR operation mode as follows:
at the beginning of the even frame 2M frame, RST is high, while CLR controls switch S CLR Closing; after a period of time, S CLR Disconnecting; thereafter SAMP2 switch control S H2 Closing, the output V of the CTIA circuit at the moment out Stored in capacitor C 2 Applying; after a period of time when RST is low, READ1 controls switch S R1 Closing, and simultaneously controlling a transistor SEL to be conducted by a ROW_SEL signal to obtain the reset voltage of the (2M-1) th frame of the pix_out odd frame; subsequent READ3 control switch S R3 Closing, and simultaneously controlling a transistor SEL to be conducted by a ROW_SEL signal to obtain the integral voltage of the (2M-1) th frame of the pix_out odd frame; when RST is about to go high, SAMP3 switch controls S H3 Closing, outputting V of even frame of CTIA circuit out Stored in capacitor C 3 Applying;
correspondingly, at the beginning of the (2M+1) th frame of the odd number frames, RST is high, while CLR controls switch S CLR Closing; after a period of time, S CLR Disconnecting; thereafter SAMP1 switch control S H1 Closing, the output V of the CTIA circuit at the moment out Stored in capacitor C 1 Applying; after a period of time when RST is low, READ2 controlSwitch S R2 Closing, and simultaneously controlling a transistor SEL to be conducted by a ROW_SEL signal to obtain the reset voltage of the 2M frame of the pix_out even frame; subsequent READ3 control switch S R3 Closing, and simultaneously controlling a transistor SEL to be conducted by a ROW_SEL signal to obtain the integration voltage of the 2M frame of the pix_out even frame; when RST is about to go high, SAMP3 switch controls S H3 Closing, outputting the odd frame output V of CTIA circuit out Stored in capacitor C 3 And (3) upper part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211599385.9A CN115914872B (en) | 2022-12-12 | 2022-12-12 | CTIA readout circuit with high dynamic range for implementing CDS in pixel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211599385.9A CN115914872B (en) | 2022-12-12 | 2022-12-12 | CTIA readout circuit with high dynamic range for implementing CDS in pixel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115914872A CN115914872A (en) | 2023-04-04 |
| CN115914872B true CN115914872B (en) | 2024-03-22 |
Family
ID=86480425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211599385.9A Active CN115914872B (en) | 2022-12-12 | 2022-12-12 | CTIA readout circuit with high dynamic range for implementing CDS in pixel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115914872B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104266764A (en) * | 2014-09-30 | 2015-01-07 | 天津工业大学 | Reading circuit for infrared planar array detector |
| CN108307133A (en) * | 2018-03-01 | 2018-07-20 | 江苏芯力特电子科技有限公司 | A kind of adaptive CT IA reading circuits for image detector |
| CN109540290A (en) * | 2019-01-10 | 2019-03-29 | 中国科学院上海技术物理研究所 | One kind four samples low noise cmos detector reading circuit |
-
2022
- 2022-12-12 CN CN202211599385.9A patent/CN115914872B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104266764A (en) * | 2014-09-30 | 2015-01-07 | 天津工业大学 | Reading circuit for infrared planar array detector |
| CN108307133A (en) * | 2018-03-01 | 2018-07-20 | 江苏芯力特电子科技有限公司 | A kind of adaptive CT IA reading circuits for image detector |
| CN109540290A (en) * | 2019-01-10 | 2019-03-29 | 中国科学院上海技术物理研究所 | One kind four samples low noise cmos detector reading circuit |
Non-Patent Citations (1)
| Title |
|---|
| A 20MHz CTIA ROIC for InGaAs Focal Plane Array;yuchun chang;《IEEE》;20180111;第267-270页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115914872A (en) | 2023-04-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10250826B2 (en) | Image sensors having extended dynamic range | |
| CN106470322B (en) | Readout circuit for reducing column fixed pattern noise of image sensor | |
| US7616146B2 (en) | A/D conversion circuit, control method thereof, solid-state imaging device, and imaging apparatus | |
| KR100660193B1 (en) | Self compensating correlated double sampling circuit | |
| KR100834424B1 (en) | Image sensor | |
| US8269873B2 (en) | Solid-state imaging device and load current source circuit | |
| US6917027B2 (en) | Method and apparatus for reducing kTC noise in an active pixel sensor (APS) device | |
| JP2016201649A (en) | Imaging apparatus, imaging system, and driving method for imaging apparatus | |
| KR20080095175A (en) | Solid-state image pickup device, a method of driving the same, a signal processing method for the same, and image pickup apparatus | |
| JP2016535548A (en) | Pixel circuit having photodiode biased with constant voltage and associated imaging method | |
| JP2016015633A (en) | Imaging device and imaging system | |
| CN112399113B (en) | High-speed global exposure pixel structure for realizing intra-pixel correlated double sampling | |
| CN115914872B (en) | CTIA readout circuit with high dynamic range for implementing CDS in pixel | |
| CN112399099B (en) | Charge domain sampling low-noise pixel structure | |
| TWI683577B (en) | Image lag mitigation for buffered direct injection readout with current mirror | |
| US20170078598A1 (en) | Imaging apparatus and imaging method thereof using correlated double sampling | |
| JP5106596B2 (en) | Imaging device | |
| WO2023152035A1 (en) | Image sensor, optoelectronic device including the image sensor and method for operating the image sensor | |
| JP2000022118A (en) | Image-pickup device | |
| WO2020196034A1 (en) | Imaging processing circuit, imaging system, imaging processing method, and program | |
| JP4708583B2 (en) | Imaging device | |
| CN111263088A (en) | High-speed sampling circuit for 8T pixel and control method thereof | |
| US11611813B2 (en) | Method of removing fixed pattern noise | |
| TWI842373B (en) | Imaging device, optoelectronic device and method for operating an imaging device | |
| US11107847B2 (en) | Pixel and imaging array with reduced dark current adapted to low light imaging |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |