CN109473427B

CN109473427B - High voltage device and method for manufacturing the same

Info

Publication number: CN109473427B
Application number: CN201710805808.0A
Authority: CN
Inventors: 黄宗义
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2017-09-08
Filing date: 2017-09-08
Publication date: 2020-06-30
Anticipated expiration: 2037-09-08
Also published as: CN109473427A

Abstract

The invention provides a high-voltage element and a manufacturing method thereof. The high voltage device is formed on a semiconductor substrate, and comprises: the first deep well region, the transverse lightly doped region, the high-voltage well region, the insulation region, the body region, the grid electrode, the source electrode, the drain electrode and the first isolation well region. The first deep well region and the first isolation well region electrically isolate the high voltage device from the adjacent devices under the upper surface of the semiconductor substrate. The transverse lightly doped region is longitudinally arranged between the first deep well region and the high-voltage well region, and is vertically adjacent to the first deep well region and the high-voltage well region. The transverse lightly doped region is used for reducing the capacitance inside the high-voltage element and improving the transient response when the high-voltage element is operated.

Description

High voltage device and method for manufacturing the same

Technical Field

The present invention relates to a high voltage device and a method for manufacturing the same, and more particularly, to a high voltage device with reduced internal capacitance to improve transient response and a method for manufacturing the same.

Background

Fig. 1A and 1B respectively show a top view and a cross-sectional view of a double-Diffused Metal Oxide Semiconductor (DMOS) device 100 of the prior art; wherein FIG. 1B shows a cross-sectional view of the cross-sectional line AA' of FIG. 1A. DMOS device 100 is a high voltage device, and as shown in fig. 1A and 1B, an N-type hvw region 102 is formed in a semiconductor substrate 101; and an insulating region 103 is formed to define an operation region 103a, wherein the insulating region 103 is, for example, a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) structure as illustrated in fig. 1B. In the operation region 103a, a field oxide region 104, a body region 105, a body electrode 105a, a gate 106, a source 107, and a drain 108 are formed. Wherein a portion of the gate 106 is located on the field oxide region 104. The N-type hvw region 102 may be formed by implanting N-type impurities into a defined region in the form of accelerated ions in an ion implantation process. The source 107 and the drain 108 are formed by defining regions through photolithography (including self-aligned process), and implanting N-type impurities into the defined regions in the form of accelerated ions through ion implantation process. The body region 105 and the body electrode 105a are formed by defining regions by photolithography process steps (including self-aligned process steps) and implanting P-type impurities into the defined regions in the form of accelerated ions by ion implantation process steps, respectively. The source 107 and the drain 108 are respectively located under two outer sides of the gate 106, and a portion of the N-hvw region 102 separates the source 107 and the drain 108 and serves as a drift region. In the DMOS device 100, when the P-type body region 105 and the N-type hvw region 102 are reverse biased, or/and when the N-type hvw region 102 and the P-type semiconductor substrate 101 are reverse biased, the junction of the regions will generate a depletion region due to the reverse bias, and the internal capacitance will limit the switching speed when the DMOS device 100 switches between on and off operation, and the larger the capacitance, the slower the switching speed, and therefore the transient response will be limited, thus limiting the application range of the DMOS device 100. DMOS elements are high voltage elements, wherein a high voltage element means that a voltage applied to the drain 15 is higher than 5V during a normal operation; in general, a drift region is disposed between the drain and the gate of the high voltage device to separate the drain from the gate, and the length of the drift region in the lateral direction (as indicated by the solid arrow) is adjusted according to the operation voltage applied during normal operation.

In view of the above, the present invention provides a high voltage device and a method for manufacturing the same, which can improve the transient response and increase the application range of the device.

Disclosure of Invention

The present invention is directed to overcome the disadvantages and drawbacks of the prior art, and to provide a high voltage device and a method for manufacturing the same, which can improve the transient response and increase the application range of the device.

In order to achieve the above object, in one aspect, the present invention provides a high voltage device formed on a semiconductor substrate, wherein the semiconductor substrate has an upper surface and a lower surface opposite to each other in a longitudinal direction, the high voltage device comprising: a first deep well region of a first conductivity type formed in the semiconductor substrate; a transverse lightly doped region covering and connected to the first deep well region; a high voltage well region of a second conductivity type formed in the semiconductor substrate and in the longitudinal direction, the high voltage well region being located below and contacting the upper surface, and the high voltage well region covering and connecting to the lateral lightly doped region, wherein a portion of the high voltage well region is used as a drift region; an insulating region formed on the upper surface for defining an operation region; a body region of the first conductivity type formed in the semiconductor substrate and located in the operating region, and located below and contacting the upper surface in the longitudinal direction, wherein a portion of the body region is used as a switching channel region, and the body region is located below the upper surface, surrounded on both sides and below by the high voltage well region; a gate formed on the upper surface and located in the device region, the gate being stacked and in contact with the upper surface in the longitudinal direction for determining conduction and non-conduction of the high voltage device according to a gate voltage; a source electrode of the second conductivity type formed in the semiconductor substrate and in the device region, and located under the upper surface and contacting the upper surface in the longitudinal direction, and located under the upper surface, surrounded by the body region on both sides and under the body region, and located under a first side outside the gate electrode in a lateral direction, and adjacent to the gate electrode in the lateral direction; a drain electrode of the second conductivity type formed in the semiconductor substrate and in the device region, and located below and in contact with the upper surface in the longitudinal direction, and located below a second side opposite to the first side outside the gate electrode in the lateral direction, and separated from the gate electrode by the drift region in the lateral direction; and a first isolation well region of the first conductivity type, the first isolation well region being located outside the operation region, below the upper surface, surrounding the operation region, extending from the upper surface to the first deep well region in the longitudinal direction, and being connected to the first deep well region; the body region, the gate, the source, and the drain are all located in the operation region.

From another viewpoint, the present invention also provides a high voltage device manufacturing method, comprising the steps of: providing a semiconductor substrate, wherein the semiconductor substrate is provided with an upper surface and a lower surface which are opposite in a longitudinal direction; forming a first deep well region in the semiconductor substrate, the first deep well region having a first conductivity type; forming a transverse lightly doped region covering and connected to the first deep well region; forming a high-voltage well region in the semiconductor substrate, wherein the high-voltage well region has a second conductivity type and is located below the upper surface and contacts with the upper surface in the longitudinal direction, and the high-voltage well region covers and is connected to the transverse lightly doped region, and part of the high-voltage well region is used as a drift region; forming an insulating region on the upper surface to define an operation region; forming a body region in the semiconductor substrate and in the operation region, the body region having the first conductivity type and being located below and contacting the upper surface in the longitudinal direction, wherein a portion of the body region is used as a switching channel region and is located below the upper surface and surrounded by the high voltage well region on both sides and below; forming a gate on the upper surface and in the device region, the gate being stacked and in contact with the upper surface in the longitudinal direction for determining conduction and non-conduction of the high voltage device according to a gate voltage; forming a source electrode in the semiconductor substrate and in the device region, the source electrode having the second conductivity type and being located below and contacting the upper surface in the longitudinal direction, the source electrode being located below the upper surface and surrounded by the body region on both sides and below thereof, the source electrode being located below a first side outside the gate electrode in a lateral direction, the source electrode being adjacent to the gate electrode in the lateral direction; forming a drain electrode in the semiconductor substrate and in the device region, the drain electrode having the second conductivity type and being located below and in contact with the upper surface in the longitudinal direction, the drain electrode being located below a second side opposite to the first side outside the gate electrode in the lateral direction, and the drain electrode being separated from the gate electrode by the drift region in the lateral direction; and forming a first isolation well region outside the operation region and below the upper surface, the first isolation well region surrounding the operation region, extending from the upper surface to the first deep well region in the longitudinal direction, and being connected to the first deep well region, the first isolation well region having the first conductivity type; the body region, the gate, the source, and the drain are all located in the operation region.

In a preferred embodiment, the high voltage device further comprises: a second deep well region of the second conductivity type formed in the semiconductor substrate and located under and contacting the first deep well region and the first isolation well region in the longitudinal direction; and a second isolation well region of the second conductivity type, the second isolation well region being located outside the first isolation well region, surrounding the first isolation well region below the upper surface, extending from the upper surface to the second deep well region in the longitudinal direction, and being connected to the second deep well region.

In a preferred embodiment, a bottom depth of the hvw region is deeper than a bottom depth of the body region.

In a preferred embodiment, a bottom depth of the hvw region is no deeper than a bottom depth of the body region.

In a preferred embodiment, the high voltage device further comprises a longitudinal lightly doped region adjacent between the body region and the high voltage well region, and the longitudinal lightly doped region extends from the upper surface to the lateral lightly doped region in the longitudinal direction.

In a preferred embodiment, the high voltage device further comprises a field oxide region stacked and contacting on the upper surface in the longitudinal direction, and at least a portion of the gate adjacent to the drain side is stacked and contacting directly above the field oxide region.

In a preferred embodiment, the lateral lightly doped region has the first conductivity type or the second conductivity type, and the lateral lightly doped region has an impurity doping concentration lower than one tenth of an impurity doping concentration of the hvw region.

In a preferred embodiment, the step of forming a lateral lightly doped region comprises: in the step of forming the high-voltage well region, the depth of the high-voltage well region is adjusted so that the high-voltage well region is not in contact with the first deep well region and has a longitudinal gap so that the transverse lightly doped region is formed in the longitudinal gap.

The purpose, technical content, features and effects of the invention will be more easily understood through the following detailed description of specific embodiments.

Drawings

Fig. 1A and 1B respectively show a top view and a cross-sectional view of a double-Diffused Metal Oxide Semiconductor (DMOS) device 100 of the prior art;

FIGS. 2A and 2B illustrate a first embodiment of the present invention;

FIGS. 3A and 3B illustrate a second embodiment of the present invention;

FIGS. 4A and 4B illustrate a third embodiment of the present invention;

FIGS. 5A and 5B illustrate a fourth embodiment of the present invention;

FIGS. 6A and 6B illustrate a fifth embodiment of the present invention;

FIGS. 7A and 7B illustrate a sixth embodiment of the present invention;

FIGS. 8A and 8B illustrate a seventh embodiment of the present invention;

FIGS. 9A and 9B illustrate an eighth embodiment of the present invention;

FIGS. 10A and 10B illustrate a ninth embodiment of the present invention;

FIGS. 11A and 11B illustrate a tenth embodiment of the present invention;

FIGS. 12A and 12B illustrate an eleventh embodiment of the present invention;

FIGS. 13A and 13B illustrate a twelfth embodiment of the present invention;

FIGS. 14A-14L illustrate a thirteenth embodiment of the invention.

Description of the symbols in the drawings

100DMOS element

101, 201 semiconductor substrate

102, 202, 302, 602, 902 hvw well region

103, 203, 503, 803, 853 insulating region

103a, 203a, 503a, 1103a operation area

104 field oxide region

105, 205 body region

105a, 205a body pole

106, 206, 256, 806, 856 gate

107, 207, 257 source

108, 208, 258 drain

200, 250, 300, 350, 400, 450, 500, 550, 600, 650, 700, 750, 800, 850, 900, 950, 1000, 1100, 1150, 1200, 1250, 1300, 1350 high voltage element

201a upper surface

201b lower surface

210 first deep well region

211 first isolation well region

211a first isolation electrode

213 second deep well region

214 second isolation well region

214a second isolation electrode

412, 462, 712, 762, 1012, 1162,1312, 1362 longitudinal lightly doped regions

AA ', BB ', CC ', DD ', EE ', FF ', GG ', HH ', II ', JJ ', KK ', LL ', MM ' section line

Bottom depths of d1, d1 ', d2, d2 ', d3, d3 ', d4, d4 ', d5, d5 ', d6 and d6

Detailed Description

The drawings in the present invention are schematic and are intended to show the process steps and the up-down order of the layers, and the shapes, thicknesses and widths are not drawn to scale.

Referring to fig. 2A and 2B, a first embodiment of the invention is shown. Fig. 2A is a top view of a high voltage device 200 and a high voltage device 250 according to the present invention. In FIG. 2A, a schematic cross-sectional view along the line BB' is shown in FIG. 2B. Referring to fig. 2A and 2B, an insulating region 203 is formed in the semiconductor substrate 201 to define an operation region 203 a. The insulating region 203 is, for example, a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) structure as shown in the figure. As shown, the operation region 203a defined by the insulation region 203 includes two

high voltage devices

200 and 250 arranged in a mirror image.

In the semiconductor substrate 201, a hvw region 202, a body region 205, a body electrode 205a, a gate 206, a gate 256, a source 207, a source 257, a drain 208, a drain 258, a lateral lightly doped region 209, a first deep well region 210, a first isolation well region 211, and a first isolation electrode 211a are formed. The body region 205, the body electrode 205a, the first deep well region 210, the first isolation well region 211 and the first isolation electrode 211a have a first conductivity type; and the hvw region 202, source 207, source 257, drain 208, drain 258 have a second conductivity type. The semiconductor substrate 201 is not limited to a P-type silicon substrate, but may be another semiconductor substrate. The first conductivity type is, for example but not limited to, P-type, or N-type, which is the opposite of P-type. The second conductive type has a conductivity type opposite to the first conductive type, and when the first conductive type is P-type, the second conductive type is N-type; when the first conduction type is N type, the second conduction type is P type. Wherein the lateral lightly doped region 209 has, for example but not limited to, a first conductivity type or a second conductivity type; the lateral lightly doped region 209 has a first conductivity type or the second conductivity type, and the lateral lightly doped region 209 has an impurity doping concentration lower than one tenth of an impurity doping concentration of the hvw region 202. The method of forming the lateral lightly doped region 209 is, for example, but not limited to, in the step of forming the hvw region 202, adjusting the depth of the hvw region 202 such that the hvw region 202 does not contact the first hvw region 210 and has a longitudinal gap such that the lateral lightly doped region 209 is formed in the longitudinal gap. That is, when the hvw region 202 is formed by the ion implantation process, the acceleration voltage of the ion implantation process is adjusted such that the ion beam implantation depth does not reach the contact depth with the first deep well region 210, thereby preventing the hvw region 202 from contacting the first deep well region 210 and forming the lateral lightly doped region 209.

The body region 205, the body electrode 205a, the first deep well region 210, the first isolation well region 211 and the first isolation electrode 211a are formed by implanting a first conductive type impurity into a defined region of the semiconductor substrate 201 in the form of accelerated ions in an ion implantation process; the hvw region 202, the source 207, the source 257, the drain 208, and the drain 258 are defined by photolithography (including self-aligned process), and are formed by implanting impurities of the second conductivity type into the defined regions in the form of accelerated ions by ion implantation process. The lateral lightly doped region 209 covers and is connected to the first deep well region 210. Between the drain 208 and the gate 206 of the high voltage device 200, there is a drift region 202a (as indicated by the thin dashed box in fig. 2B) separating the drain 208 and the gate 206, and the length of the drift region 202a in the lateral direction (as indicated by the solid arrow) is adjusted according to the operation voltage applied during normal operation.

The high voltage device 200 is formed in a semiconductor substrate 201, wherein the semiconductor substrate 201 has an upper surface 201a (indicated by the broken line of the thick black dashed line in the upper half of the semiconductor substrate 201 in fig. 2B) and a lower surface 201B (indicated by the straight line of the thick black dashed line in the lower half of the semiconductor substrate 201 in fig. 2B) opposite to each other in the longitudinal direction (indicated by the arrow of the thick black dashed line in fig. 2B). The first deep well region 210 has a first conductivity type and is formed in the semiconductor substrate 201. The lateral lightly doped region 209 overlies and is connected to the first deep well region 210. The hvw region 202 has a second conductivity type, is formed in the semiconductor substrate 201, and in the longitudinal direction, the hvw region 202 is located below the upper surface 201a and contacts the upper surface 201a, and the hvw region 202 covers and is connected to the lateral lightly doped region 209, wherein a portion of the hvw region 202 is used as a drift region 202a (as indicated by the thin dashed line in fig. 2B). The insulating region 203 is formed on the upper surface 201a to define an operation region 203 a.

The body region 205 of the first conductivity type is formed in the semiconductor substrate 201 and located in the operation region 203a, and is located below the upper surface 201a and in contact with the upper surface 201a in the longitudinal direction, wherein a portion of the body region 205 is used as a switching channel region 205B (as indicated by the thick solid line frame in fig. 2B), and the body region 205 is located below the upper surface 201a, and surrounded on both sides and below by the hvw region 202. The gate 206 is formed on the top surface 201a and located in the device region 203a, and the gate 206 is stacked and contacted on the top surface 201a in the longitudinal direction for determining the conduction and non-conduction of the high voltage device 200 according to the gate voltage. The gate 206 includes a conductive layer, a dielectric layer, and a spacer layer. The conductor layer is used for electrical connection and receiving grid voltage; the dielectric layer electrically isolates the conductive layer from the semiconductor substrate 201 to prevent the conductive layer from being directly connected to the semiconductor substrate; the spacing layer covers the conductor layer for electrically isolating the conductor layer from other adjacent wires or electrical contacts. It should be noted that the switching channel region 205b is an inversion region formed when the gate voltage is applied to the gate 206 to turn on the high voltage device 200; the drift region 202a is a region through which the on-current flows between the switch channel region 205b and the drain 208, which is well known in the art and will not be described herein. The on-current is the main current flowing between the drain 208 and the source 207 when the high voltage device 200 is turned on, and the range of the vertical height of the current is mostly near the top surface 201 a.

The source 207 having the second conductivity type is formed in the semiconductor substrate 201 and located in the device region 203a, and is located below the upper surface 201a and in contact with the upper surface 201a in the longitudinal direction, and the source 207 is located below the upper surface 201a, surrounded on both sides and below by the body region 205, and in the lateral direction, the source 207 is located below the first side 206a outside the gate 206, and in the lateral direction, the source 207 is adjacent to the gate 206. The drain 208 of the second conductivity type is formed in the semiconductor substrate 204 and located in the device region 203a, and is located below the upper surface 201a and in contact with the upper surface 201a in the longitudinal direction, and the drain 208 is located below a second side 206b opposite to the first side 206a outside the gate 206 in the lateral direction, and the drain 208 and the gate 206 are separated by the drift region 202a in the lateral direction. The first isolation well region 211 has the first conductivity type, and the first isolation well region 211 is located outside the operation region 203a, below the upper surface 201a, surrounds the operation region 203a, extends downward from the upper surface 201a to the first deep well region 210 in the longitudinal direction, and is connected to the first deep well region 210. The body region 205, the gate 206, the source 207, and the drain 208 are all located in the operation region 203 a. It should be noted that the high voltage device 200 and the high voltage device 250 are arranged in the semiconductor substrate 201 in a mirror image manner and share the hvw region 202, the body region 205, the body electrode 205a, the lateral lightly doped region 209, the first deep well region 210, the first isolation well region 211 and the first isolation electrode 211 a. The first isolation electrode 211a is formed under the top surface 201a and contacts the top surface 201a, and is electrically connected to the first isolation well 211 to serve as an electrical contact of the first isolation well 211.

Fig. 3A and 3B show a second embodiment of the present invention. Fig. 3A is a top view of a high voltage device 300 and a high voltage device 350 according to the present invention. In FIG. 3A, a schematic cross-sectional view of the section line CC' is shown in FIG. 3B. Referring to fig. 3A and 3B, in the present embodiment, an insulating region 203 is formed in the semiconductor substrate 201 to define an operation region 203A. As shown, the operation region 203a defined by the insulation region 203 includes two mirror-image arranged

high voltage devices

300 and 350.

In the semiconductor substrate 201, a hvw region 302, a body region 205, a body electrode 205a, a gate 206, a gate 256, a source 207, a source 257, a drain 208, a drain 258, a lateral lightly doped region 309, a first deep well region 210, a first isolation well region 211, and a first isolation electrode 211a are formed. This embodiment is different from the first embodiment in that: in the first embodiment, the bottom depth d1 of the hvw region 202 is deeper than the bottom depth d2 of the body region 205; in the present embodiment, the bottom depth d1 'of the hvw region 302 is not deeper than the bottom depth d 2' of the body region 205.

Fig. 4A and 4B show a third embodiment of the present invention. Fig. 4A is a top view of a high voltage device 400 and a high voltage device 250 according to the present invention. In FIG. 4A, a cross-sectional view along section line DD' is shown in FIG. 4B. Referring to fig. 4A and 4B, in the present embodiment, an insulating region 203 is formed in the semiconductor substrate 201 to define an operation region 203 a. As shown, the operation region 203a defined by the insulation region 203 includes two mirror-image arranged

high voltage devices

400 and 450.

In the semiconductor substrate 201, a hvw region 202, a body region 205, a body electrode 205a, a gate 206, a gate 256, a source 207, a source 257, a drain 208, a drain 258, a lateral lightly doped region 209, a first deep well region 210, a first isolation well region 211, a first isolation electrode 211a, a vertical lightly doped region 412, and a vertical lightly doped region 462 are formed. This embodiment is different from the first embodiment in that: in the present embodiment, the

high voltage devices

400 and 450 further include vertical lightly doped

regions

412 and 462, respectively. The vertical lightly doped region 412 is adjacent to the body region 205 and the hvw region 202, and the vertical lightly doped region 412 extends from the top surface 201a to the lateral lightly doped region 209 in the vertical direction. The vertical lightly doped region 412 has the first conductivity type or the second conductivity type, and the vertical lightly doped region 412 has an impurity doping concentration, such as but not limited to, lower than one tenth of the impurity doping concentration of the hvw region 202. The vertical lightly doped region 412 is formed by, for example, but not limited to, masking a defined region of the vertical lightly doped region 412 with a photoresist layer or other mask to prevent ion beam implantation during the ion implantation process to form the hvw region 202.

Fig. 5A and 5B illustrate a fourth embodiment of the present invention. Fig. 5A is a top view of a high voltage device 500 and a high voltage device 550 according to the present invention. In FIG. 5A, a schematic cross-sectional view along section line EE' is shown in FIG. 5B. Referring to fig. 5A and 5B, in the present embodiment, an insulating region 503 is formed in the semiconductor substrate 201 to define an operation region 503 a. As shown, the operation region 503a defined by the insulation region 503 includes two mirror-image arranged

high voltage devices

500 and 550.

In the semiconductor substrate 201, a hvw region 202, a body region 205, a body electrode 205a, a gate 206, a gate 256, a source 207, a source 257, a drain 208, a drain 258, a lateral lightly doped region 209, a first deep well region 210, a first isolation well region 211, a first isolation electrode 211a, a second deep well region 213, a second isolation well region 214, and a second isolation electrode 214a are formed. This embodiment is different from the first embodiment in that: in the present embodiment, the high voltage device 500 further includes a second deep well region 213 and a second isolation well region 214. The second deep well region 213 of the second conductivity type is formed in the semiconductor substrate 201 and is located below the first deep well region 210 and the first isolation well region 211 in the longitudinal direction and contacts the first deep well region 210 and the first isolation well region 211. The second isolation well region 214 has a second conductivity type, and the second isolation well region 214 is located outside the first isolation well region 211, surrounds the first isolation well region 211 below the upper surface 201a, extends downward from the upper surface 201a to the second deep well region 213 in the longitudinal direction, and is connected to the second deep well region 213. The second isolation electrode 214a is formed under the top surface 201a and contacts the top surface 201a, and is electrically connected to the second isolation well 214 to serve as an electrical contact point of the second isolation well 214. It should be noted that the high voltage device 500 and the high voltage device 550 are arranged in the semiconductor substrate 201 in a mirror image manner and share the hvw region 202, the body region 205, the body pole 205a, the lateral lightly doped region 209, the first deep well region 210, the first isolation well region 211, the first isolation pole 211a, the second deep well region 213, the second isolation well region 214 and the second isolation pole 214 a.

Fig. 6A and 6B show a fifth embodiment of the present invention. Fig. 6A is a top view of a high voltage device 600 and a high voltage device 650 according to the present invention. In FIG. 6A, a cross-sectional view of the sectional line FF' is shown in FIG. 6B. Referring to fig. 6A and 6B, in the present embodiment, an insulating region 503 is formed in the semiconductor substrate 201 to define an operation region 503 a. As shown, the operation region 503a defined by the insulation region 503 includes two mirror-image

high voltage devices

600 and 650.

In the semiconductor substrate 201, a hvw region 602, a body region 205, a body electrode 205a, a gate 206, a gate 256, a source 207, a source 257, a drain 208, a drain 258, a lateral lightly doped region 609, a first deep well region 210, a first isolation well region 211, a first isolation electrode 211a, a second deep well region 213, a second isolation well region 214, and a second isolation electrode 214a are formed. The present embodiment is different from the fourth embodiment in that: in the fourth embodiment, the bottom depth d3 of the hvw region 202 is deeper than the bottom depth d4 of the body region 205; in the present embodiment, the bottom depth d3 'of the hvw region 602 is not deeper than the bottom depth d 4' of the body region 205.

Fig. 7A and 7B show a sixth embodiment of the present invention. Fig. 7A is a top view of the high voltage device 700 and the high voltage device 550 according to the present invention. In FIG. 7A, a schematic cross-sectional view of GG' is shown in FIG. 7B. Referring to fig. 7A and 7B, in the present embodiment, an insulating region 503 is formed in the semiconductor substrate 201 to define an operation region 503 a. As shown, the operation region 503a defined by the insulation region 503 includes two mirror-image arranged

high voltage devices

700 and 750.

In the semiconductor substrate 201, a hvw region 202, a body region 205, a body electrode 205a, a gate 206, a gate 256, a source 207, a source 257, a drain 208, a drain 258, a lateral lightly doped region 209, a first deep well region 210, a first isolation well region 211, a first isolation electrode 211a, a second deep well region 213, a second isolation well region 214 and a second isolation electrode 214a, a vertical lightly doped region 712 and a vertical lightly doped region 762 are formed. This embodiment is different from the fourth embodiment in that: in the present embodiment, the

high voltage devices

700 and 750 further include longitudinal lightly doped regions 712 and 762, respectively. A vertical lightly doped region 712 is adjacent between the body region 205 and the hvw region 202, and in the vertical direction, the vertical lightly doped region 712 extends from the top surface 201a down to the lateral lightly doped region 209. The vertical lightly doped region 712 has the first conductivity type or the second conductivity type, and the vertical lightly doped region 712 has an impurity doping concentration, such as but not limited to, lower than one tenth of the impurity doping concentration of the hvw region 202. The longitudinal lightly doped region 712 may be formed by, for example, but not limited to, masking a defined region of the longitudinal lightly doped region 712 with a photoresist layer or other mask during the ion implantation process step to form the hvw region 202, thereby avoiding ion beam implantation to form the longitudinal lightly doped region 712.

Fig. 8A and 8B show a seventh embodiment of the present invention. Fig. 8A is a top view of a high voltage device 800 and a high voltage device 850 according to the present invention. In FIG. 8A, a schematic cross-sectional view of HH' is shown in FIG. 8B. Referring to fig. 8A and 8B, in the present embodiment, an insulating region 203 is formed in the semiconductor substrate 201 to define an operation region 203 a. As shown, the operation region 203a defined by the insulation region 203 includes two mirror-image

high voltage devices

800 and 850.

In the semiconductor substrate 201, the hvw region 202, the body region 205, the body electrode 205a, the gate 806, the gate 856, the source 207, the source 257, the drain 208, the drain 258, the lightly doped lateral region 209, the first deep well region 210, the first isolation well region 211, and the first isolation electrode 211a are formed. This embodiment is different from the first embodiment in that: in the present embodiment, the high voltage device 800 further includes a field oxide region 803, the field oxide region 803 is stacked and contacted on the upper surface 201a in the vertical direction, and at least a portion of the gate 806 near the drain 208 is stacked and contacted directly above the field oxide region 803. The high voltage device 850 further includes a field oxide 853, the field oxide 853 is stacked and contacted on the upper surface 201a in the vertical direction, and at least a portion of the gate 856 near the drain 258 side is stacked and contacted right above the field oxide 853. It should be noted that the high voltage device 800 and the high voltage device 850 are arranged in the semiconductor substrate 201 in a mirror image, and share the hvw region 202, the body region 205, the body pole 205a, the lateral lightly doped region 209, the first deep well region 210, the first isolation well region 211 and the first isolation pole 211 a.

FIGS. 9A and 9B illustrate an eighth embodiment of the present invention. Fig. 9A is a top view of a high voltage device 900 and a high voltage device 950 according to the present invention. In FIG. 9A, a schematic cross-sectional view along section line II' is shown in FIG. 9B. Referring to fig. 9A and 9B, in the present embodiment, an insulating region 203 is formed in the semiconductor substrate 201 to define an operation region 203 a. As shown, the operation region 203a defined by the insulation region 203 includes two mirror-image

high voltage devices

900 and 950.

In the semiconductor substrate 201, a hvw region 902, a body region 905, a body electrode 205a, a gate 806, a gate 856, a source 207, a source 257, a drain 208, a drain 258, a lateral lightly doped region 209, a first deep well region 210, a first isolation well region 211, and a first isolation electrode 211a are formed. This embodiment is different from the seventh embodiment in that: in the seventh embodiment, the bottom depth d5 of the hvw region 202 is deeper than the bottom depth d6 of the body region 205; in the present embodiment, the bottom depth d5 'of the hvw region 902 is not deeper than the bottom depth d 6' of the body region 905.

FIGS. 10A and 10B show a ninth embodiment of the present invention. Fig. 10A is a top view of a high voltage device 1000 and a high voltage device 850 according to the present invention. In FIG. 10A, a cross-sectional view of a cross-section of JJ' is shown in FIG. 10B. Referring to fig. 10A and 10B, in the present embodiment, an insulating region 203 is formed in the semiconductor substrate 201 to define an operation region 203 a. As shown, the operation region 203a defined by the insulation region 203 includes two

high voltage devices

1000 and 1150 arranged in a mirror image.

In the semiconductor substrate 201, the hvw region 202, the body region 205, the body pole 205a, the gate 806, the gate 856, the source 207, the source 257, the drain 208, the drain 258, the lateral lightly doped region 209, the first deep well region 210, the first isolation well region 211, the first isolation pole 211a, the vertical lightly doped region 1012, and the vertical lightly doped region 1162 are formed. This embodiment is different from the seventh embodiment in that: in the present embodiment, the

high voltage devices

1000 and 1150 further comprise vertical lightly doped

regions

1012 and 1162, respectively. A vertical lightly doped region 1012 is adjacent to the body region 205 and the hvw region 202, and the vertical lightly doped region 1012 extends from the top surface 201a to the lateral lightly doped region 209 in the vertical direction. The vertical lightly doped region 1012 has the first conductivity type or the second conductivity type, and the vertical lightly doped region 1012 has an impurity doping concentration, such as but not limited to, lower than one tenth of the impurity doping concentration of the hvw region 202. The vertical lightly doped region 1012 may be formed by, for example, but not limited to, masking a defined region of the vertical lightly doped region 1012 with a photoresist layer or other mask to prevent ion beam implantation during the ion implantation process to form the hvw region 202.

FIGS. 11A and 11B show a tenth embodiment of the present invention. Fig. 11A is a top view of a high voltage device 1100 and a high voltage device 1150 according to the present invention. In fig. 11A, a cross-sectional view along KK' is shown in fig. 11B. Referring to fig. 11A and 11B, in the present embodiment, an insulating region 1103 is formed in the semiconductor substrate 201 to define an operation region 1103 a. As shown, the operation region 1103a defined by the insulation region 1103 includes two

high voltage devices

1100 and 1150 arranged in a mirror image.

In the semiconductor substrate 201, the hvw region 202, the body region 205, the body electrode 205a, the gate 806, the gate 856, the source 207, the source 257, the drain 208, the drain 258, the lateral lightly doped region 209, the first deep well region 210, the first isolation well region 211, the first isolation electrode 211a, the second deep well region 1113, the second isolation well region 1114, and the second isolation electrode 1114a are formed. This embodiment is different from the seventh embodiment in that: in the present embodiment, the high voltage device 1100 further includes a second deep well region 1113 and a second isolation well region 1114. The second deep well region 1113 of the second conductivity type is formed in the semiconductor substrate 201 and is located below the first deep well region 210 and the first isolation well region 211 in the longitudinal direction and contacts the first deep well region 210 and the first isolation well region 211. The second isolation well 1114 has a second conductivity type, and the second isolation well 1114 is located outside the first isolation well 211, surrounds the first isolation well 211 below the upper surface 201a, extends downward from the upper surface 201a to the second deep well 213 in the longitudinal direction, and is connected to the second deep well 213. The second isolation electrode 214a is formed under the top surface 201a and contacts the top surface 201a, and is electrically connected to the second isolation well 214 to serve as an electrical contact of the second isolation well 1114. It should be noted that the high voltage device 1100 and the high voltage device 1150 are arranged in the semiconductor substrate 201 in a mirror image manner and share the hvw region 202, the body region 205, the body electrode 205a, the lateral lightly doped region 209, the first deep well region 210, the first isolation well region 211, the first isolation electrode 211a, the second deep well region 1113, the second isolation well region 1114 and the second isolation electrode 1114 a.

Fig. 12A and 12B show an eleventh embodiment of the present invention. FIG. 12A is a top view of a high voltage device 1200 and a high voltage device 1250 according to the present invention. In FIG. 12A, a cross-sectional view of section line LL' is shown in FIG. 12B. Referring to fig. 12A and 12B, in the present embodiment, an insulating region 1103 is formed in the semiconductor substrate 201 to define an operation region 1103 a. As shown, the operation area 1103a defined by the insulation area 1103 includes two mirror-image arranged

high voltage devices

1200 and 1250.

In the semiconductor substrate 201, the hvw region 1202, the body region 1205, the body electrode 205a, the gate 806, the gate 856, the source 207, the source 257, the drain 208, the drain 258, the lightly doped lateral region 209, the first deep well region 210, the first isolation well region 211, the first isolation electrode 211a, the second deep well region 1113, the second isolation well region 1114, and the second isolation electrode 1114a are formed. This embodiment is different from the tenth embodiment in that: in the tenth embodiment, the bottom depth d7 of the hvw region 202 is deeper than the bottom depth d8 of the body region 205; in the present embodiment, the bottom depth d7 'of the hvw region 1202 is not deeper than the bottom depth d 8' of the body region 1205.

FIGS. 13A and 13B show a twelfth embodiment of the present invention. Fig. 13A is a top view of a high voltage device 1300 and a high voltage device 1150 according to the present invention. In FIG. 13A, a cross-sectional view of the MM' cross-section is shown in FIG. 13B. Referring to fig. 13A and 13B, in the present embodiment, an insulating region 1103 is formed in the semiconductor substrate 201 to define an operation region 1103A. As shown, the operation region 1103a defined by the insulation region 1103 includes two mirror-image arranged

high voltage elements

1300 and 1350.

In the semiconductor substrate 201, a hvw region 202, a body region 205, a body electrode 205a, a gate 806, a gate 856, a source 207, a source 257, a drain 208, a drain 258, a lateral lightly doped region 209, a first deep well region 210, a first isolation well region 211, a first isolation electrode 211a, a second deep well region 1113, a second isolation well region 1114, a second isolation electrode 1114a, a vertical lightly doped region 1312, and a vertical lightly doped region 1362 are formed. This embodiment is different from the tenth embodiment in that: in the present embodiment, the

high voltage devices

1300 and 1350 further comprise vertical lightly doped

regions

1312 and 1362, respectively. A vertical lightly doped region 1312 is adjacent to the body region 205 and the hvw region 202, and the vertical lightly doped region 1312 extends from the top surface 201a to the lateral lightly doped region 209 in the vertical direction. The vertical lightly doped region 1312 has the first conductivity type or the second conductivity type, and the vertical lightly doped region 1312 has an impurity doping concentration, which is, for example, but not limited to, lower than one tenth of the impurity doping concentration of the hvw region 202. The vertical lightly doped region 1312 may be formed by, for example, but not limited to, masking a defined region of the vertical lightly doped region 1312 with a photoresist layer or other mask during the ion implantation process to form the hvw region 202, thereby avoiding ion beam implantation and forming the vertical lightly doped region 1312.

FIGS. 14A-14L illustrate a thirteenth embodiment of the invention. Fig. 14A-14L are schematic cross-sectional views illustrating a method for manufacturing the

high voltage elements

200 and 250 according to the present invention. First, as shown in fig. 14A and 14B (fig. 14A is a schematic top view, and fig. 14B is a schematic cross-sectional view), a semiconductor substrate 201 is provided; the semiconductor substrate 201 is not limited to a P-type silicon substrate, but may be another semiconductor substrate. The semiconductor substrate 21 has an upper surface 201a (for avoiding misunderstanding, the upper surface 201a is shown by a thick dashed line in fig. 14F) and a lower surface 201B opposite to each other in a longitudinal direction (shown by a thick dashed arrow in fig. 14B). Next, forming a first deep well region 210 in the semiconductor substrate 201, and located above the lower surface 201 in the longitudinal direction, with or without contacting the lower surface 201 b; the method for forming the first deep well region 210 is, for example, but not limited to, a photolithography process, an ion implantation process (as indicated by the thin dashed arrow in the figure), and a thermal process, which are well known to those skilled in the art and will not be described herein. Next, with continued reference to fig. 14A and 14B, a first isolation well region 211 is formed outside the operation region (the range of the operation region will be described in detail later) and below the upper surface 201a, the first isolation well region 211 surrounds the operation region, extends from the upper surface 201a to the first deep well region 210 in the longitudinal direction, and is connected to the first deep well region 210, and the first isolation well region 211 has the first conductivity type.

Next, as shown in fig. 14C and fig. 14D (fig. 14C is a top view and fig. 14D is a cross-sectional view), the hvw region 202 is formed in the semiconductor substrate 201, the hvw region 202 has the second conductivity type, and in the longitudinal direction, the hvw region 202 is located below the upper surface 201a and contacts the upper surface 201a, and the hvw region 202 covers and is connected to the lateral lightly doped region 209, wherein a portion of the hvw region 202 is used as the drift region 202 a. The method for forming the hvw region 202 is, for example, but not limited to, formed by photolithography, ion implantation (as indicated by the thin dashed arrow in the figure) and process steps such as masking with a photoresist 202', and thermal processes, which are well known to those skilled in the art and will not be described herein. The method of forming the lateral lightly doped region 209 is, for example, but not limited to, in the step of forming the hvw region 202, adjusting the depth of the hvw region 202 such that the hvw region 202 does not contact the first hvw region 210 and has a longitudinal gap such that the lateral lightly doped region 209 is formed in the longitudinal gap. That is, when the hvw region 202 is formed by the ion implantation process, the acceleration voltage of the ion implantation process is adjusted such that the ion beam implantation depth does not reach the contact depth with the first deep well region 210, thereby preventing the hvw region 202 from contacting the first deep well region 210 and forming the lateral lightly doped region 209.

Next, as shown in fig. 14E and 14F (fig. 14E is a schematic top view, and fig. 14F is a schematic cross-sectional view), an insulating region 203 is formed in the semiconductor substrate 201 to define an operation region 203 a. The insulating region 203 is, for example, a Shallow Trench Isolation (STI) structure or a local oxidation on silicon (LOCOS) structure as shown in the figure, so as to define an operation region 203 a.

Next, as shown in fig. 14G and 14H, a body region 205 and a body electrode 205a, both having the first conductivity type, are formed in the semiconductor substrate 201, and are located in the operation region 203a, and are located below the upper surface 201a and in contact with the upper surface 201a in the longitudinal direction. A portion of the body region 205 is used as the switch channel region 205b, and the body region 205 is under the top surface 201a, surrounded by the hvw region 202 on both sides and below. Then, a first isolation electrode 211a is formed to serve as an electrical contact of the first isolation well 211.

Next, as shown in fig. 14I and 14J,

gates

206 and 256 are formed on the upper surface 201a, and in the vertical direction, the

gates

206 and 256 are stacked and contacted on the upper surface 201a to determine whether the

high voltage devices

200 and 250 are turned on or off according to the gate voltages, respectively.

Next, as shown in fig. 14K and 14L, the

source electrodes

207 and 257, and the

drain electrodes

208 and 258 are formed, for example, by defining each region through photolithography process steps (including self-aligned process steps), and implanting second conductive type impurities in the form of accelerated ions into the defined regions through ion implantation process steps, respectively. The source 207, the drain 208 are respectively located below two outer sides of the gate 206. The source 207 is located in the device region 203a, and is located below the upper surface 201a in the longitudinal direction and in contact with the upper surface 201a, and the source 207 is located below the upper surface 201a, surrounded on both sides and below by the body region 205, and in the lateral direction, the source 207 is located below the first side 206a outside the gate 206, and in the lateral direction, the source 207 is adjacent to the gate 206.

The drain 208 of the second conductivity type is formed in the semiconductor substrate 201 and located in the device region 203a, and is located below the upper surface 201a and contacting the upper surface 201a in the longitudinal direction, and is located below the second side 206b opposite to the first side 206a outside the gate 206 in the lateral direction, and the drain 208 and the gate 206 are separated by the drift region 202a in the lateral direction, and the length of the drift region 202a in the lateral direction (the direction indicated by the dashed arrow) is adjusted according to an operating voltage applied during normal operation. In which a portion of the body region 205 is used as the switch channel region 205b (as illustrated by the bold solid line in fig. 14E). The body region 205, the gate 206, the source 207, and the drain 208 are all located in the operation region 203 a.

The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the contents of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. Equivalent variations will occur to those skilled in the art, within the same spirit of the invention. For example, other process steps or structures, such as threshold voltage adjustment regions, may be added without affecting the primary characteristics of the device; for another example, the lithography technique is not limited to the mask technique, but may include electron beam lithography; for another example, the conductive P-type and N-type can be interchanged, only the other regions need to be interchanged accordingly. The scope of the invention should be determined to encompass all such equivalent variations. Furthermore, equivalent variations and combinations will occur to those skilled in the art, within the same spirit of the invention, for example, the invention may be applied to other forms of high voltage components. It is understood that equivalent variations and combinations, not necessarily all illustrated, will occur to those of skill in the art, which combinations are not necessarily intended to be limiting. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above.

Claims

1. A high voltage device formed on a semiconductor substrate, wherein the semiconductor substrate has an upper surface and a lower surface opposite to each other in a longitudinal direction, the high voltage device comprising:

a first deep well region of a first conductivity type formed in the semiconductor substrate;

a transverse lightly doped region covering and connected to the first deep well region;

a high voltage well region of a second conductivity type formed in the semiconductor substrate and in the longitudinal direction, the high voltage well region being located below and contacting the upper surface, and the high voltage well region covering and connecting to the lateral lightly doped region, wherein a portion of the high voltage well region is used as a drift region;

an insulating region formed on the upper surface for defining an operation region;

a body region of the first conductivity type formed in the semiconductor substrate and located in the operating region, and located below and contacting the upper surface in the longitudinal direction, wherein a portion of the body region is used as a switching channel region, and the body region is located below the upper surface, surrounded on both sides and below by the high voltage well region;

a gate formed on the upper surface and located in the device region, the gate being stacked and in contact with the upper surface in the longitudinal direction for determining conduction and non-conduction of the high voltage device according to a gate voltage;

a source electrode of the second conductivity type formed in the semiconductor substrate and in the device region, and located under the upper surface and contacting the upper surface in the longitudinal direction, and located under the upper surface, surrounded by the body region on both sides and under the body region, and located under a first side outside the gate electrode in a lateral direction, and adjacent to the gate electrode in the lateral direction;

a drain electrode of the second conductivity type formed in the semiconductor substrate and in the device region, and located below and in contact with the upper surface in the longitudinal direction, and located below a second side opposite to the first side outside the gate electrode in the lateral direction, and separated from the gate electrode by the drift region in the lateral direction; and

a first isolation well region of the first conductivity type, the first isolation well region being located outside the operation region, below the upper surface, surrounding the operation region, extending from the upper surface to the first deep well region in the longitudinal direction, and being connected to the first deep well region;

the body region, the gate, the source, and the drain are all located in the operation region.

2. The high voltage component of claim 1, further comprising:

a second deep well region of the second conductivity type formed in the semiconductor substrate and located under and contacting the first deep well region and the first isolation well region in the longitudinal direction; and

and a second isolation well region of the second conductivity type, the second isolation well region being located outside the first isolation well region, surrounding the first isolation well region below the upper surface, extending from the upper surface to the second deep well region in the longitudinal direction, and being connected to the second deep well region.

3. The device of claim 1 or 2, wherein a bottom depth of the hvw region is deeper than a bottom depth of the body region.

4. The HVW device of claim 1 or claim 2, wherein a bottom depth of the HVW region is not deeper than a bottom depth of the body region.

5. The high-voltage device as claimed in claim 1 or 2, further comprising a vertical lightly doped region adjacent between the body region and the hvw region, wherein the vertical lightly doped region extends from the top surface to the lateral lightly doped region in the vertical direction.

6. The high-voltage device as claimed in claim 1 or 2, further comprising a field oxide region stacked and contacting on the upper surface in the longitudinal direction, and at least a portion of the gate adjacent to the drain is stacked and contacting directly above the field oxide region.

7. The device of claim 6, wherein a bottom depth of the HVW region is deeper than a bottom depth of the body region.

8. The device of claim 6, wherein a bottom depth of the HVW region is not deeper than a bottom depth of the body region.

9. The high-voltage device of claim 6, further comprising a vertical lightly doped region adjacent between said body region and said HVW region, said vertical lightly doped region extending from said top surface to said lateral lightly doped region in said vertical direction.

10. The high voltage device of claim 1 or 2, wherein the lateral lightly doped region has the first conductivity type or the second conductivity type, and the lateral lightly doped region has an impurity doping concentration less than one tenth of an impurity doping concentration of the HVW region.

11. A method for manufacturing a high voltage device, comprising the steps of:

providing a semiconductor substrate, wherein the semiconductor substrate is provided with an upper surface and a lower surface which are opposite in a longitudinal direction;

forming a first deep well region in the semiconductor substrate, the first deep well region having a first conductivity type;

forming a transverse lightly doped region covering and connected to the first deep well region;

forming a high-voltage well region in the semiconductor substrate, wherein the high-voltage well region has a second conductivity type and is located below the upper surface and contacts with the upper surface in the longitudinal direction, and the high-voltage well region covers and is connected to the transverse lightly doped region, and part of the high-voltage well region is used as a drift region;

forming an insulating region on the upper surface to define an operation region;

forming a body region in the semiconductor substrate and in the operation region, the body region having the first conductivity type and being located below and contacting the upper surface in the longitudinal direction, wherein a portion of the body region is used as a switching channel region and is located below the upper surface and surrounded by the high voltage well region on both sides and below;

forming a gate on the upper surface and in the device region, the gate being stacked and in contact with the upper surface in the longitudinal direction for determining conduction and non-conduction of the high voltage device according to a gate voltage;

forming a source electrode in the semiconductor substrate and in the device region, the source electrode having the second conductivity type and being located below and contacting the upper surface in the longitudinal direction, the source electrode being located below the upper surface and surrounded by the body region on both sides and below thereof, the source electrode being located below a first side outside the gate electrode in a lateral direction, the source electrode being adjacent to the gate electrode in the lateral direction;

forming a drain electrode in the semiconductor substrate and in the device region, the drain electrode having the second conductivity type and being located below and in contact with the upper surface in the longitudinal direction, the drain electrode being located below a second side opposite to the first side outside the gate electrode in the lateral direction, and the drain electrode being separated from the gate electrode by the drift region in the lateral direction; and

forming a first isolation well region outside the operation region and below the upper surface, the first isolation well region surrounding the operation region, extending from the upper surface to the first deep well region in the longitudinal direction, and being connected to the first deep well region, the first isolation well region having the first conductivity type;

12. The manufacturing method of a high-voltage component according to claim 11, further comprising:

forming a second deep well region in the semiconductor substrate, the second deep well region having the second conductivity type and being located below and contacting the first deep well region and the first isolation well region in the longitudinal direction; and

forming a second isolation well region outside the first isolation well region and below the upper surface, surrounding the first isolation well region, extending from the upper surface to the second deep well region in the longitudinal direction, and connected to the second deep well region, the second isolation well region having the second conductivity type.

13. The method of claim 11 or 12, wherein a bottom depth of the hvw region is deeper than a bottom depth of the body region.

14. The method of claim 11 or 12, wherein a bottom depth of the hvw region is not deeper than a bottom depth of the body region.

15. The manufacturing method of a high-voltage component according to claim 11 or 12, further comprising: forming a longitudinal lightly doped region adjacent to the body region and the HVW region, wherein the longitudinal lightly doped region extends from the upper surface to the transverse lightly doped region in the longitudinal direction.

16. The manufacturing method of a high-voltage component according to claim 11 or 12, further comprising: and forming a field oxide region which is stacked and contacted on the upper surface in the longitudinal direction, wherein at least one part of the region of the grid electrode close to the drain electrode side is stacked and contacted right above the field oxide region.

17. The method of claim 16, wherein a bottom depth of the hvw region is deeper than a bottom depth of the body region.

18. The method of claim 16, wherein a bottom depth of the hvw region is not deeper than a bottom depth of the body region.

19. The method of claim 16, further comprising forming a vertical lightly doped region adjacent between said body region and said hvw region, said vertical lightly doped region extending from said top surface to said lateral lightly doped region in said vertical direction.

20. The method of claim 11 or 12, wherein the step of forming a lateral lightly doped region comprises: in the step of forming the high-voltage well region, the depth of the high-voltage well region is adjusted so that the high-voltage well region is not in contact with the first deep well region and has a longitudinal gap so that the transverse lightly doped region is formed in the longitudinal gap.