CN115719765A - Power element and method for manufacturing the same - Google Patents

Abstract

The invention provides a power element and a manufacturing method thereof. The power element includes: the semiconductor device comprises a semiconductor layer, a well region, a body region, a grid electrode, a source electrode, a drain electrode, a field oxidation region and a self-alignment drift region. The field oxide region is formed on the upper surface of the semiconductor layer and is arranged between the grid electrode and the drain electrode. The field oxide region is formed by a chemical mechanical polishing process step. The self-aligned drift region is formed in the semiconductor layer, and the self-aligned drift region is completely located and connected right below the field oxide region.

Description

Power element and method for manufacturing the same

Technical Field

The present invention relates to a power device and a method for fabricating the same, and more particularly, to a power device having a field oxide region and a self-aligned drift region and a method for fabricating the same.

Background

Fig. 1A and 1B respectively show a top view and a cross-sectional view of a conventional power device 100. FIG. 1B shows a cross-sectional view of the AA' cross-section of FIG. 1A. The term "power device" means that the voltage applied to the drain is higher than 5V during normal operation. In general, a drift region 12a (as indicated by the dashed-line frame in fig. 1B) is disposed between the drain and the gate of the power device to separate the drain 19 from the body region 16, and the lateral length of the drift region 12a is adjusted according to the operating voltage applied during normal operation. As shown in fig. 1A and 1B, the power device 100 includes: well region 12, insulating structure 13, body region 16, gate 17, source 18 and drain 19. The well 12 has an N-type conductivity and is formed on the substrate 11, and the insulating structure 13 is a local oxidation of silicon (LOCOS) structure to define an operation region 13a as a main active region of the power device 100 during operation. The range of the operation region 13a is indicated by a thick black dashed box in fig. 1A. In order to increase the breakdown voltage of the power device 100, the length of the drift region 12a in the channel direction may be increased, but the on-resistance may be increased, so that the operation speed may be decreased; in addition, the N-type impurity concentration difference between the drift region 12a and the drain 19 is large, and the voltage difference between the voltages coupled to the drift region and the drain exceeds a high voltage of 5V to several hundred V, which limits the breakdown voltage of the power device 100, and limits the application range of the power device 100, thereby reducing the performance of the device.

In view of the above, the present invention provides a power device and a method for manufacturing the same, which can increase the breakdown voltage during the off operation, increase the withstand voltage (breakdown voltage) of the power device 100, and reduce the on-resistance.

Disclosure of Invention

In one aspect, the present invention provides a power device, comprising: a semiconductor layer formed on a substrate, the semiconductor layer having an upper surface; a well region of a first conductivity type formed in the semiconductor layer, the well region being located below and connected to the upper surface; a body region of a second conductivity type formed in the semiconductor layer, the body region being located below and connected to the upper surface, the body region being located adjacent to the well region in a channel direction; a gate formed on the upper surface, wherein a portion of the body region is located right under the gate and connected to the gate to provide an inversion current channel of the power device in a conducting operation, and a portion of the well region is located right under the gate to provide a drift current channel of the power device in the conducting operation; a source and a drain of the first conductivity type, the source and the drain being formed under and connected to the upper surface and respectively located in the body region under the outside of the gate and in the well region away from the body region side; a field oxide region formed on the upper surface and between the gate and the drain, the field oxide region being formed by a Chemical Mechanical Polishing (CMP) process; and a self-aligned drift region of the first conductivity type formed in the semiconductor layer and completely located and connected to the right under the field oxide region.

In another aspect, the present invention provides a method for manufacturing a power device, comprising: forming a semiconductor layer on a substrate, the semiconductor layer having an upper surface; forming a well region in the semiconductor layer, the well region having a first conductivity type and being located below and connected to the upper surface; forming a body region in the semiconductor layer, the body region having a second conductivity type, the body region being located below and connected to the upper surface, the body region being adjacent to the well region in a channel direction; forming a gate on the upper surface, wherein a portion of the body region is located right under the gate and connected to the gate to provide an inversion current channel of the power device in a conducting operation, and a portion of the well region is located right under the gate to provide a drift current channel of the power device in the conducting operation; forming a source and a drain under the upper surface and connected to the upper surface, the source and the drain having the first conductivity type and being located in the body region under the outside of the gate and the well region away from the body region side, respectively; forming a field oxide region on the upper surface by a Chemical Mechanical Polishing (CMP) process, wherein the field oxide region is between the gate and the drain; and forming a self-aligned drift region in the semiconductor layer, wherein the self-aligned drift region has the first conductivity type and is completely located and connected right below the field oxide region.

In one embodiment, the power device further includes a field plate having conductivity, the field plate is formed on the field oxide region and connected to the field oxide region, and the field plate is electrically connected to a predetermined potential to mitigate electric field distribution during operation of the power device.

In one embodiment, the self-aligned drift region has a first conductive type impurity concentration lower than that of the drain, and the self-aligned drift region has a first conductive type impurity concentration higher than that of the well.

In one embodiment, the self-aligned drift region and the field oxide region are defined by the same photolithography process.

In one embodiment, the field plate is electrically connected to the source.

In an embodiment, the method for manufacturing a power device further includes: forming a shield on the upper surface and connected to the upper surface by a lithography process step, wherein the shield defines the field oxide region and the self-aligned drift region; implanting the first conductive type impurity into the region defined by the shield in the form of accelerated ions by an ion implantation process step to form the self-aligned drift region; depositing an oxide layer by a deposition process step, and removing the oxide layer outside the region defined by the mask by the CMP process step; and removing the shield.

The invention has the advantages that the low-voltage region can be protected by covering the whole low-voltage region through the shield and only exposing the upper surface of the high-voltage region, the insulating structure can be prevented from being etched through the shield, the self-aligned drift region and the field oxide region can be simultaneously formed by only using a single shield, the influence of a heating process on the low-voltage region can be reduced by replacing the heating process step through the CMP process step, and the high-voltage region can have the gradual first conductive impurity concentration through the self-aligned drift region.

The purpose, technical content, features and effects of the present invention will be more readily understood by the following detailed description of specific embodiments.

Drawings

Fig. 1A and 1B respectively show a top view and a cross-sectional view of a conventional power device.

Fig. 2A and 2B are a schematic top view and a schematic cross-sectional view respectively illustrating a power device according to an embodiment of the invention.

Fig. 3A and 3B are a schematic top view and a schematic cross-sectional view respectively illustrating a power device according to another embodiment of the invention.

Fig. 4A-4L are schematic cross-sectional views illustrating a method for manufacturing a power device according to an embodiment of the invention.

Description of the symbols in the drawings

11, 21, 31: substrate

12, 22, 32: well region

12a,22a,32a: drift region

13: insulation structure

13a: operating area

16, 26, 36: body region

17, 27, 37: grid electrode

18, 28, 38: source electrode

19, 29, 39: drain electrode

21',31': semiconductor layer

21a,31a: upper surface of

21b,31b: lower surface

23, 33: field oxide region

25, 35: self-aligned drift region

33': oxide layer

34: shielding

34': shielding material

36',38': the photoresist layer

37': field plate

100, 200, 300: power element

271, 371, 371': dielectric layer

272, 372, 372': conductive layer

273, 373, 373': spacer layer

Detailed Description

The foregoing and other technical and other features and advantages of the invention will be apparent from the following detailed description of preferred embodiments, read in conjunction with the accompanying drawings. The drawings in the present invention are schematic and are intended to show the process steps and the up-down order of the layers, and the shapes, thicknesses and widths are not drawn to scale.

Please refer to fig. 2A and fig. 2B, which respectively show a top view and a cross-sectional view of a power device 200 according to an embodiment of the invention. FIG. 2B shows a schematic cross-sectional view of the BB' cut line of FIG. 2A. As shown in fig. 2A and 2B, the power device 200 includes: semiconductor layer 21', well region 22, field oxide region 23, self-aligned drift region 25, body region 26, gate 27, source 28, and drain 29. A semiconductor layer 21' is formed on the substrate 21; the well region 22, the self-aligned drift region 25, the source 28 and the drain 29 have a first conductivity type; body region 26 has a second conductivity type. The power device 200 is, for example, a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) device as shown in fig. 2A and 2B. The power device according to the present invention is applied to a power stage circuit in a switching power supply circuit, which is well known to those skilled in the art and will not be described herein.

A semiconductor layer 21 'is formed on the substrate 21, and the semiconductor layer 21' has an upper surface 21a and a lower surface 21B opposite to each other in a vertical direction (as indicated by a dotted arrow in fig. 2B, the same applies hereinafter). The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 21 'is formed on the substrate 21, for example, by an epitaxial process, or a portion of the substrate 21 is used as the semiconductor layer 21'. The manner of forming the semiconductor layer 21' is well known to those skilled in the art and will not be described herein.

With continued reference to fig. 2A and 2B, the well 22 of the first conductivity type is formed in the semiconductor layer 21', and the well 22 is located under the upper surface 21a and connected to the upper surface 21a. Body region 26 of the second conductivity type is formed in semiconductor layer 22, and body region 26 is located under upper surface 21a and connected to upper surface 21a, and body region 26 is adjacent to well region 22 in the channel direction (as indicated by the solid arrow in fig. 2B, the same below). A gate 27 is formed on the upper surface 21a, a portion of the body region 26 is located directly under the gate 27 and connected to the gate 27 to provide an inversion current path for the power device 200 in the turn-on operation, and a portion of the well region 22 is located directly under the gate 27 to provide a drift current path for the power device 200 in the turn-on operation (as indicated by the thick dashed box in fig. 2B). The source 28 and the drain 29 have the first conductivity type, the source 28 and the drain 29 are formed under the upper surface 21a and connected to the upper surface 21a, and the source 28 and the drain 29 are respectively located in the body region 26 under the outer portion of the gate 27 and in the well region 22 at the side far from the body region 26.

A field oxide region 23 is formed on the upper surface 21a, and the field oxide region 23 is between the gate 27 and the drain 29. In one embodiment, the field oxide region 23 is formed by a Chemical Mechanical Polishing (CMP) process step. The self-aligned drift region 25 has a first conductivity type and is formed in the semiconductor layer 21'. The self-aligned drift region 25 is located entirely and connected directly below the field oxide region 23.

The self-aligned drift region 25 and the field oxide region 23 are defined by using the same mask in the same photolithography process. In one embodiment, the self-aligned drift region 25 has a lower first-conductivity-type impurity concentration than the drain 29, and the self-aligned drift region 25 has a higher first-conductivity-type impurity concentration than the well 22.

The gate 27 includes a dielectric layer 271 connected to the upper surface 21a, a conductive layer 272 having conductivity, and a spacer layer 273 having an electrical insulating property. The gate 27 is used for turning on and off the power device 200 under the control of the control signal.

With reference to fig. 2B, in the channel direction, the drift region 22a is located between the drain 29 and the body region 26, separates the drain 29 and the body region 26, and is located in the well region 22 near the upper surface 21a for serving as a drift current channel of the power device 200 in the on operation.

It should be noted that the inversion current channel refers to a region where an inversion layer (inversion layer) is formed below the gate 27 to pass an on current due to a voltage applied to the gate 27 during the on operation of the power device 200, which is well known to those skilled in the art and will not be described herein.

It should be noted that the drift current channel refers to a region through which the on current passes in a drift manner during the on operation of the power device 200, which is well known to those skilled in the art and is not described herein again.

Note that the upper surface 21a does not mean a completely flat plane, but means a surface of the semiconductor layer 21'.

The first conductivity type and the second conductivity type are different conductivity type impurities doped in the semiconductor composition region (such as, but not limited to, the well region, the body region, the source and the drain) in the power device, so that the semiconductor composition region has the first or the second conductivity type (such as, but not limited to, the first conductivity type is N type, and the second conductivity type is P type, or vice versa), wherein the first conductivity type and the second conductivity type are opposite conductivity types.

It should be noted that the power device is configured such that the voltage applied to the drain during normal operation is higher than a specific voltage, for example, 5V, and the lateral distance (drift length) between the body region 26 and the drain 29 is adjusted according to the operation voltage applied during normal operation, so that the power device can operate at the higher specific voltage. This is well known to those skilled in the art and will not be described in detail herein.

Please refer to fig. 3A and fig. 3B, which respectively show a top view and a cross-sectional view of a power device 300 according to another embodiment of the invention. FIG. 3B shows a schematic cross-sectional view of the CC' cut line of FIG. 3A. As shown in fig. 3A and 3B, the power device 300 includes: semiconductor layer 31', well region 32, field oxide region 33, self-aligned drift region 35, body region 36, gate 37, field plate 37', source 38, and drain 39. The well region 32, the self-aligned drift region 35, the source 38 and the drain 39 have a first conductivity type; the body regions 36 have a second conductivity type.

Referring to fig. 3A and fig. 3B, the power device 300 of the present embodiment is different from the embodiment of fig. 2B in that the power device includes a field plate 37 'having conductivity, and the field plate 37' is formed on the field oxide region 33 and connected to the field oxide region 33. The field plate 37' is electrically connected to a predetermined potential to relax the electric field distribution of the power device 300 during operation. In a preferred embodiment, the field plate 37' is electrically connected to the source 38. In one embodiment, the field plate 37' may be formed using the same process steps as the gate 37. In this embodiment, as shown in fig. 3B, the field plate 37 'includes a dielectric layer 371' connected to the upper surface 31a, a conductive layer 372 'having conductivity, and a spacer layer 373' having electrical insulation property. In another embodiment, the field plate 37' may also be a metal silicide layer or a metal layer formed by other metal silicide process steps or metal process steps.

Please refer to fig. 4A-4L, which are schematic cross-sectional views illustrating a method for manufacturing a power device according to an embodiment of the invention. As shown in fig. 4A, a substrate 31 is first provided, and the substrate 31 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. Next, as shown in fig. 4B, a semiconductor layer 31 'is formed on the substrate 31, wherein the semiconductor layer 31' has an upper surface 31a and a lower surface 31B opposite to each other in a vertical direction (as indicated by a dotted arrow in fig. 4B, the same applies below). The semiconductor layer 31 'is formed on the substrate 31, or a portion of the substrate 31 is used as the semiconductor layer 31', for example, by an epitaxial process. The manner of forming the semiconductor layer 31' is well known to those skilled in the art and will not be described herein.

Continuing with fig. 4B, a well region 32 is formed in the semiconductor layer 31', and the well region 32 is located under the upper surface 31a and connected to the upper surface 31a in the vertical direction. The well region 32 has a first conductivity type, and impurities of the first conductivity type can be implanted into the semiconductor layer 31' in the form of accelerated ions, as indicated by the downward dashed arrow in fig. 4B, for example, but not limited to, an ion implantation process step to form the well region 32.

Next, referring to fig. 4C, a body region 36 is formed in the semiconductor layer 31', wherein the body region 36 is located under the upper surface 31a and connected to the upper surface 31a, and the body region 36 is adjacent to the well region 32 in the channel direction (as indicated by the arrow of the solid line in fig. 4C, the same applies below). A portion of the body region 36 is located directly below the subsequently formed gate 37 and connected to the gate 37 to provide a reverse current path for the power element 300 in the turn-on operation. The body region 36 has a second conductivity type, and the step of forming the body region 36, such as but not limited to, using a photoresist layer 36 'formed by a photolithography process as a mask, dopants of the second conductivity type into the well region 32 of the semiconductor layer 31', and counter-doping (counter-doping) a defined portion from the well region 32 to form the body region 36. In this embodiment, for example, but not limited to, an ion implantation process may be performed to implant the second conductive type impurity into a portion of the well region 32 in the form of accelerated ions to form the body region 36.

Next, referring to fig. 4D, a mask material 34 'is formed on the upper surface 31a of the semiconductor layer 31' by, for example, a deposition process step to cover the entire upper surface 31a. In one embodiment, the masking material 34' is, for example, but not limited to, silicon nitride (SiN). Next, referring to fig. 4E, a photoresist layer 38 'is formed on the mask material 34' by, for example, a photolithography process. Next, referring to fig. 4F, a portion of the masking material 34 'not covered by the photoresist layer 38' is removed by, for example, an etching process step, such that the remaining masking material serves as the mask 34. A shield 34 is formed on the upper surface 31a and connected to the upper surface 31a, and the shield 34 defines a field oxide region 33 and a self-aligned drift region 35. It should be noted that the shield 34 covers the entire upper surface 31a of the low voltage region, and only in the high voltage region will the upper surface 31a be exposed as shown in fig. 4F.

Thereafter, referring to fig. 4G, a self-aligned drift region 35 is formed in the semiconductor layer 31'. The self-aligned drift region 35 is located entirely directly below and connected to the subsequently formed field oxide region 33. The self-aligned drift region 35 has a first conductivity type, and for example, a first conductivity type impurity may be implanted into the region defined by the shield 34, for example, but not limited to, by an ion implantation process step, in the form of accelerated ions, as indicated by the downward dashed arrow in fig. 4G, to form the self-aligned drift region 35. In one embodiment, the first conductive type impurity concentration of the self-aligned drift region 35 is lower than that of the drain 39, and the first conductive type impurity concentration of the self-aligned drift region 35 is higher than that of the well region 32.

Referring to fig. 4H, after removing the photoresist layer 38', an oxide layer 33' is formed on the mask 34 by, for example, a deposition process.

Next, referring to fig. 4I, the oxide layer 33' outside the region defined by the mask 34 is removed by a CMP process step to form a field oxide region 33 on the upper surface 31a. A field oxide region 33 is interposed between a subsequently formed gate 37 and drain 39.

Then, referring to fig. 4J, the mask 34 is removed. Next, referring to fig. 4K, a gate electrode 37 is formed on the upper surface 31a of the semiconductor layer 31', and a field plate 37' is formed on the field oxide region 33. Wherein a portion of the body region 36 is located directly under the gate 37 and connected to the gate 37 to provide a reverse current path for the power device 300 in the on operation. A portion of the well region 32 is located directly under the gate 37 to provide a drift current path for the power element 300 in the on operation. The field plate 37 'is connected to the field oxide region 33, and the field plate 37' has conductivity. The field plate 37' is electrically connected to a predetermined potential to relax the electric field distribution of the power device 300 during operation. The field plate 37' is electrically connected to a subsequently formed source 38.

In the present embodiment, the field plate 37' can be formed simultaneously by the same process steps as the gate 37. In this embodiment, as shown in fig. 4K, the field plate 37 'includes a dielectric layer 371' connected to the upper surface 31a, a conductive layer 372 'having conductivity, and a spacer layer 373' having electrical insulation property. In another embodiment, the field plate 37' may also be a metal silicide layer or a metal layer formed by other metal silicide process steps or metal process steps.

As shown in fig. 4K, the gate 37 includes a dielectric layer 371 connected to the upper surface 31a, a conductive layer 372 having conductivity, and a spacer layer 373 having electrical insulation property. The gate 37 is controlled by a control signal to turn on and off the power device 300.

With reference to fig. 4L, a source 38 and a drain 39 are formed under the upper surface 31a and connected to the upper surface 31a, and the source 38 and the drain 39 are respectively located in the body region 36 under the gate 37 outside the channel direction and in the well region 32 far from the body region 36 side, and in the channel direction, the drift region 32a is located between the drain 39 and the body region 36 and in the well region 32 near the upper surface 31a for serving as a drift current channel of the power device 300 in the on operation. The source 38 and drain 39 are formed by doping impurities of the first conductivity type into the body region 36 and the well region 32, respectively, using, for example, but not limited to, the gate 37, the field plate 37', the field oxide region 33, and a photoresist layer formed by a photolithography process as a mask to form the source 38 and drain 39. In this embodiment, for example, but not limited to, ion implantation process steps may be used to implant the first conductive type impurities into the body region 36 and the well region 32 in the form of accelerated ions to form the source 38 and the drain 39.

As described above, the present invention provides a power device 300 having a field oxide region 33 and a self-aligned drift region 35 and a method for fabricating the same, which can protect a low voltage region by covering the entire low voltage region with a shield and exposing only an upper surface of the high voltage region, prevent an insulating structure from being etched by the shield, simultaneously form a self-aligned drift region and a field oxide region with only a single shield, reduce an influence of a heating process on the low voltage region by a CMP process step instead of the heating process step, and make the high voltage region have a gradual first conductive type impurity concentration by the self-aligned drift region.

The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. Equivalent variations will occur to those skilled in the art, within the same spirit of the invention. For example, other process steps or structures, such as silicide layers, may be added without affecting the main characteristics of the device; for example, the lithography technique is not limited to the mask technique, but may include electron beam lithography. All of which can be analogized to the teachings of the present invention. Further, the embodiments described are not limited to the single application, and may be combined, for example, but not limited to, a combination of both embodiments. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above. Furthermore, it is not necessary for any embodiment of the invention to achieve all of the objects or advantages, and thus, any one of the claims should not be limited thereby.

Claims (10)

1. A power device, comprising:

a semiconductor layer formed on a substrate, the semiconductor layer having an upper surface;

a well region of a first conductivity type formed in the semiconductor layer, the well region being located below the upper surface and connected to the upper surface;

a body region of a second conductivity type formed in the semiconductor layer, the body region being located below and connected to the upper surface, the body region being located adjacent to the well region in a channel direction;

a gate formed on the upper surface, wherein a portion of the body region is located right under the gate and connected to the gate to provide an inversion current channel of the power device in a conducting operation, and a portion of the well region is located right under the gate to provide a drift current channel of the power device in the conducting operation;

a source and a drain of the first conductivity type, the source and the drain being formed under and connected to the upper surface and respectively located in the body region under the outside of the gate and in the well region away from the body region side;

a field oxide region formed on the upper surface and between the gate and the drain, the field oxide region being formed by a chemical mechanical polishing process; and

and a self-aligned drift region of the first conductivity type formed in the semiconductor layer and completely located and connected to the right under the field oxide region.

2. The power device of claim 1, further comprising a field plate having conductivity, wherein the field plate is formed on and connected to the field oxide region, and the field plate is electrically connected to a predetermined potential to mitigate electric field distribution during operation of the power device.

3. The power device of claim 1, wherein a first conductive type impurity concentration of the self-aligned drift region is lower than a first conductive type impurity concentration of the drain, and the first conductive type impurity concentration of the self-aligned drift region is higher than a first conductive type impurity concentration of the well region.

4. The power device of claim 1, wherein said self-aligned drift region and said field oxide region are defined by the same lithography process step.

5. The power device of claim 2, wherein the field plate is electrically connected to the source.

6. A method for manufacturing a power device, comprising:

forming a semiconductor layer on a substrate, the semiconductor layer having an upper surface;

forming a well region in the semiconductor layer, wherein the well region has a first conductivity type and is located below and connected to the upper surface;

forming a body region in the semiconductor layer, the body region having a second conductivity type, the body region being located below and connected to the upper surface, the body region being adjacent to the well region in a channel direction;

forming a gate on the upper surface, wherein part of the body region is located right below the gate and connected to the gate to provide an inversion current channel of the power device in a conducting operation, and part of the well region is located right below the gate to provide a drift current channel of the power device in the conducting operation;

forming a source and a drain under the upper surface and connected to the upper surface, the source and the drain having the first conductivity type and being located in the body region under the outside of the gate and the well region away from the body region side, respectively;

forming a field oxide region on the upper surface by a chemical mechanical polishing process, wherein the field oxide region is arranged between the grid and the drain; and

forming a self-aligned drift region in the semiconductor layer, wherein the self-aligned drift region has the first conductivity type and is completely located and connected right below the field oxide region.

7. The power element manufacturing method according to claim 6, further comprising:

forming a shield on the upper surface and connected to the upper surface by a lithography process step, wherein the shield defines the field oxide region and the self-aligned drift region;

implanting the first conductive type impurity into the region defined by the shield in the form of accelerated ions by an ion implantation process step to form the self-aligned drift region;

depositing an oxide layer by a deposition process step, and removing the oxide layer outside the region defined by the mask by a chemical mechanical polishing process step; and

the shield is removed.

8. The method according to claim 6, further comprising forming a field plate on and connected to the field oxide region, wherein the field plate is conductive and electrically connected to a predetermined potential to mitigate electric field distribution during operation of the power device.

9. The method according to claim 6, wherein the self-aligned drift region has a lower concentration of impurities of the first conductivity type than the drain, and the self-aligned drift region has a higher concentration of impurities of the first conductivity type than the well.

10. The method according to claim 8, wherein the field plate is electrically connected to the source electrode.

Images