CN111696984B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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CN111696984B
CN111696984B CN202010516053.4A CN202010516053A CN111696984B CN 111696984 B CN111696984 B CN 111696984B CN 202010516053 A CN202010516053 A CN 202010516053A CN 111696984 B CN111696984 B CN 111696984B
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well region
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CN111696984A (en
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韩广涛
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Joulwatt Technology Co Ltd
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Joulwatt Technology Co Ltd
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
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    • H01L27/0722—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/8248—Combination of bipolar and field-effect technology
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
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Abstract

A deep well region is manufactured on a substrate, a first well region, a second well region, a third well region and a fourth well region which are of two types of conductivity types are manufactured on the upper surface of the deep well region by adopting two photoetching plates, a buried layer which is connected with the first well region and the third well region and surrounds the second well region is manufactured in the deep well region, the first well region and the fourth well region and the doped region therein form source and drain, a DEMOS device is formed, the first well region, the buried layer and the third well region are doped of the second conductivity type, the second well region and the deep well region which are doped with the first conductivity type separated by the first well region and the third well region form a parasitic JFET device, the parasitic JFET device can improve the withstand voltage of the DEMOS device, and the higher withstand voltage expansion of the DEMOS device is realized.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
BCD (Bipolar-CMOS-DMOS) technology is an integrated process technology that enables Bipolar, CMOS (Complementary Metal Oxide Semiconductor ) and DMOS (double-dif-fused MOSFET) devices to be integrated simultaneously on a single chip.
In the conventional high-voltage BCD process, MOS (Metal Oxide Semiconductor ) devices with different voltage rules are provided, including a low-voltage CMOS device, a DEMOS (demain-extended MOS) device, and a high-voltage LDMOS (Lateral double diffusion MOS, lateral double-diffused metal oxide semiconductor field effect transistor), where a certain voltage resistance can be extended in the low-voltage CMOS to realize an extended design of the DEMOS.
With the development of technology, a higher pressure-resistant DEMOS is required, a photolithography mask is increased according to the expansion requirement of a traditional BCD process, and the photolithography mask corresponds to the production cost, so that the expansion of the higher pressure-resistant DEMOS of the traditional BCD process increases the process cost, and further the cost of a single chip is increased.
Disclosure of Invention
In view of the foregoing, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can realize higher withstand voltage extension of DEMOS while controlling the number of photolithography steps.
According to an aspect of the present invention, there is provided a semiconductor device characterized by comprising:
a substrate;
a deep well region on the substrate doped with a first conductivity type;
the first well region, the second well region, the third well region and the fourth well region are sequentially and linearly arranged on the upper surface of the deep well region, the first well region and the third well region are doped with the second conductivity type, and the second well region and the fourth well region are doped with the first conductivity type;
a buried layer, located in the deep well region, doped with a second conductivity type, connected to the first well region and the third well region, and surrounding the second well region with the first well region and the third well region;
the first doped region is positioned in the first well region and doped with the first conductivity type;
the second doping region is positioned in the second well region and doped with a second conductive type;
the third doped region is positioned in the fourth well region and doped with the first conductivity type;
the fourth doped region is positioned in the fourth well region and doped with the second conductive type, and the fourth doped region is far away from the first doped region than the third doped region;
a gate structure overlying the third well region and the fourth well region,
wherein the first doped region, the second doped region, the third doped region and the fourth doped region are all electrically led out.
Optionally, the first well region is a drift region.
Optionally, the third well region is a drift region.
Optionally, the deep well region is doped with N type, and the substrate is P type.
Optionally, the deep well region is P-type doped, and the substrate is an N-type substrate.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:
manufacturing a deep well region on a substrate, wherein the deep well region is doped with a first conductive type;
manufacturing a buried layer in the deep well region, wherein the buried layer is doped with a second conductive type;
a first well region, a second well region, a third well region and a fourth well region which are sequentially and linearly distributed are manufactured on the upper surface of the deep well region, the first well region and the third well region are doped with a second conductive type, and the second well region and the fourth well region are doped with a first conductive type;
a third doped region and a fourth doped region are manufactured on the upper surface of the fourth well region, the third doped region is closer to the second well region than the fourth doped region, the third doped region is doped with the second conductive type, and the fourth doped region is doped with the first conductive type;
manufacturing a second doped region on the upper surface of the second well region, wherein the second doped region is doped with a second conductive type;
manufacturing a first doped region on the upper surface of the first well region, wherein the first doped region is doped with a first conductive type;
manufacturing a grid structure on the third well region and the fourth well region;
in the step of manufacturing the first well region, the second well region, the third well region and the fourth well region, the well regions with the same doping type are manufactured by using the same photomask as a mask.
Optionally, the method further comprises:
after the first well region is manufactured, a drift region photomask is used as a mask to inject corresponding doped impurities into the first well region, so that the first well region is manufactured into a drift region.
Optionally, the method further comprises:
and after the third well region is manufactured, adopting a drift region photomask as a mask to inject corresponding doped impurities into the third well region so as to manufacture the third well region into the drift region.
Optionally, after the first well region and the third well region are manufactured, a drift region photomask is used as a mask, and corresponding doping impurities are injected into the first well region and the third well region at the same time, so that the first well region and the third well region are manufactured into drift regions.
Optionally, the first conductivity type doping is an N-type doping or a P-type doping, and the second conductivity type doping is opposite to the first conductivity type doping.
The semiconductor device provided by the invention comprises a first well region, a second well region, a third well region and a fourth well region, and four low-voltage well regions on the upper surface of a deep well region; the first well region and the third well region are connected with the buried layer, and the doping types of the first well region and the third well region are the same; the second well region is opposite to the buried layer in doping type, is positioned between the first well region and the third well region, and forms a JFET (junction field effect transistor) together with the deep well region; the fourth well region is positioned outside the first well region, the second well region and the third well region, and forms a DEMOS device with the first doped region, the third doped region, the fourth doped region and the grid structure in the deep well region, and the JFET device is parasitized in the DEMOS device, so that the withstand voltage value of the DEMOS device can be improved, and higher withstand voltage expansion of the DEMOS device is realized.
At least one of the first well region and the third well region is made into a drift region, the withstand voltage of the device can be further increased, and no additional cost of photolithography is increased compared with the prior art in which the drift region is made to increase the withstand voltage of the device.
The first well region, the fourth well region, the buried layer and the doped regions therein form a basic DEMOS device, the additionally arranged second well region, the additionally arranged third well region, the first well region and the fourth well region are low-voltage well regions, and in the manufacturing process, the well regions with the same doping type can use the same photomask in the manufacturing process of the DEMOS device, so that higher withstand voltage expansion of the DEMOS device can be realized under the condition of no consumption of additional photomasks.
The method for manufacturing the semiconductor device comprises the steps of manufacturing a first well region and a third well region with a second conductivity type and a second well region and a fourth well region with a first conductivity type on the upper surface of a deep well region by adopting two photoetching plates, wherein the first well region and the fourth well region are respectively etched by adopting two photoetching plates in the original BCD process, the conductivity types of the second well region and the third well region which are increased are the same as those of the fourth well region and the first well region respectively, the second well region and the third well region can be expanded by adopting the original quantity of photoetching plates for etching, the subsequent doped region is not increased in variety, namely the quantity of the non-photoetching plates is increased, namely the second well region and the third well region are expanded under the condition that the quantity of photoetching plates is not increased, the parasitic JFET device is expanded in a DEMOS device, and the high withstand voltage of the DEMOS device is improved.
And then adopting a photoetching plate to manufacture at least one of the first well region and the third well region as a drift region, so that the withstand voltage of the device can be further increased.
The method is applicable to N-type and P-type semiconductor devices simultaneously, has wide applicability, has opposite doping types of the deep well region and the substrate, and can ensure the withstand voltage of the deep well region and further ensure the withstand voltage of the device.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a flow chart of a conventional high voltage BCD process according to the prior art;
fig. 2 shows a schematic structure of a low voltage DEMOS device according to the prior art;
fig. 3 shows a schematic structural diagram of a DEMOS device according to the prior art;
fig. 4 shows a schematic structural diagram of a medium voltage PMOS device according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples.
Fig. 1 shows a flow chart of a conventional high voltage BCD process according to the prior art. As shown, the conventional high voltage BCD process sequentially includes:
step S01: a substrate is provided. I.e., a substrate having a thickness that matches the final desired semiconductor device, wherein the substrate may be a silicon substrate, and if a PMOS (positive Metal Oxide Semiconductor, P-type metal oxide semiconductor) device is used, the substrate may be a P-type silicon substrate.
Step S02: and manufacturing a deep well region. I.e. a deep well region is made on the substrate, which is used for high voltage resistance.
Step S03: and manufacturing an active region and a local silicon oxide isolation. The isolation layer comprises a plurality of isolation regions, wherein the regions between the isolation regions are active regions, and the active regions correspond to source drain well regions, source drain doped regions and the like in the subsequent manufacturing process.
Step S04: and (5) manufacturing a buried layer. According to the theory of reducing the surface electric field (RESURF), an impurity with the opposite doping type to the drift region is injected into the drift region of the LDMOS device, and the injected impurity forms the buried layer, so that the depletion of the drift region by the substrate can be matched, the surface electric field is reduced, the on-state voltage is reduced, and the withstand voltage of the device is improved. Specifically, the drift region of the corresponding N-type LDMOS is an N-type drift region, and the doping impurities of the corresponding buried layer are P-type doping impurities.
Step S05: and manufacturing an N well region and a P well region. And injecting corresponding doped impurities into the body regions corresponding to the N well region and the P well region by taking the isolation layer as a mask or adopting other masks to obtain the N well region and the P well region. An N-plate is used for the N-well region and a P-plate is used for the P-well region.
Step S06: and manufacturing a drift region. The traditional high-voltage BCD technology is added with a drift region photoetching plate, and the drift region photoetching plate corresponds to the drift region and is used for forming a low-concentration drift region, so that the withstand voltage of the device can be increased.
Step S07: and manufacturing a grid structure. The gate structure is positioned between the source end doping region and the drain end doping region, is generally in contact connection with the source end doping region, and is generally formed by growing a gate oxide layer and then depositing a polysilicon layer on the gate oxide layer.
Step S08: and manufacturing lightly doped drain and source drain regions. Lightly doped drain (Lightly Doped Drain, LDD) is used for defining source-drain expansion region of MOS device, LDD impurity is located under the grid structure and clings to the edge of channel region, so that impurity concentration gradient can be provided for source-drain region, and ohmic contact effect of source-drain grid is improved.
Step S09: cobalt silicide is formed. After the source drain gate is manufactured, the source drain gate needs to be electrically led out, a metal conductive wire can be generally manufactured, and cobalt silicide is formed at the connection part of the metal conductive wire and the source drain gate, so that the contact resistance of the connection part can be reduced, and good ohmic contact is obtained. Specifically, cobalt silicide may be selected from metal silicide such as cobalt silicide (cobalt silicide).
Step S10: and (5) a subsequent process. And a subsequent process flow is carried out, namely a plurality of layers of conductive metal wires are established, different metal wires can be connected by columnar metal, the material of the conductive metal wires can be copper generally, the electrical isolation between the conductive metal wires can be realized by an insulating layer, namely the columnar metal wires and the metal wires can be manufactured in the insulating layer, and corresponding through holes are arranged in the insulating layer to place the columnar metal wires and the metal wires.
Fig. 2 shows a schematic structure of a low voltage DEMOS device according to the prior art. As shown in the figure, the low voltage DEMOS device 100 includes a substrate 110, the substrate 110 includes a deep well region 120, the deep well region 120 includes a first well region 130 and a second well region 140 disposed side by side, the first well region 130 includes a drain doped region 131, the second well region 140 includes a first source doped region 141 and a second source doped region 142, an isolation layer 150 is disposed on the first well region 130 and the second well region 140, and a gate structure 160 is disposed on the first well region 130, the second well region 140 and the isolation layer 150. Drain terminal D is drawn from drain terminal doped region 131, source terminal S is drawn from first source terminal doped region 141, body region B is drawn from second source terminal doped region 142, and gate G is drawn from gate structure 160. In the low-voltage DEMOS device 100 of this example, the substrate 110 is a P-type silicon substrate, the deep well region 120 is a high-voltage N-type deep well region, the first well region 130 is a P-type well region, the second well region 140 is an N-type well region, the drain doped region 131 is a P-type doped, the first source doped region 141 is a P-type doped, the second source doped region 142 is an N-type doped, and the isolation layer 150 is typically made of silicon oxide.
In the low-voltage DEMOS device 100 of the present embodiment, the isolation layer 150 includes two isolation regions respectively located in the first well region 130 and the second well region 140, in the first well region 130, the drain doped region 131 is far away from the second well region 140 compared to the corresponding isolation region, and the beak part of the isolation region extends into the drain doped region 131; in the second well region 140, the first source doped region 141 is closer to the first well region 130 than the second source doped region 142, and is separated from each other by a corresponding isolation region, and a beak portion of the isolation region extends into the first source doped region 141 and the second source doped region 142, and one end of the gate structure 160 is in contact connection with the first source doped region 141.
Fig. 3 shows a schematic structure of a DEMOS device according to the prior art. As shown, the DEMOS device 200 includes a substrate 210, a deep well region 220 is included on the substrate 210, a drift region 230 and a well region 240 are disposed side by side on the deep well region 220, a drain doped region 231 is included in the drift region 230, a first source doped region 241 and a second source doped region 242 are included in the well region 240, an isolation layer 250 is disposed on the drift region 230 and the well region 240, and a gate structure 260 is disposed on the drift region 230, the well region 240 and the isolation layer 250. Drain terminal D is drawn from drain terminal doped region 231, source terminal S is drawn from first source terminal doped region 241, body region lead-out terminal B is drawn from second source terminal doped region 242, and gate G is drawn from gate structure 260. In the DEMOS device 200 of the present embodiment, the substrate 210 is a P-type silicon substrate, the deep well 220 is a high voltage N-type deep well, the drift region 230 is a P-type drift region, the well 240 is an N-type well, the drain doped region 231 is P-type doped, the first source doped region 241 is P-type doped, the second source doped region 242 is N-type doped, and the isolation layer 250 is typically made of silicon oxide.
In the low-voltage DEMOS device 200 of the present embodiment, the isolation layer 250 includes two isolation regions respectively located in the drift region 230 and the well region 240, in the drift region 230, the drain doped region 231 is far away from the well region 240 compared to the corresponding isolation region, and the beak portion of the isolation region extends into the drain doped region 231; in the well region 240, the first source doped region 241 is closer to the drift region 230 than the second source doped region 242, and is separated from each other by a corresponding isolation region, and a beak portion of the isolation region extends into the first source doped region 241 and the second source doped region 242, and one end of the gate structure 260 is in contact connection with the first source doped region 241.
In this embodiment, the DEMOS device 200 is provided with the drift region 230, compared with the first well region 130 at the same position of the low-voltage DEMOS device 100, the drift region 230 can improve the withstand voltage of the device, and the design of the HVMOS device can be realized by using the DEMOS device, but the process belongs to the BCD process, and in a chip, not only the DEMOS device 200 of the type is provided, but also other devices are integrated, so that a photolithography mask needs to be added in the process of manufacturing the drift region 230, so that other body regions of the chip are not affected in the process of manufacturing the drift region 230.
Fig. 4 shows a schematic structural diagram of a medium voltage PMOS device according to an embodiment of the invention. As shown in the drawing, the PMOS device 300 of the embodiment of the invention includes a P-type silicon substrate 310, a deep well region 320 is disposed on the P-type silicon substrate 310, a first P-well region 340, a first N-well region 350, a second P-well region 360 and a second N-well region 370 are sequentially disposed on the upper surface of the deep well region 320 in a linear manner, a P-type buried layer 330 is disposed on the lower surfaces of the first P-well region 340, the first N-well region 350 and the second P-well region 360 in a connected manner, a drain-end doped region 341 is disposed on the upper surface of the first P-well region 340, a body-region doped region 351 is disposed on the upper surface of the first N-well region 350, a first source-end doped region 371 and a second source-end doped region 372 are disposed on the upper surface of the second N-well region 370, and an isolation layer and a gate structure 390 is disposed on the deep well region 320, wherein the isolation layer includes an isolation region 381, an isolation region 382 and an isolation region 383. The drain terminal D is led out from the drain terminal doped region 341, the first body region led out terminal B1 is led out from the body region doped region 351, the source terminal S is led out from the first source terminal doped region 371, the second body region led out terminal B2 is led out from the second source terminal doped region 372, the first source terminal doped region 371 is closer to the gate structure 390 than the second source terminal doped region 372 and spaced apart from the second source terminal doped region 372, and the first source terminal doped region 371 is in contact connection with one end of the gate structure 390.
In the PMOS device 300 of the present embodiment, the deep well 320 is a high voltage N-type deep well, the drain doped region 341 is a P-type doped region, the body doped region 351 is an N-type doped region, the first source doped region 371 is a P-type doped region, and the second source doped region 372 is an N-type doped region.
In the PMOS device 300 of the present embodiment, the isolation region 381 of the isolation layer is located corresponding to the first P-well region 340 and the first N-well region 350, and is provided with a drain doped region 341 and a body doped region 351 at both ends thereof; the isolation region 382 corresponds to the first N-well region 350 and the second P-well region 360, with one end connected to the body region doped region 351 and the other end located in the second P-well region 360; an isolation region 383 is located in the second N-well region 370, isolating the first source-side doped region 371 and the second source-side doped region 372. Namely, the drain doped region 341, the body doped region 351, the first source doped region 371 and the second source doped region 372 are manufactured by using the isolation regions and the gate structures of the isolation layers as masks through alignment implantation.
The gate structure 390 covers the first source doped region 371 to the second P-well region 360 and covers the isolation region 382, and in this embodiment, the gate structure 390 extends toward the drain D and completely covers the second P-well region 360 but does not extend as far as the first N-well region 350 on the upper surface to ensure the extraction of the body doped region 351.
The P-type buried layer 330 connects the first P-well region 340 and the second P-well region 360 to form a forward path, the first N-well region 350 is interposed between the first P-well region 340 and the second P-well region 360, and is a low-voltage N-well region, the second N-well region 370 is a low-voltage N-well region, the deep well region 320 may be a high-voltage N-well region, that is, the low-voltage N-well region, the P-type buried layer and the high-voltage N-well region may form a parasitic MOS transistor having a JFET (Junction Field-Effect Transistor) performance, and the first P-well region 340 and the P-type buried layer 330 are low-voltage DEMOS devices with the second N-well region 370 and the deep well region 320, and the final withstand voltage of the PMOS device 300 is a pinch-off voltage of the parasitic JFET plus a breakdown voltage of DEMOS, and the breakdown voltage is improved.
The first body region leading-out terminal B1 is the gate of the JFET, the deep well region 320 is the other gate of the JFET, and the first P-well region 340, the buried layer 330, and the second P-well region 360 are the channels of the JFET.
The first P-well region 340, the first N-well region 350, the second P-well region 360 and the second N-well region 370 are common well regions, the doping concentrations of the well regions with the same doping type are the same, and the well regions with the same doping type of the chip can be manufactured by adopting a photomask together in the manufacturing process.
After the first P-well region 340 is fabricated, the first P-well region 340 is implanted with the corresponding doped impurities, so that the first P-well region 340 is fabricated into a drift region to increase the voltage endurance of the PMOS device, meanwhile, compared with the prior art shown in fig. 3, no additional photolithography is added, and the parasitic JFET is relied on to realize the expansion of higher voltage endurance at the same photolithography cost as the embodiment of fig. 3. The first P-well region 340 is fabricated as a drift region, which can increase the withstand voltage of the device, and similarly, the second P-well region 360 is fabricated as a drift region, which can also increase the withstand voltage of the device, and the drift region can be implanted by using the same block of drift region lithography patterned corresponding to the drift region as the first P-well region 340.
The manufacturing method of the semiconductor device of the present invention is different from the conventional high voltage BCD process shown in fig. 1 in that the present invention does not have step S06, more N-well regions and P-well regions are simultaneously manufactured in step S05, and more doped regions in the well regions are manufactured in step S08. Corresponding to the PMOS device 300 of the present embodiment, the first N-well region 350, the second P-well region 360 and the body region doped region 351 are additionally fabricated, and the number and the positions of the isolation regions of the corresponding isolation layers are adaptively adjusted, wherein the patterning pattern of the corresponding photolithography mask is adaptively adjusted, but no additional photolithography mask is consumed.
Taking the PMOS device 300 as an example, the main point of the present embodiment is that a parasitic JFET device is fabricated in a conventional DEMOS device, so that the voltage withstand value of the device is the voltage withstand value of the original DEMOS plus the pinch-off voltage of the parasitic JFET device, the voltage withstand of the DEMOS device is improved, and the high voltage withstand extension of the DEMOS device is realized, where the fabrication of the parasitic JFET device only requires the fabrication of more low-voltage N-well regions and low-voltage P-well regions, no drift region is required, and the additionally fabricated low-voltage N-well regions and low-voltage P-well regions are located at the same level as the low-voltage well regions of the original device, i.e., the same photomask can be used, and the well regions with the same doping type are simultaneously implanted for fabrication, and the difference is only that the patterned patterns of the photomasks are different, i.e., the number cost of the non-photomask is increased.
The semiconductor device and the manufacturing method thereof utilize the buried layer in the common DEMOS device, and simultaneously manufacture more low-voltage N well regions and low-voltage P well regions, so that the parasitic JFET device is manufactured under the condition that the number of photolithography plates is not increased, the withstand voltage of the device is improved, and the high withstand voltage expansion of the medium-voltage DEMOS device is realized under the condition that the cost of the number of photolithography plates is not increased.
Meanwhile, for the technical scheme of manufacturing the drift region to improve the withstand voltage of the device, the parasitic JFET can be expanded, and the withstand voltage of the device can be expanded without increasing the number cost of the photolithography mask, so that the design of a DEMOS device with higher withstand voltage is realized.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (10)

1. A semiconductor device, comprising:
a substrate;
a deep well region on the substrate doped with a first conductivity type;
the first well region, the second well region, the third well region and the fourth well region are sequentially and linearly arranged on the upper surface of the deep well region, the first well region and the third well region are doped with the second conductivity type, and the second well region and the fourth well region are doped with the first conductivity type;
a buried layer, located in the deep well region, doped with a second conductivity type, connected to the first well region and the third well region, and surrounding the second well region with the first well region and the third well region;
the first doping region is positioned in the first well region and doped with the second conductivity type;
the second doped region is positioned in the second well region and doped with the first conductivity type;
the third doped region is positioned in the fourth well region and doped with the second conductivity type;
the fourth doped region is positioned in the fourth well region and doped with the first conductive type, and the fourth doped region is far away from the first doped region than the third doped region;
a gate structure overlying the third well region and the fourth well region,
wherein the first doped region, the second doped region, the third doped region and the fourth doped region are all electrically led out.
2. The semiconductor device according to claim 1, wherein,
the first well region is a drift region.
3. The semiconductor device according to claim 1, wherein,
the third well region is a drift region.
4. The semiconductor device according to claim 1, wherein,
the deep well region is doped with N type, and the substrate is a P type substrate.
5. The semiconductor device according to claim 1, wherein,
the deep well region is doped with P type, and the substrate is an N type substrate.
6. A method of fabricating a semiconductor device, comprising:
manufacturing a deep well region on a substrate, wherein the deep well region is doped with a first conductive type;
manufacturing a buried layer in the deep well region, wherein the buried layer is doped with a second conductive type;
a first well region, a second well region, a third well region and a fourth well region which are sequentially and linearly distributed are manufactured on the upper surface of the deep well region, the first well region and the third well region are doped with a second conductive type, and the second well region and the fourth well region are doped with a first conductive type;
a third doped region and a fourth doped region are manufactured on the upper surface of the fourth well region, the third doped region is closer to the second well region than the fourth doped region, the third doped region is doped with the second conductive type, and the fourth doped region is doped with the first conductive type;
manufacturing a second doped region on the upper surface of the second well region, wherein the second doped region is doped with the first conductivity type;
manufacturing a first doped region on the upper surface of the first well region, wherein the first doped region is doped with a second conductive type;
manufacturing a grid structure on the third well region and the fourth well region;
in the step of manufacturing the first well region, the second well region, the third well region and the fourth well region, the well regions with the same doping type are manufactured by using the same photomask as a mask.
7. The method for manufacturing a semiconductor device according to claim 6, further comprising:
after the first well region is manufactured, a drift region photomask is used as a mask to inject corresponding doped impurities into the first well region, so that the first well region is manufactured into a drift region.
8. The method for manufacturing a semiconductor device according to claim 6, further comprising:
and after the third well region is manufactured, adopting a drift region photomask as a mask to inject corresponding doped impurities into the third well region so as to manufacture the third well region into the drift region.
9. The method for manufacturing a semiconductor device according to claim 6, wherein,
after the first well region and the third well region are manufactured, a drift region photomask is adopted as a mask, and corresponding doped impurities are injected into the first well region and the third well region at the same time so as to manufacture the first well region and the third well region into the drift region.
10. The method for manufacturing a semiconductor device according to claim 6, wherein,
the first conductivity type doping is either an N-type doping or a P-type doping, and the second conductivity type doping is opposite to the first conductivity type doping.
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