CN101819997A - LDMOS device capable of improving rebound performance and manufacturing method thereof - Google Patents
LDMOS device capable of improving rebound performance and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses an LDMOS device capable of improving rebound performance and a manufacturing method thereof. In the prior art, the LDMOS device has poor rebound performance because a low doping concentration of a high-voltage trap needs to be maintained to ensure that the LDMOS device has a high breakdown voltage. The LDMOS device capable of improving the rebound performance of the invention comprises a silicon substrate, a high-voltage trap, a source, a source drift region, a drain, a drain drift region, a gate and a side wall thereof; the LDMOS device also comprises a relieving block which is arranged in the high-voltage trap and is adjacent to the source drift region; and the relieving block has the same doping type as the high-voltage trap and has a higher impurity concentration than the high-voltage trap. Due to the arrangement of the relieving block, the LDMOS device can effectively reduce the base resistance of a parasitic BJT in the LDMOS device without changing the impurity concentration of the high-voltage trap, thereby effectively improving the maximum working voltage of the LDMOS device and improving the rebound performance of the LDMOS device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of LDMOS device and manufacture method thereof of improving rebound performance.
Background technology
Power MOS pipe is used very extensive in power electronic equipment, and it is the majority carrier conduction when forward bias is worked, and is regarded as the device that does not have second breakdown usually.But power MOS pipe has a parasitic bipolar transistor (BJT), and the collector and emitter of parasitic BJT also is the drain electrode and the source electrode of metal-oxide-semiconductor simultaneously.When the power MOS pipe drain electrode exists big drain current Id and high drain voltage Vd, device internal ionization effect aggravation, a large amount of hole currents appears, base resistance Rb through parasitic BJT flows into its source electrode, cause the base potential Vb of parasitic BJT to raise, so-called rebound (Snapback) phenomenon appears, promptly when Vb is elevated to a certain degree, parasitic BJT conducting, puncture voltage when its collector electrode (be power MOS pipe drain electrode) voltage fast return reaches parasitic BJT open base, parasitic BJT conducting makes power MOS pipe carry out the transition to the low-voltage, high-current state rapidly by the little electric current of high voltage.
Now Chang Yong power MOS pipe is LDMOS transistor (LateralDiffused Medal Oxide Semiconductor; Be called for short LDMOS), it is easier to be widely adopted with the CMOS process compatible.The LDMOS device architecture as shown in Figure 1, the LDMOS device comprises silicon substrate 10, high pressure trap 11, source electrode 12, source electrode drift region 13, grid 14, grid curb wall 15, drain electrode 16 and drain-drift region 17, this high pressure trap 11 is formed in this silicon substrate 10, this source electrode drift region 13 and drain-drift region 17 are formed in this high pressure trap 11 and are arranged in grid 14 both sides, and this source electrode 12 and drain electrode 16 are respectively formed in this source electrode drift region 13 and the drain-drift region 17.This source electrode 12 and drain electrode 16 are isolated with grid 14 by the nearly gate groove isolation structure 20 and 21 that is arranged on source electrode drift region 13 and drain-drift region 17 respectively, and respectively by being arranged on away from the gate groove isolation structure 22 far away of grid 14 1 sides and 23 and 11 isolation of high pressure trap.
In LDMOS device as shown in Figure 1, its high pressure trap 11, source electrode drift region 13 and drain-drift region 17 are respectively base stage, the emitter and collector of parasitic BJT; Prior art is to guarantee that the LDMOS device has higher puncture voltage, and the doping content of its high pressure trap 11 is lower, so can cause the base resistance Rb of parasitic BJT bigger; And between parasitic BJT base emitter-base bandgap grading voltage U be equal base resistance Rb and base current Ib long-pending, voltage U be is steady state value 0.7V between the basic emitter-base bandgap grading of silicon materials, when voltage U be is greater than 0.7V between basic emitter-base bandgap grading, parasitic BJT opens and makes the LDMOS device out of control, cause the LDMOS device rebound phenomenon just to occur and rebound performance is not good, and then reduced the maximum operating voltage of LDMOS device at the low voltage place.
Referring to Fig. 2, it has shown the Id-Vd graph of relation of n raceway groove LDMOS device when Vg equals 35V in the prior art, as shown in the figure, curve L1 is the relation curve of Id-Vd, from curve L1 as can be seen the Id of LDMOS device increase along with the increase of Vd from the starting stage, when Vd is increased to the 50V left and right sides, thereby rebound phenomenon takes place in the parasitic BJT conducting of LDMOS device correspondence, the LDMOS device just knock-ons at lower drain voltage place in the prior art, causes rebound performance not good.
Therefore, how to provide a kind of LDMOS device that improves rebound performance and manufacture method thereof improving the rebound performance of device, and effectively improve the maximum operating voltage of LDMOS device, become the technical problem that industry needs to be resolved hurrily.
Summary of the invention
The object of the present invention is to provide a kind of LDMOS device and manufacture method thereof of improving rebound performance, can effectively improve the rebound performance of LDMOS device, and can improve the maximum operating voltage of LDMOS device by described Apparatus and method for.
The object of the present invention is achieved like this: a kind of LDMOS device that improves rebound performance, comprise silicon substrate, the high pressure trap, source electrode, the source electrode drift region, drain electrode, drain-drift region, grid and side wall thereof, this high pressure trap is formed in this silicon substrate, this source electrode drift region and drain-drift region are formed in this high pressure trap and are arranged in the grid both sides, this source electrode and drain electrode are respectively formed in this source electrode drift region and the drain-drift region, this LDMOS device also comprises the relieving block that is arranged in the high pressure trap and adjoins the source electrode drift region, and this relieving block and its impurity concentration identical with high pressure trap doping type is higher than this high pressure trap.
In the LDMOS of above-mentioned improved rebound performance device, this source electrode and drain electrode be respectively by being arranged on the nearly gate groove isolation structure and the gate isolation of source electrode drift region and drain-drift region, and respectively by being arranged on the gate groove isolation structure far away and the isolation of high pressure trap away from grid one side.
In the LDMOS of above-mentioned improved rebound performance device, this LDMOS device is a N raceway groove LDMOS device, and the doping type of this silicon substrate, high pressure trap, source electrode, source electrode drift region, grid, drain electrode, drain-drift region and relieving block is respectively P type, P type, the heavy doping of N type, N type light dope, the heavy doping of N type, the heavy doping of N type, N type light dope and P type.
In the LDMOS of above-mentioned improved rebound performance device, this LDMOS device is a P raceway groove LDMOS device, and the doping type of this silicon substrate, high pressure trap, source electrode, source electrode drift region, grid, drain electrode, drain-drift region and relieving block is respectively P type, N type, the heavy doping of P type, P type light dope, the heavy doping of P type, the heavy doping of P type, P type light dope and N type.
The present invention also provides a kind of above-mentioned manufacture method of improving the LDMOS device of rebound performance, may further comprise the steps: a, provide a silicon substrate; B, carry out ion implantation technology and annealing process and form the high pressure trap at this silicon substrate; C, carry out ion implantation technology and annealing process and form source electrode drift region and drain-drift region at this high pressure trap; D, on the high pressure trap, make grid and side wall thereof; E, carry out ion implantation technology and annealing process and form source electrode and drain electrode in source electrode drift region and drain-drift region respectively; Also have step c1 between step c and the d: carry out ion implantation technology and annealing process in the high pressure trap and adjoin the source electrode drift region and form relieving block, the implanted dopant type of the ion implantation technology among this step c1 and the step b is identical.
In the manufacture method of the LDMOS of above-mentioned improved rebound performance device, the ion implantation technology that forms high pressure trap, source electrode, source electrode drift region, grid, drain electrode, drain-drift region and relieving block is respectively P type, the heavy doping of N type, N type light dope, the heavy doping of N type, the heavy doping of N type, N type light dope and P type ion implantation technology, wherein, the implanted dopant that forms the ion implantation technology of relieving block is a boron, the injection energy is 1200kev, and implantation dosage is 1 * 10
13Cm
-2
In the manufacture method of the LDMOS of above-mentioned improved rebound performance device, the ion implantation technology that forms high pressure trap, source electrode, source electrode drift region, grid, drain electrode, drain-drift region and relieving block is respectively N type, the heavy doping of P type, P type light dope, the heavy doping of P type, the heavy doping of P type, P type light dope and N type ion implantation technology.
In the manufacture method of the LDMOS of above-mentioned improved rebound performance device, this method also has between step b and c in high pressure trap area of grid both sides makes nearly gate groove isolation structure respectively, and the step of making gate groove isolation structure far away respectively in source electrode and both sides, drain region.
Cause the LDMOS device rebound phenomenon just to take place when the less drain voltage comparing with the doping content of prior art mesohigh trap is low, LDMOS device that improves rebound performance of the present invention and manufacture method thereof by ion implantation technology and annealing process in the high pressure trap and adjoin the source electrode drift region and form relieving block, thereby effectively reduce the base resistance Rb of parasitic BJT, effectively improve parasitic BJT and opened LDMOS device drain voltage when producing rebound phenomenon, thereby improved rebound performance, and effectively improved the maximum operating voltage of LDMOS device.
Description of drawings
LDMOS device and the manufacture method thereof of improving rebound performance of the present invention provided by following embodiment and accompanying drawing.
Fig. 1 is the composition structural representation of LDMOS device in the prior art;
Fig. 2 is the Id-Vd graph of relation of n raceway groove LDMOS device when Vg equals 35V in the prior art;
Fig. 3 is the composition structural representation that improves the LDMOS device of rebound performance of the present invention;
Fig. 4 is prior art and the Id-Vd relation curve comparison diagram of n raceway groove LDMOS device of the present invention when Vg equals 35V;
Fig. 5 is the flow chart that improves the LDMOS device making method of rebound performance of the present invention;
Fig. 6 to Figure 10 is respectively and finishes among Fig. 5 the composition structural representation of LDMOS device behind the step S51 to S55.
Embodiment
Below will be described in further detail LDMOS device and the manufacture method thereof of improving rebound performance of the present invention.
Referring to Fig. 3, the LDMOS device that improves rebound performance of the present invention comprises silicon substrate 10, high pressure trap 11, source electrode 12, source electrode drift region 13, grid 14, grid curb wall 15, drain electrode 16, drain-drift region 17, nearly gate groove isolation structure 20 and 21, gate groove isolation structure 22 far away and 23 and relieving block 3.Below will be elaborated to each member that improves the LDMOS device of rebound performance of the present invention.
Described high pressure trap 11 is formed in the described silicon substrate 10, described source electrode drift region 13 and drain-drift region 17 are formed in the described high pressure trap 11 and are arranged in grid 14 both sides, and described source electrode 12 and drain electrode 16 are respectively formed in described source electrode drift region 13 and the drain-drift region 17; Described source electrode 12 and drain electrode 16 are isolated with grid 14 by the nearly gate groove isolation structure 20 and 21 that is arranged on source electrode drift region 13 and drain-drift region 17 respectively, and respectively by being arranged on away from the gate groove isolation structure 22 far away of grid 14 1 sides and 23 and 11 isolation of high pressure trap; Relieving block 3 is arranged in the high pressure trap 11 and adjoins source electrode drift region 13, and described relieving block 3 and its impurity concentration identical with high pressure trap 11 doping types is higher than described high pressure trap 11.
In first embodiment of the LDMOS device that improves rebound performance of the present invention, described LDMOS device is a N raceway groove LDMOS device, and the doping type of described silicon substrate 10, high pressure trap 11, source electrode 12, source electrode drift region 13, grid 14, drain electrode 16, drain-drift region 17 and relieving block 18 is respectively P type, P type, the heavy doping of N type, N type light dope, the heavy doping of N type, the heavy doping of N type, N type light dope and P type; Wherein, the implanted dopant that forms the ion implantation technology of relieving block 3 is a boron, and the injection energy is 1200kev, and implantation dosage is 1 * 10
13Cm
-2, the vertical section of described relieving block 3 is a rectangle.
Referring to Fig. 4, it has shown the Id-Vd relation curve comparison diagram of N groove LDMOS device when Vg equals 35V in prior art and the first embodiment of the invention, as shown in the figure, curve L1 and L2 are respectively the Id-Vd relation curve of N groove LDMOS device when Vg equals 35V in prior art and the first embodiment of the invention, the Id of N groove LDMOS device of the present invention also increased along with the increase of Vd in the starting stage, when Vd was increased to the 54V left and right sides, the collision electric current in the N groove LDMOS device aggravated to open and produce rebound phenomenon to the parasitic BJT that makes its correspondence.Can contrast from curve L1 and L2 and to find out, the present invention by in high pressure trap 11 and the zone of adjoining source electrode drift region 13 relieving block 3 is set, thereby effectively the rebound starting resistor of LDMOS device is brought up to 54V from 50V of the prior art, the maximum operating voltage that has effectively improved the LDMOS device has also effectively improved the rebound performance of LDMOS device.
In second embodiment of the LDMOS device that improves rebound performance of the present invention, described LDMOS device is a P raceway groove LDMOS device, and the doping type of described silicon substrate 10, high pressure trap 11, source electrode 12, source electrode drift region 13, grid 14, drain electrode 16, drain-drift region 17 and relieving block 18 is respectively P type, N type, the heavy doping of P type, P type light dope, the heavy doping of P type, the heavy doping of P type, P type light dope and N type.
Referring to Fig. 5, it is the flow chart that improves the LDMOS device making method of rebound performance of the present invention, and as shown in the figure, the LDMOS device making method that improves rebound performance of the present invention at first carries out step S50, and a silicon substrate is provided.In first and second embodiment of the LDMOS device making method that improves rebound performance of the present invention, described silicon substrate is the P type.
Then continue step S51, carry out ion implantation technology and annealing process and form the high pressure trap at described silicon substrate.In first and second embodiment of the LDMOS device making method that improves rebound performance of the present invention, form high pressure trap 11 by P type ion implantation technology and N type ion implantation technology respectively, the annealing process of this step is for to carry out in the thermal diffusion boiler tube, annealing temperature is 900 to 1000 ℃, and annealing time is 20 to 30min.
Referring to Fig. 6, it has shown the composition structural representation of LDMOS device behind the completing steps S51, and as shown in the figure, high pressure trap 11 is formed in the silicon substrate 10.
Then continue step S52, make nearly gate groove isolation structure respectively, and make gate groove isolation structure far away respectively at source electrode and both sides, drain region in high pressure trap area of grid both sides.
Referring to Fig. 7, in conjunction with referring to Fig. 3 and Fig. 6, Fig. 7 has shown the composition structural representation of LDMOS device behind the completing steps S52, as shown in the figure, nearly gate groove isolation structure 20 and 21 is formed on high pressure trap 11 area of grid both sides, and gate groove isolation structure 22 and 23 far away is formed on source electrode and both sides, drain region.
Then continue step S53, carry out ion implantation technology and annealing process and form source electrode drift region and drain-drift region at described high pressure trap.In first embodiment of the LDMOS device making method that improves rebound performance of the present invention, by N type light dope ion implantation technology to form source electrode drift region and drain-drift region; In a second embodiment, form source electrode drift region and drain-drift region by P type light dope ion implantation technology.The annealing process of this step is for to carry out in the thermal diffusion boiler tube, and annealing temperature is 900 to 1000 ℃, and annealing time is 20 to 30min.
Referring to Fig. 8, in conjunction with referring to Fig. 6 and Fig. 7, Fig. 8 has shown the composition structural representation of completing steps S 53 back LDMOS devices, as shown in the figure, source electrode drift region 13 and drain-drift region 17 are formed in the high pressure trap 12 and cover nearly gate groove isolation structure 20 and 21 and gate groove isolation structure 22 and 23 far away.
Then continue step S54, carry out ion implantation technology and annealing process in the high pressure trap and adjoin the source electrode drift region and form relieving block.In first embodiment of the LDMOS device making method that improves rebound performance of the present invention, to form relieving block, implanted dopant is a boron by P type ion implantation technology, and the injection energy is 1200kev, and implantation dosage is 1 * 10
13Cm
-2In a second embodiment, form relieving block by N type ion implantation technology.The annealing process of this step is a rapid thermal anneal process, and annealing temperature is 900 to 1000 ℃, and annealing time is 5 to 10s.
Referring to Fig. 9, in conjunction with referring to Fig. 6 to Fig. 8, Fig. 9 has shown the composition structural representation of LDMOS device behind the completing steps S54, and as shown in the figure, relieving block 3 is formed in the high pressure trap 11 and adjoins source electrode drift region 13.
Then continue step S55, make grid and side wall thereof on the high pressure trap, its concrete steps are: at first deposit grid oxide layer and polysilicon layer, then carry out etching technics and form grid, and deposited oxide layer afterwards, last etching forms grid curb wall.In this step, also feed impurity gas in the time of the deposit spathic silicon layer polysilicon layer is carried out heavy doping, in first and second embodiment of the LDMOS device making method that improves rebound performance of the present invention, the impurity gas of feeding is respectively N type and P type impurity gas.
Referring to Figure 10, in conjunction with referring to Fig. 6 to Fig. 9, Figure 10 has shown the composition structural representation of LDMOS device behind the completing steps S55, as shown in the figure, grid 14 is deposited on the high pressure trap 11, grid curb wall 15 covers grid 14 both sides, and source electrode drift region 13 is formed in the high pressure trap 17 with drain-drift region 17 and is arranged in grid 14 both sides, and nearly gate groove isolation structure 20 and 21 is arranged in the area of grid both sides respectively and lays respectively in source electrode drift region 13 and the drain-drift region 17.
Then continue step S56, carry out ion implantation technology and annealing process and form source electrode and drain electrode in source electrode drift region and drain-drift region respectively.In first embodiment of the LDMOS device making method that improves rebound performance of the present invention, by N type heavy doping ion injection technology to form source electrode and drain electrode; In a second embodiment, by P type heavy doping ion injection technology to form source electrode and drain electrode.The annealing process of this step is rapid thermal annealing (RTP) technology, and annealing temperature is 900 to 1000 ℃, and annealing time is 5 to 10s.
The composition structural representation of LDMOS device as shown in Figure 3 behind the completing steps S56, grid 12 is arranged in source electrode drift region 13 and is positioned at nearly gate groove isolation structure 20 and 22 of gate groove isolation structures far away, and drain electrode 16 is arranged in drain-drift region 17 and is positioned at nearly gate groove isolation structure 21 and 23 of gate groove isolation structures far away.
In sum, LDMOS device that improves rebound performance of the present invention and manufacture method thereof by ion implantation technology and annealing process in the high pressure trap and adjoin the source electrode drift region and form relieving block, thereby effectively reduce the base resistance Rb of parasitic BJT, effectively improve parasitic BJT and opened LDMOS device drain voltage when producing rebound phenomenon, thereby improved rebound performance, and effectively improved the maximum operating voltage of LDMOS device.
Claims (9)
1. LDMOS device that can improve rebound performance, comprise silicon substrate, the high pressure trap, source electrode, the source electrode drift region, drain electrode, drain-drift region, grid and side wall thereof, this high pressure trap is formed in this silicon substrate, this source electrode drift region and drain-drift region are formed in this high pressure trap and are arranged in the grid both sides, this source electrode and drain electrode are respectively formed in this source electrode drift region and the drain-drift region, it is characterized in that, this LDMOS device also comprises the relieving block that is arranged in the high pressure trap and adjoins the source electrode drift region, and this relieving block and its impurity concentration identical with high pressure trap doping type is higher than this high pressure trap.
2. the LDMOS device that improves rebound performance as claimed in claim 1, it is characterized in that, this source electrode and drain electrode be respectively by being arranged on the nearly gate groove isolation structure and the gate isolation of source electrode drift region and drain-drift region, and respectively by being arranged on the gate groove isolation structure far away and the isolation of high pressure trap away from grid one side.
3. the LDMOS device that improves rebound performance as claimed in claim 1, it is characterized in that, this LDMOS device is a N raceway groove LDMOS device, and the doping type of this silicon substrate, high pressure trap, source electrode, source electrode drift region, grid, drain electrode, drain-drift region and relieving block is respectively P type, P type, the heavy doping of N type, N type light dope, the heavy doping of N type, the heavy doping of N type, N type light dope and P type.
4. the LDMOS device that improves rebound performance as claimed in claim 1, it is characterized in that, this LDMOS device is a P raceway groove LDMOS device, and the doping type of this silicon substrate, high pressure trap, source electrode, source electrode drift region, grid, drain electrode, drain-drift region and relieving block is respectively P type, N type, the heavy doping of P type, P type light dope, the heavy doping of P type, the heavy doping of P type, P type light dope and N type.
5. described manufacture method of improving the LDMOS device of rebound performance of claim 1 may further comprise the steps: a, provide a silicon substrate; B, carry out ion implantation technology and annealing process and form the high pressure trap at this silicon substrate; C, carry out ion implantation technology and annealing process and form source electrode drift region and drain-drift region at this high pressure trap; D, on the high pressure trap, make grid and side wall thereof; E, carry out ion implantation technology and annealing process and form source electrode and drain electrode in source electrode drift region and drain-drift region respectively; It is characterized in that this method also has step c1 between step c and the d: carry out ion implantation technology and annealing process in the high pressure trap and adjoin the source electrode drift region and form relieving block, the implanted dopant type of the ion implantation technology among this step c1 and the step b is identical.
6. the manufacture method of improving the LDMOS device of rebound performance as claimed in claim 5, it is characterized in that the ion implantation technology that forms high pressure trap, source electrode, source electrode drift region, grid, drain electrode, drain-drift region and relieving block is respectively P type, the heavy doping of N type, N type light dope, the heavy doping of N type, the heavy doping of N type, N type light dope and P type ion implantation technology.
7. the manufacture method of improving the LDMOS device of rebound performance as claimed in claim 6 is characterized in that, the implanted dopant that forms the ion implantation technology of relieving block is a boron, and the injection energy is 1200kev, and implantation dosage is 1 * 10
13Cm
-2
8. the manufacture method of improving the LDMOS device of rebound performance as claimed in claim 5, it is characterized in that the ion implantation technology that forms high pressure trap, source electrode, source electrode drift region, grid, drain electrode, drain-drift region and relieving block is respectively N type, the heavy doping of P type, P type light dope, the heavy doping of P type, the heavy doping of P type, P type light dope and N type ion implantation technology.
9. the manufacture method of improving the LDMOS device of rebound performance as claimed in claim 5, it is characterized in that, this method also has between step b and c in high pressure trap area of grid both sides makes nearly gate groove isolation structure respectively, and the step of making gate groove isolation structure far away respectively in source electrode and both sides, drain region.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102569392A (en) * | 2010-12-27 | 2012-07-11 | 中芯国际集成电路制造(北京)有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) transistor, layout method and manufacture method |
| CN103325834A (en) * | 2013-05-02 | 2013-09-25 | 上海华力微电子有限公司 | Transistor and method for forming channel length of transistor |
| CN104282667A (en) * | 2014-09-30 | 2015-01-14 | 中航（重庆）微电子有限公司 | MOS electrostatic protection structure and protection method |
| CN104752204A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of LDMOS device |
| CN109473427A (en) * | 2017-09-08 | 2019-03-15 | 立锜科技股份有限公司 | High voltage device and its manufacturing method |
| CN109659368A (en) * | 2018-12-19 | 2019-04-19 | 上海华力微电子有限公司 | A kind of high maintenance voltage NLDMOS and preparation method thereof |
| CN111104716A (en) * | 2019-12-09 | 2020-05-05 | 北京航空航天大学 | Automatic generation method of groove type resistance reducing structure based on thermal diffusion facing to blade |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102569392A (en) * | 2010-12-27 | 2012-07-11 | 中芯国际集成电路制造(北京)有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) transistor, layout method and manufacture method |
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| CN104752204A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of LDMOS device |
| CN104282667A (en) * | 2014-09-30 | 2015-01-14 | 中航（重庆）微电子有限公司 | MOS electrostatic protection structure and protection method |
| CN109473427A (en) * | 2017-09-08 | 2019-03-15 | 立锜科技股份有限公司 | High voltage device and its manufacturing method |
| CN109473427B (en) * | 2017-09-08 | 2020-06-30 | 立锜科技股份有限公司 | High voltage device and method for manufacturing the same |
| CN109659368A (en) * | 2018-12-19 | 2019-04-19 | 上海华力微电子有限公司 | A kind of high maintenance voltage NLDMOS and preparation method thereof |
| CN111104716A (en) * | 2019-12-09 | 2020-05-05 | 北京航空航天大学 | Automatic generation method of groove type resistance reducing structure based on thermal diffusion facing to blade |
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