CN109411532A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN109411532A
CN109411532A CN201810403205.2A CN201810403205A CN109411532A CN 109411532 A CN109411532 A CN 109411532A CN 201810403205 A CN201810403205 A CN 201810403205A CN 109411532 A CN109411532 A CN 109411532A
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China
Prior art keywords
semiconductor device
layer
source
epitaxially grown
drain regions
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CN201810403205.2A
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English (en)
Inventor
申洪湜
金泰坤
雄朗·佐佐木
雄一朗·佐佐木
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN109411532A publication Critical patent/CN109411532A/zh
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Abstract

本发明提供一种半导体装置，包括：衬底，包括定义有源区的场区；源区/漏区，位于有源区中；沟道区，位于源区/漏区之间；轻掺杂漏(LDD)区，位于源区/漏区中的一个与沟道区之间；以及栅极结构，位于沟道区上。有源区的上部部分可包括外延生长层，所述外延生长层的晶格常数大于硅(Si)的晶格常数，且源区/漏区以及LDD区可掺杂有镓(Ga)。

Description

半导体装置
相关申请的交叉参考
本申请主张2017年8月17日在韩国知识产权局递交的韩国专利申请第10-2017-0104160号的优先权，所述韩国专利申请的公开内容全文并入本案供参考。
技术领域
本公开涉及半导体装置，且特别是涉及在沟道区中具有提高的迁移率特性的载流子的半导体装置。
背景技术
随着电子行业已快速发展且随着用户需求增加，电子装置变得更小且更轻。具有高集成度的半导体装置是电子装置中所需的，因此半导体装置的元件的设计规则也随之减小。此外，对于高速半导体装置的需求逐渐增大。已部分地进行了各种研究以满足半导体装置的高集成度和高速的要求。
发明内容
本公开提供半导体装置，所述半导体装置可在其沟道区中具有提高的迁移率特性的载流子。
根据本公开的一方面，提供一种半导体装置。所述半导体装置可包含：衬底，包括定义有源区的场区；源区/漏区，位于有源区中；沟道区，位于源区/漏区之间；轻掺杂漏(LDD)区，位于源区/漏区中的一个与沟道区之间；以及栅极结构，位于沟道区上。所述有源区的上部部分可包含外延生长层，外延生长层的晶格常数大于硅(Si)的晶格常数，且源区/漏区以及轻掺杂漏区可掺杂有镓(Ga)。
根据本公开的另一方面，提供一种半导体装置。所述半导体装置可包含：衬底，具有第一晶体管区以及第二晶体管区且由第一材料形成；第一有源区，形成于第一晶体管区中；以及第二有源区，形成于第二晶体管区中且包含源区/漏区以及沟道区。第一有源区的上部区可包含第一外延生长层，第一外延生长层包含第一材料，且第二有源区的上部部分可包含第二外延生长层，所述第二外延生长层包含超过50原子百分比(at％)的第二材料。第二材料可以不同于第一材料，源区/漏区可掺杂有镓(Ga)，且第一有源区和第二有源区中的每一个的顶部表面可以是平坦的。
根据本公开的另一方面，提供一种半导体装置。所述半导体装置可包含：有源区，具有沟道区和掺杂有镓(Ga)的源区/漏区；沟道硅锗(c-SiGe)层，构成所述有源区的上部部分且包含超过50原子百分比(at％)的Ge；以及栅极结构，设置于所述沟道硅锗(c-SiGe)层上且包含高介电常数栅极绝缘层以及金属栅极电极。
附图说明
结合附图及以下详细描述，将更加清楚地理解本公开的各个方面，在附图中：
图1到图11是用于描述根据本公开的方面的半导体装置的制造方法的截面图。
图12是绘示根据本公开的方面的薄层电阻相对于用于半导体装置中的杂质的剂量的曲线图。
图13是根据本公开的方面的包含半导体装置的系统的配置的视图。
附图标号说明：
10：半导体装置
101：衬底
111：第一半导体层
111'：n型LDD区
111"：n型源区/漏区
111T：顶部表面
120：p型沟道区
121：第二半导体层
121'：p型轻掺杂漏(LDD)区
121"：p型源区/漏区
121T：顶部表面
131：装置隔离层
131T：顶部表面
210：虚设栅极结构
211：虚设栅极
213：栅极掩模
220：间隔物
230：栅极结构
231：栅极绝缘层
233：栅极电极
310：金属间绝缘层
320：接触塞
330：层间绝缘层
340：导线
1000：系统
1010：控制器
1020：输入/输出装置
1030：存储器装置
1040：接口
1050：总线
AR：有源区
M1：第一掩模图案
M2：第二掩模图案
M3：第三掩模图案
M4：第四掩模图案
Rs：薄层电阻
TR1：n型晶体管
TR2：p型晶体管
具体实施方式
下文中，将参看附图详细描述本公开的各个方面。
图1到图11是用于描述根据本公开的方面的半导体装置的制造方法的截面图。
参看图1，衬底101可包含第一晶体管区n-FET以及第二晶体管区p-FET。
衬底101可包含硅(Si)，例如结晶硅(Si)、多晶硅(Si)或非晶硅(Si)。在其它实施例中，衬底101可包含化合物半导体，例如锗(germanium；Ge)、硅锗(silicon germanium；SiGe)、碳化硅(silicon carbide；SiC)、砷化镓(gallium arsenide；GaAs)、砷化铟(indiumarsenide；InAs)或磷化铟(indium phosphide；InP)。在一些实施例中，衬底101可包含导电区，例如掺杂有杂质的阱或掺杂有杂质的结构。下文中，在当前示例实施例中，衬底101为Si衬底。
衬底101可包含第一晶体管区n-FET以及第二晶体管区p-FET。多个半导体装置可以位于第一晶体管区n-FET以及第二晶体管区p-FET中的每一个中。如下文将描述，衬底101上的半导体装置可以通过装置隔离层(例如，图4的装置隔离层131)而彼此电分离。
第一晶体管区和第二晶体管区可以相对于彼此来定义。也就是说，当第一晶体管区是n-FET区时，第二晶体管区可以是p-FET区。或者，当第一晶体管区是p-FET区时，第二晶体管区可以是n-FET区。下文中，在当前示例实施例中，第二晶体管区是p-FET区。
参看图2，第一半导体层111可形成于第一晶体管区n-FET上。第一掩模图案M1可形成于第二晶体管区p-FET上。
第一半导体层111可形成于第一晶体管区n-FET上，且第一半导体层111可以是使用外延生长工艺从构成衬底101的Si原子生长的硅(Si)、硅锗(SiGe)或适用于半导体装置的任何材料。下文中，在当前示例实施例中，第一半导体层111是Si层。
因此，第一晶体管区n-FET中的半导体装置的沟道区的晶格结构可以由衬底101的晶格结构以及第一半导体层111的晶格结构来确定。同时，可执行外延生长工艺使得衬底101可以不具有晶格缺陷或具有最小晶格缺陷。
由于第一掩模图案M1是形成于第二晶体管区p-FET中，因此可以抑制/阻止第二晶体管区p-FET中的Si外延生长，使得可以选择性地在第一晶体管区n-FET中执行Si外延生长。
第一半导体层111经生长以使缺陷最小化且使应变最大化。第一半导体层111在后续工艺中形成有源区(例如，图4的有源区AR)的上部部分。
考虑到后续工艺，第一半导体层111的顶部表面111T可与衬底101的顶部表面齐平或不齐平。第一半导体层111的顶部表面111T的位置可以根据由待后续工艺执行的第一晶体管区n-FET与第二晶体管区p-FET之间的拓扑(topology)的差异造成的困难程度来调节。
参看图3，移除第一掩模图案(例如，图2的第一掩模图案M1)以后，可使用形成于第一半导体层111上的第二掩模图案M2来形成第二半导体层121于第二晶体管区p-FET中。
第二半导体层121可以形成于第二晶体管区p-FET中且可以是使用外延生长工艺从构成衬底101的Si原子生长的Si、SiGe或适用于半导体装置的任何材料。下文中，在当前示例实施例中，第二半导体层121是SiGe层。
因此，第二晶体管区p-FET中的半导体装置的沟道区的晶格结构可以由衬底101以及第二半导体层121的晶格结构来确定。第二晶体管区p-FET的沟道区可包含超出50原子百分比(可在本文中被称作at％)的Ge原子。同时，在第二晶体管区p-FET的沟道区中可以有影响沟道电流特性的悬空键。因此，可执行外延生长工艺使得衬底101可不存在晶格缺陷或只有最小晶格缺陷。
由于第二掩模图案M2形成于第一晶体管区n-FET中，因此可以防止第一晶体管区n-FET中的SiGe外延生长，使得可以选择性地在第二晶体管区p-FET中执行SiGe外延生长。
第二半导体层121可经生长以使缺陷最小化且使应变最大化。第二半导体层121在后续工艺中构成有源区(参看图4的AR)的上部部分。由于在p型晶体管中，作为沟道区中的载流子的空穴的迁移率影响装置的特性，因此可使用将应变施加到沟道区的方法。
SiGe具有比Si更大的晶格常数。由于晶格常数不匹配造成的应力而产生应变，例如是张力应变(tension-strain)，且因此可以提高空穴的迁移率特性。在执行后续工艺时，应变可完全地保留或可以部分地释放。
考虑到上述工艺，第二半导体层121的顶部表面121T可与衬底101的顶部表面齐平或不齐平。第二半导体层121的顶部表面121T的位置可以根据由在上述工艺中执行的第二晶体管区p-FET与第一晶体管区n-FET之间的拓扑的差异造成的工艺的困难度而调节。
参看图4，在移除第二掩模图案(例如，图3的第二掩模图案M2)之后，衬底101的有源区AR可以通过装置隔离层131而彼此电分离。
装置隔离层131可包含一个绝缘层，但可包含外绝缘层以及内绝缘层。外绝缘层及内绝缘层可以由不同材料形成。举例来说，外绝缘层可包含氧化物层，且内绝缘层可包含氮化物层。然而，装置隔离层131的配置不限于以上描述。举例来说，装置隔离层131可包含多层，所述多层包含至少三种类型的绝缘层的组合。
第一晶体管区n-FET及第二晶体管区p-FET中的每一个可包含在其中形成半导体装置的有源区AR。装置隔离层131可定义每个有源区AR。第一晶体管区n-FET及第二晶体管区p-FET可以通过装置隔离层131来彼此分离。也就是说，装置隔离层131可被称为场区(field region)。此外，装置隔离层131可以是浅沟槽隔离区。
根据本公开，构成第二晶体管区p-FET的有源区AR的上部部分的第二半导体层121的顶部表面121T可以与装置隔离层131的顶部表面131T大体上齐平。此外，第一半导体层111的顶部表面111T可与装置隔离层131的顶部表面131T大体上齐平。也就是说，第一半导体层111的顶部表面111T、第二半导体层121的顶部表面121T以及装置隔离层131的顶部表面131T可齐平或大体上齐平。
参看图5，可形成多个虚设栅极结构210，以形成后栅极方案应用装置(gate lastscheme-applied device)的替代金属栅极。
多个虚设栅极结构210可以利用形成多个虚设栅极211的工艺以及在在多个虚设栅极211的顶部表面上形成栅极掩模213的工艺来形成。
现将更详细地描述形成多个虚设栅极结构210的方法。
可在第一半导体层111及第二半导体层121上形成虚设栅极形成层，且可在虚设栅极形成层上形成栅极掩模形成层。在栅极掩模形成层上形成用于形成多个虚设栅极211及栅极掩模213的掩模图案。可以使用掩模图案作为蚀刻掩模来对栅极掩模形成层及虚设栅极形成层进行蚀刻，以在第一半导体层111及第二半导体层121上形成包含多个虚设栅极211及栅极掩模213的多个虚设栅极结构210。具有相同宽度及高度的多个虚设栅极211可以形成于第一半导体层111及第二半导体层121上。然而，本公开不限于此，且可以形成具有不同宽度及高度的多个虚设栅极211。
举例来说，虚设栅极211可以由Si形成。详细地说，虚设栅极211可以由多晶硅、非晶硅或其组合形成。多晶硅可以使用化学气相沉积(chemical vapor deposition；CVD)形成，且非晶硅可以使用溅镀、CVD、等离子沉积及类似工艺形成。然而，本公开不限于此。下文中，在当前示例实施例中，虚设栅极211由多晶硅形成。
虚设栅极211可在相同区中具有相同宽度。或者，虚设栅极211可根据其目的即使在相同区中也可具有不同的宽度。尽管在图式中具有相同宽度的虚设栅极211形成于第一半导体层111及第二半导体层121上，但本公开不限于此。
举例来说，栅极掩模213可包含氧化硅层、氮化硅层、氮氧化硅层或其组合。栅极掩模213可以使用CVD来形成。下文中，在当前实施例中，栅极掩模213中的每一个包含氮化硅层。
每个栅极掩模213的宽度及高度可根据虚设栅极211而改变。虚设栅极211的宽度越大，栅极掩模213的宽度越大。
栅极掩模213可在相同区中具有相同高度。或者，栅极掩模213可即使在相同区中也可具有不同的高度。尽管图式示出具有相同高度的栅极掩模213形成于第一半导体层111及第二半导体层121上，但本公开不限于此。
参看图6，可通过离子注入具有杂质的镓(Ga)来形成p型轻掺杂漏(lightly dopeddrain；LDD)区121'。
随着半导体装置的集成增加，构成集成电路的晶体管的尺寸也逐渐减小。因此，晶体管的沟道长度也会减小，且可能出现使晶体管的特性退化的短沟道效应。短沟道效应的出现可能是由于漏极诱导势垒降低(drain induced barrier lowering；DIBL)、穿通(punch through)或热载流子效应(hot carrier effect)。
热载流子效应是指以下这种现象：随着源极与漏极之间的距离缩短，从源极发出的载流子通过靠近漏极的边缘的高电场快速加速而使得产生热载流子，且所述热载流子导致晶体管的特性恶化。LDD区可用于改善由于热载流子导致的晶体管恶化。
在本文中将更详细地描述形成p型LDD区121'的方法。首先，可以形成覆盖第一晶体管区n-FET的第三掩模图案M3。第三掩模图案M3可以使用曝光及显影工艺形成。随后，可使用第三掩模图案M3及第二半导体层121上的虚设栅极结构210作为离子注入(ionimplantation；IIP)的阻断掩模来将Ga作为杂质注入到暴露的区域中。IIP可使用离子注入设备来执行，且IIP的倾角(其与衬底101的顶部表面形成的角)可在约30°到约90°的范围内。
尽管未绘示，但可在形成p型LDD区121'之前或之后执行n型杂质的环状离子注入(halo ion implantation)。环状离子注入使用与晶体管类型相反的杂质。环状离子注入可有效防止穿通(punch through)。
根据本公开的方面，p型LDD区121'中的Ga的剂量可以为约1E13到2E15原子/平方厘米(atoms/cm2)。随着构成第二半导体层121的SiGe中的Ge的化学计量增加，p型LDD区121'掺杂有Ga，Ga相较于硼(boron；B)具有较高程度的电激活(electrical activation)，使得可以提高p型晶体管的速度特性。当具有相对较高激活程度的Ga用于第二半导体层121中时，相较于注入与Ga相同剂量的B的情况，可以实现低电阻使得可以提高p型晶体管的速度特性。这将参考图12详细地描述。
参看图7，在移除第三掩模图案(例如，图6的第三掩模图案M3)之后，可通过对第一晶体管区n-FET执行n型杂质的离子注入而形成n型LDD区111'，且间隔物220可以形成于多个虚设栅极结构210中的每一个的两个侧壁处。
形成n型LDD区111'的工艺可与在第二晶体管区p-FET中形成p型LDD区121'的工艺类似。然而，不同之处在于注入到第二晶体管区p-FET中的是n型杂质。举例来说，n型杂质可以是第V族元素。形成n型LDD区111'的工艺可以由本领域的技术人员参考图6所描述进行修改。因此，将省略其详细描述。
尽管未绘示，但在形成n型LDD区111'之前或之后，可使用p型杂质执行环状离子注入。环状离子注入使用与晶体管类型相反的杂质。
在形成n型LDD区111'及p型LDD区121'之后，间隔物220可以形成于多个虚设栅极结构210中的每一个的两侧。间隔物220可由选自由以下组成的族群中的至少一个形成：氧化硅、氮化硅以及氮氧化硅。在当前示例实施例中，间隔物220包含单层。然而，本公开不限于此，且间隔物220还可以包含双层或三层。
参看图8，可通过将Ga作为杂质离子注入到第二晶体管区p-FET中，以形成p型源区/漏区121"。
现将更详细地描述形成p型源区/漏区121"的方法。
首先，可形成第四掩模图案M4，以覆盖第一晶体管区n-FET。第四掩模图案M4可以使用曝光及显影工艺形成。随后，使用第四掩模图案M4、设置于第二半导体层121上的虚设栅极结构210以及形成于每个虚设栅极结构210的两个侧壁处的间隔物220作为IIP的阻断掩模，以将Ga(其为杂质)注入到暴露出的区域中。IIP可使用离子注入设备来执行，且IIP的倾角(其与衬底101的顶部表面形成的角)可以在约70°到约90°的范围内。
根据本公开的各个方面，p型源区/漏区121"中的Ga的剂量可以为5E13到5E15原子/平方厘米。p型源区/漏区121"中的Ga的剂量可高于p型LDD区121'中的Ga的剂量。
随着构成第二半导体层121的SiGe中的Ge的化学计量增加，p型源区/漏区121"可掺杂有相较于B具有较高电激活程度的Ga，使得可以提高p型晶体管的速度特性。p型源区/漏区121"可不仅形成于第二半导体层121上，还可形成于部分衬底101上。也就是说，p型源区/漏区121"的上部部分可以是包含超过50原子百分比的Ge的SiGe的外延生长层，而p型源区/漏区121"的其他部分可以是Si。
当具有相对较高激活程度的Ga用于第二半导体层121中时，例如，用于p型源区/漏区121"的上部部分中，相较于其中注入与Ga相同剂量的B的情况，可以实现低电阻，使得可以提高p型晶体管的速度特性。这将在下文参考图12详细地描述。
p型源区/漏区121"可以形成于间隔物220两侧的衬底101内，且可在虚设栅极结构210下方定义位于p型源区/漏区121"之间的p型沟道区120。
p型沟道区120可位于第二半导体层121中。也就是说，p型沟道区120可以是包含超过50原子百分比的Ge的SiGe的外延生长层。换句话说，p型沟道区120可位于沟道硅锗(c-SiGe)层中。此外，p型LDD区121'可位于p型沟道区120的两侧。由于p型LDD区121'与p型源区/漏区121"彼此交叠的区被定义为p型源区/漏区121"，因此p型LDD区121'可仅位于p型沟道区120的两侧。
参看图9，在移除第四掩模图案(例如，图8的第四掩模图案M4)之后，可通过将n型杂质离子注入到第一晶体管区n-FET中，以形成n型源区/漏区111"。
形成n型源区/漏区111"的工艺可与在第二晶体管区p-FET中形成p型源区/漏区121"的工艺类似。然而，唯一差别是在第二晶体管区p-FET中注入的是n型杂质。n型杂质可以是第V族元素。形成n型源区/漏区111"的工艺可以由本领域的技术人员参考图8所描述的进行修改，且因此，将省略其详细描述。
n型源区/漏区111"可不仅形成于第一半导体层111上，而且可以形成于部分衬底101上。也就是说，n型源区/漏区111"的上部部分可以是Si的外延生长层，且n型源区/漏区111"的其他部分也可以是Si。
n型源区/漏区111"可以形成于间隔物220两侧的衬底101内，且可在虚设栅极结构210下方定义位于n型源区/漏区111"之间的n型沟道区110。
n型沟道区110可位于第一半导体层111中。也就是说，n型沟道区110可以是Si的外延生长层。换句话说，n型沟道区110可位于沟道硅(c-Si)层中。此外，n型LDD区111'可位于n型沟道区110的两侧。n型LDD区111'及n型源区/漏区111"彼此交叠的区可以被定义为n型源区/漏区111"。也就是说，n型LDD区111'可仅位于n型沟道区110的两侧。
在对n型LDD区111'及p型LDD区121'及n型源区/漏区111"以及p型源区/漏区121"执行杂质掺杂之后，可以在约650℃到1050℃的温度下对衬底101进行退火约5秒到240秒，以便修补由杂质注入造成的损伤。时间和温度不限于以上数值。
参看图10，可以移除多个虚设栅极结构(参看图9的210)，以形成多个栅极结构230。
在本文中现将更详细地描述形成多个栅极结构230的方法。
首先，举例来说，移除多个虚设栅极结构(参看图9的210)的蚀刻工艺可以是使用氨(ammonia)、氢氧化四甲基铵(tetramethyl ammonium hydroxide；TMAH)及/或氢氧化四乙基铵(tetraethylammonium hydroxide；TEAH)的湿式蚀刻工艺。然而，本公开不限于此。
可在暴露出n型沟道区110的顶部表面及p型沟道区120的顶部表面的沟槽内形成界面层(未绘示)及栅极绝缘层231。
界面层可防止形成于其上的栅极绝缘层231与下部第一半导体层及第二半导体层(例如图5的半导体层111及半导体层121)之间的界面缺陷。举例来说，界面层可以是氧化硅层、氮氧化硅层、硅酸盐层或其组合。在一些实施例中，形成界面层的工艺是可以省略的或可省略。
栅极绝缘层231可以使用原子层沉积(atomic layer deposition；ALD)或化学氧化来形成。栅极绝缘层231可包含高介电常数介电材料。高介电常数介电材料可以是介电常数比氧化硅层的介电常数更高的材料。
高介电常数介电材料可以是包含选自以下组成的族群中的至少一种：氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽以及铅铌酸锌。
可在栅极绝缘层231上形成栅极电极233。栅极电极233可包含钛、氮化钛、钽、氮化钽、钨、铜、铝或其混合物。可使用例如ALD、金属有机ALD(metal organic ALD；MOALD)、CVD、金属有机CVD(metal organic CVD；MOCVD)或物理气相沉积(physical vapor deposition；PVD)等工艺来形成栅极电极233。然而，本公开不限于此。
在一些实施例中，在形成栅极电极233时，为了提高构成栅极绝缘层231的高介电常数介电材料以及构成栅极电极233的金属层堆叠结构的可靠性，在栅极绝缘层231上形成构成栅极电极233的金属层堆叠结构的部分金属层之后，可在所述部分金属层上形成用于热处理的多晶硅牺牲层，所得结构可经热处理且接着可再次移除用于热处理的所述多晶硅牺牲层。随后，可在经热处理的部分金属层上形成另一金属层，以形成栅极电极233。
包含多个栅极结构230及间隔物220的n型晶体管TR1及p型晶体管TR2中的每一个可具有平面结构。也就是说，形成于衬底101上的第一半导体层及第二半导体层(例如，图5的半导体层111及半导体层121)可被大体上形成为平坦的，且n型晶体管TR1及p型晶体管TR2可以形成于所述第一半导体层及第二半导体层之上。
参看图11，半导体装置10可包含接触塞320及导线340。
可在多个栅极结构230及间隔物220上形成金属间绝缘层310。金属间绝缘层310可包含氧化硅层、氮化硅层或其组合。接触塞320可穿透金属间绝缘层310，且因此可与n型源区/漏区111"及p型源区/漏区121"直接接触。
在本文中现将更详细地描述形成接触塞320的方法。
可在金属间绝缘层310上形成掩模图案(未绘示)。掩模图案可覆盖除了将要形成接触孔的区域之外的金属间绝缘层310的一部分。在金属间绝缘层310上形成掩模图案(未绘示)之后，可使用所述掩模图案作为蚀刻掩模来对部分金属间绝缘层310进行蚀刻，以形成接触孔。n型源区/漏区111"及p型源区/漏区121"可以通过接触孔暴露出来。
可以形成覆盖接触孔的内壁的导电势垒层(未绘示)。可将导电材料填充于接触孔中，以形成接触塞320。
随后，可在金属间绝缘层310及接触塞320的顶部表面上形成层间绝缘层330及导线340。在一些实施例中，接触塞320及导线340可以使用镶嵌工艺或双重镶嵌工艺形成。所述工艺可由本领域的技术人员在形成半导体装置的工艺中执行，且因此将省略其详细描述。
通过这些工艺，本公开的方面提供半导体装置10，其具有的提高的速度特性的p型晶体管TR2。
图12是绘示根据本公开的方面的薄层电阻相对于用于半导体装置中的杂质的剂量的曲线图。
参看图12，薄层电阻Rs是根据相对于包含约55at％的Ge的SiGe的B及Ga的剂量来绘示。
需要n型晶体管及p型晶体管来配置CMOS晶体管。在这种状况下，电子和空穴被用作载流子。当Si用作有源区中的材料时，空穴的迁移率低于电子的迁移率。因此，p型晶体管的性能相对低于n型晶体管的性能。
为补充p型晶体管的性能，将SiGe代替Si用于有源区中的工艺应用到p型晶体管区。在纯Si及纯Ge中，空穴的迁移率分别为450cm2/V·s及1900cm2/V·s，且SiGe具有对应于其化学计量的值。
此外，为配置p型晶体管，在SiGe通过外延生长形成后，使用离子注入将具有所需浓度的所需杂质注入所需深度。已发现在p型晶体管中，当p型杂质离子注入到LDD区及源区/漏区中且构成有源区的SiGe中的Ge的含量足够高(例如当Ge超出50原子百分比)时，Ga的激活程度比位于同一III族元素的B的激活程度高。
因此，当在p型晶体管中使用具有相对较高激活程度的Ga作为杂质时，相较于注入相同剂量的B的情况，可以实现低电阻，从而提高p型晶体管的速度特性，且因此可以提高半导体装置的特性。
为验证SiGe层中的结果，分别根据包含约55at％的Ge的SiGe层中的B的剂量及Ga的剂量来测量薄层电阻Rs。B的剂量及Ga的剂量以对数尺度(log scale)表示。
如图12中所说明，Ga的剂量小于B的剂量，以展示等效薄层电阻(equivalentsheet resistance)Rs。详细地说，为达到值为约4100Ω/sq的薄层电阻Rs，所需B的剂量为约2E14原子/平方厘米，且当掺杂具有相同剂量的Ga时，薄层电阻Rs的值可为约2000Ω/sq。
也就是说，当Ga的剂量与B的剂量相同时，两者的薄层电阻Rs的值可以彼此相差两倍或大于两倍。具有较低值的薄层电阻Rs是间接表示空穴的迁移率提高的指数。因此，即使在注入具有相同剂量的杂质时，也可以通过掺杂Ga来提高p型晶体管的速度特性。
因此，在p型晶体管中的有源区中使用包含超过50原子百分比的Ge的SiGe时，如果使用第III族元素当中的Ga作为杂质，那么相较于B作为杂质的情况，可以期望使用较低的剂量而获得相同或更佳的提高的空穴的迁移率。因此，可以提高p型晶体管的速度特性，且因此可以提高半导体装置的特性。
图13是包含根据本公开的方面的半导体装置的系统的配置的视图。
参看图13，系统1000包含控制器1010、输入/输出装置1020、存储器装置1030、接口1040以及总线1050。
系统1000可以是移动系统或用于发射或接收信息的系统。在一些实施例中，移动系统可以是便携式计算机、上网本(web tablet)、移动电话、数字音乐播放器、存储卡或类似物。
在控制系统1000中用于控制执行程序的控制器1010可以是微处理器、数字信号处理器、微控制器或类似装置。
输入/输出装置1020可用于输入或输出系统1000的数据。可将系统1000连接到外部装置，例如个人计算机或网络，或可使用输入/输出装置1020与外部装置交换数据。输入/输出装置1020可以是触控板、键盘或显示装置。
存储器装置1030可以存储用于操作控制器1010的数据或由控制器1010处理的数据。存储器装置1030可包含根据本文所提供的本发明概念的上述实施例的半导体装置10。
接口1040可以是系统1000与外部装置之间的数据传输路径。控制器1010、输入/输出装置1020、存储器装置1030以及接口1040可以通过总线1050彼此连通。
虽然已经参考本发明的实施例展示且描述本发明概念，但将理解，可以在不脱离所附权利要求书的范围的情况下在其中作出形式及细节的各种改变。

Claims (20)

1.一种半导体装置，其特征在于，包括：
衬底，包括定义有源区的场区；
源区/漏区，位于所述有源区中；
沟道区，位于所述源区/漏区之间；
轻掺杂漏区，位于所述源区/漏区中的一个与所述沟道区之间；以及
栅极结构，位于所述沟道区上，
其中所述有源区的上部部分包括外延生长层，所述外延生长层的晶格常数大于硅的晶格常数，以及
其中所述源区/漏区及所述轻掺杂漏区掺杂有镓。
2.根据权利要求1所述的半导体装置，其特征在于，其中所述外延生长层包括硅锗层，所述硅锗层包含超过50原子百分比的锗。
3.根据权利要求1所述的半导体装置，其特征在于，其中所述源区/漏区中的镓的剂量为5E13原子/平方厘米至5E15原子/平方厘米。
4.根据权利要求1所述的半导体装置，其特征在于，其中所述轻掺杂漏区中的镓的剂量为1E13至2E15原子/平方厘米。
5.根据权利要求1所述的半导体装置，其特征在于，其中所述外延生长层的顶部表面是大体上平坦的。
6.根据权利要求5所述的半导体装置，其特征在于，其中所述外延生长层在所述源区/漏区的厚度、所述外延生长层在所述轻掺杂漏区的厚度以及所述外延生长层在所述沟道区的厚度大体上相同。
7.根据权利要求1所述的半导体装置，其特征在于，其中所述栅极结构为平面结构。
8.根据权利要求7所述的半导体装置，其特征在于，其中所述栅极结构包括高介电常数介电栅极绝缘层以及金属栅极电极。
9.根据权利要求1所述的半导体装置，其特征在于，其中所述场区为浅沟槽隔离区。
10.根据权利要求9所述的半导体装置，其特征在于，其中所述浅沟槽隔离区的顶部表面以及所述外延生长层的顶部表面大体上共面。
11.一种半导体装置，其特征在于，包括：
衬底，包括第一晶体管区及第二晶体管区且包括第一材料；
第一有源区，位于所述第一晶体管区中；以及
第二有源区，位于所述第二晶体管区中且包括源区/漏区及沟道区，
其中：
所述第一有源区的上部区包括第一外延生长层，所述第一外延生长层包括所述第一材料，
所述第二有源区的上部部分包括第二外延生长层，所述第二外延生长层包括超过50原子百分比的第二材料，
所述第二材料不同于所述第一材料，
所述源区/漏区掺杂有镓，以及
所述第一有源区和所述第二有源区中的每一个的顶部表面是平坦的。
12.根据权利要求11所述的半导体装置，其特征在于，其中所述第二外延生长层的晶格常数大于所述衬底的晶格常数。
13.根据权利要求11所述的半导体装置，其特征在于，其中所述第二外延生长层因晶格常数不匹配而产生应变。
14.根据权利要求12所述的半导体装置，其特征在于，其中所述第二外延生长层包括张力应变的硅锗。
15.根据权利要求11所述的半导体装置，其特征在于，还包括轻掺杂漏区，所述轻掺杂漏区位于所述源区/漏区中的一个与所述沟道区之间并且掺杂有镓，
其中所述轻掺杂漏区的镓的第一剂量低于所述源区/漏区的镓的第二剂量。
16.一种半导体装置，其特征在于，包括：
有源区，包括沟道区和掺杂有镓的源区/漏区；
沟道硅锗层，构成所述有源区的上部部分且包括超过50原子百分比的锗；以及
栅极结构，位于所述沟道硅锗层上且包括高介电常数栅极绝缘层以及金属栅极电极。
17.根据权利要求16所述的半导体装置，其特征在于，其中所述栅极结构为平面结构。
18.根据权利要求16所述的半导体装置，其特征在于，其中所述沟道硅锗层包括外延生长层。
19.根据权利要求16所述的半导体装置，其特征在于，还包括轻掺杂漏区，所述轻掺杂漏区位于所述源区/漏区中的一个与所述沟道区之间并且掺杂有镓。
20.根据权利要求19所述的半导体装置，其特征在于，其中所述沟道硅锗层延伸至所述轻掺杂漏区以及所述源区/漏区。
CN201810403205.2A 2017-08-17 2018-04-28 半导体装置 Pending CN109411532A (zh)

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