CN109411366B - Surface-protecting three-dimensional packaging method - Google Patents
Surface-protecting three-dimensional packaging method Download PDFInfo
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- CN109411366B CN109411366B CN201811081741.1A CN201811081741A CN109411366B CN 109411366 B CN109411366 B CN 109411366B CN 201811081741 A CN201811081741 A CN 201811081741A CN 109411366 B CN109411366 B CN 109411366B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
Abstract
The invention discloses a three-dimensional packaging method for surface protection.A component and a lead bridge are assembled on a PCB (printed Circuit Board); connecting one ends of the pins through resin encapsulation to obtain a bottom plate; the jig is provided with laminated plates and a bottom plate, and the laminated plates are vertically arranged in a layered manner; resin is encapsulated between two adjacent layers of plates, after the resin is cured and molded, the plates are cut according to the designed outline dimension of the chip, and the side surfaces of the plates are exposed out of the section of the lead bridge of the laminated plate; carrying out metal coating on the side surface, engraving the metal coating, and connecting and forming; and painting the surface, and painting the side surface and the top surface of the third molding module. The obtained chip is packaged, the internal structure is compact, the electric connection is good, and the insulation and isolation of each layer are good; the outer layer has high hardness, reliability, good long-term stability, good acid and alkali resistance, good thermal shock resistance and good vacuum temperature cycle resistance, and can be excellently applied to aerospace.
Description
Technical Field
The invention relates to a packaging technology, in particular to a three-dimensional packaging method for surface protection.
Background
The electrical interconnection of the upper layer and the lower layer of the miniaturized three-dimensional packaging module realized by the prior art method is realized by laser engraving of a metal coating on the surface of a molding module, the metal coating is completely exposed on a simulated surface, and the thickness of the coating is very thin and is about 20 mu m. On one hand, in the process of transporting, carrying and using the module, the surface of the module is inevitably scratched, so that the surface coating of the module is easily damaged and falls off, or the surface coating is damaged due to exposure and finally causes the failure of a molding module and the failure of chip packaging. On the other hand, the metal coatings for realizing the interconnection of the upper layer and the lower layer are exposed on the surface of the molding module and are easily influenced by moisture, pollutants and the like, so that the insulation strength between the metal coatings on the surface of the molding module is reduced, and finally the short circuit failure condition occurs.
In addition, the packaged chip is applied to severe environments in the aerospace field, and the chip must meet strict requirements such as volatile matter limitation, water vapor content, high and low temperature impact resistance, moisture resistance, high temperature reflow soldering resistance and the like.
Therefore, it is necessary to design a three-dimensional packaging method so that the packaged chip meets the strict requirements of aerospace.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention adopts the technical scheme that:
a surface-protecting three-dimensional packaging method comprises the following steps: step a, mounting an electric device, wherein elements are assembled on a PCB, and lead bridges electrically connected with the corresponding elements are arranged on the PCB to obtain a laminated plate; clamping a pin lead bridge on the jig, and connecting one ends of a plurality of pins through resin encapsulation to obtain a bottom plate;
step b, stacking, namely, arranging laminated plates and a bottom plate on the jig, wherein the laminated plates are vertically arranged in a layered manner, every two adjacent layers of laminated plates are separated, and the bottom plate is distributed at the lowest end to obtain a stacked body;
step c, first encapsulation molding, namely encapsulating resin between two adjacent laminate plates in the stacked body, and removing the jig after the resin is cured and molded to obtain a molding module I;
d, cutting and forming, namely cutting the forming module I according to the designed outline dimension of the chip to obtain a forming module II with a smooth side surface, wherein the side surface of the forming module II is exposed out of the section of the lead bridge of the laminated plate;
e, performing surface metallization treatment on the side surface of the side surface plating layer and the side surface of the forming module II to obtain a metal plating layer, wherein lead bridges between the laminated plates are electrically connected;
step f, connecting and molding, namely engraving the metal coating to electrically connect lead bridges among the laminated plates according to the setting of the chip circuit to obtain a third molding module;
step g, surface painting, coating paint on the side surface of the forming module III, wherein the paint comprises 30-60% of acrylic epoxy resin, 10-25% of curing agent, 1-4% of active agent and 1-5% of dispersing agent.
According to another embodiment of the present invention, the paint further comprises 40% to 50% of acrylic epoxy resin, 10% to 18% of curing agent, 2% to 3% of active agent, and 3% to 4% of dispersing agent.
According to another embodiment of the present invention, further, in the step a, the curing temperature of the base plate is 115 to 135 ℃, and the curing time is 80 to 100 min.
According to another embodiment of the present invention, further, in the step b, the stacked body is baked at a baking temperature of 115 to 135 ℃, and deformation deviation of the pins and the lead bridges is detected.
According to another embodiment of the present invention, further, in the step c, the glue filling pressure is 0.9 to 1.1 MPa.
According to another embodiment of the present invention, further, in the step c, the curing temperature is 140 to 160 ℃; in the step g, the curing temperature of the paint layer is 110-140 ℃.
According to another embodiment of the present invention, in the step e, chemical plating is performed to obtain a plating layer with a thickness of 1-4 um; then, electroplating is performed.
According to another embodiment of the present invention, further, in the step g, the thickness of the side-coated paint layer is 1.7 to 2.3 mm.
The surface-protected three-dimensional packaging method adopted by the invention has the following beneficial effects: the obtained chip is packaged, the internal structure is compact, the electric connection is good, and the insulation and isolation of each layer are good; the outer layer has high hardness, reliability, good long-term stability, good acid and alkali resistance, good thermal shock resistance and good vacuum temperature cycle resistance, and can be excellently applied to aerospace.
In application, the defect that a metal coating on the surface of the existing three-dimensional packaging is easy to damage is solved; by adopting improved three-dimensional encapsulation, the miniaturization and high integration are realized, the electrical interconnection signal wires on the upper layer and the lower layer are realized by the metal coating after laser engraving, the metal coating is embedded in the surface of the module, and the metal coating is not exposed on the outer surface of the module, so that the effect of protecting the metal coating is achieved. On the one hand, in the process of transporting, carrying and using the module, even if the surface of the module is scratched, the metal plating layers which are interconnected with the upper layer and the lower layer cannot be damaged and fall off. On the other hand, because the metal plating layers for realizing interconnection of the upper layer and the lower layer are embedded in the module surface, the module is not easily affected by moisture, pollutants and the like, and the insulation strength of the metal plating layers for interconnection of the upper layer and the lower layer is not reduced, so that the short circuit failure condition is avoided.
Drawings
FIG. 1 is a schematic process flow diagram of the present invention;
FIG. 2 is a schematic structural diagram of a first molding module of the present invention;
FIG. 3 is a schematic structural diagram of a second forming module of the present invention;
figure 4 is a schematic structural view of a laminate panel of the present invention;
fig. 5 is a schematic structural diagram of the bottom plate of the present invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
As shown in fig. 1 to 5, a vertical interconnection method of a three-dimensional package includes the following steps:
step a, performing electric fitting, wherein a PCB is divided into a middle part and an outer part along the radial direction, an element 21 is assembled in the middle part of the PCB, a slotted hole 23 penetrating through the upper end and the lower end is formed in the outer part of the PCB through milling and drilling, a lead bridge 22 of the electric connection element 21 is assembled at the upper end of the slotted hole 23, and a positioning hole is formed in the PCB through milling and drilling to obtain a laminated plate 2; clamping pins 11 on the jig, connecting one ends of a plurality of pins 11 through resin encapsulation to obtain a bottom plate 1 inserted with the plurality of pins 11, assembling a lead bridge 22 electrically connected with the pins 11 on the bottom plate 1, and milling and drilling the bottom plate 1 to process positioning holes;
step b, stacking, namely, mounting a laminated plate 2 and a bottom plate 1 on the jig, wherein the lead bridges 22 of the upper and lower laminated plates correspond to each other in position, and the corresponding positioning holes on the laminated plate 2 and the bottom plate 1 are sleeved with the same positioning rod 3; the laminated plates 2 are vertically arranged in a layered manner, every two adjacent laminated plates 2 are separated, and the bottom plate 1 is distributed at the lowest end to obtain a stacked body;
step c, first encapsulation molding, namely encapsulating resin between two adjacent laminate plates in the stacked body, and removing the jig after the resin is cured and molded to obtain a molding module I;
d, cutting and forming, namely cutting the forming module I according to the designed outline dimension of the chip to obtain a forming module II with a smooth side surface, wherein the side surface of the forming module II is exposed out of the section of the lead bridge 22 of the laminated plate 2;
e, performing surface metallization treatment on the side surface of the side surface plating layer and the side surface of the forming module II to obtain a metal plating layer, and electrically connecting lead bridges 22 among the laminated plates 2;
and f, connecting the wires for molding, and engraving the metal coating to ensure that the lead bridges 22 between the laminated plates 2 are electrically connected according to the setting of the chip circuit and the wires on the side surfaces are along the axial direction to obtain a third molded module, or the third molded module is a product after the step f and realizes vertical interconnection. And (3) connecting the metal coatings in a partitioning manner, wherein lead bridges 22 between the laminated plates 2 accord with the setting of the chip circuit, the reserved coating lines are carved to be used as connecting lines, and the lead bridges 22 between the laminated plates 2 are interconnected according to the setting of the chip circuit.
The outer layer of the chip package may be provided as: and g, potting resin on the side surface and the top surface of the third molding module in a second potting molding process, wherein the pressure of the encapsulation resin in the second potting molding process is greater than that of the encapsulation resin in the first potting molding process, and the curing temperature of the second potting molding process is less than that of the first potting molding process. The inner layer is filled in place, and the outer layer is quickly filled in place and stably fixed and molded. In the packaged chip, the filling pressure ensures that the inner layer element is insulated, isolated and sealed and protected, and the pressure is not easy to cause element damage, dislocation and the like; the outer layer of the packaged chip forms a firm and tight protective layer, and the inner layer circuit is not easy to be affected with damp, crack and the like, and is wear-resistant and pressure-resistant.
The bottom plate, the first encapsulation and the second encapsulation are preferably epoxy resin, and the epoxy resin has the characteristics of compactness, water resistance, good leakage resistance, high strength, high temperature resistance, low temperature resistance, difficult deformation and cracking and the like, and has good technological properties of strong adhesive force, normal-temperature operation, simple and convenient construction and the like.
The outer layer of the chip package may also be configured as: and g, surface painting, and coating a paint on the side surface of the forming module III, wherein the paint comprises acrylic epoxy resin, and the paint is acrylic epoxy resin paint. In the step g, the top surface of the third forming module is also coated with paint, and paint layers are formed on the side surfaces and the top surface of the third forming module.
The paint comprises, by mass, 30-60% of acrylic epoxy resin, 10-25% of a curing agent, 1-4% of an active agent and 1-5% of a dispersing agent; in addition, the water accounts for 10 to 20 percent, and the emulsifier accounts for 3 to 8 percent; the paint is a single component and mainly comprises acrylic epoxy resin, and has the advantages of few varieties of required raw materials and simple preparation. Compared with the common protective paint, the paint has good transparency, short-time recoatability, strong adhesive force and reliability, high paint film hardness and good long-term stability; the acid and alkali resistance is excellent; the product is resistant to cold and heat shock, qualified after 500 times of temperature cycles at-55-125 ℃ and suitable for severe environment; the product is resistant to cold and heat shock, and is qualified after 500 times of temperature circulation at-55-125 ℃; the moisture resistance is excellent, and the moisture resistance of double 85 is verified, and the moisture resistance is verified to be qualified at 500h, 85% RH and 85 ℃; the vacuum temperature cycle/low air pressure meets the requirement, the temperature is-40 ℃ to +70 ℃, each step is 1 hour, the cycle is 10 times, and the temperature is 2 ℃/min; 10-6torr, and the test is satisfactory. The paint film has high hardness, reliability, good long-term stability, good acid and alkali resistance, good cold and hot shock resistance and good vacuum temperature cycle resistance, and can be excellently applied to aerospace. The paint has low odor, the loss of recovery substances is TML, and suspicious volatile substances CVCM meet the use requirement of aerospace. The paint has excellent acid and alkali resistance and soldering temperature resistance, can be suitable for various strict circuit board manufacturing processes, is resistant to washing, is suitable for reflow soldering, and has the reflow soldering temperature of 240 ℃. Preferably, the paint comprises 40-50% of acrylic epoxy resin, 10-18% of curing agent, 2-3% of active agent and 3-4% of dispersing agent, and the paint layer has better comprehensive performance. And curing after painting, wherein the curing temperature is 110-140 ℃, and the curing time is 80-120 min.
In the step a, the base plate 1 is formed by resin encapsulation and curing, a plurality of pins 11 are encapsulated on the base plate 1, and the pins 11 are chip pins 11 and are used for electrically connecting corresponding elements 21 on the laminated plate 2 according to a circuit set in a chip. In the step a, curing is carried out in an oven, wherein the curing temperature of a bottom plate 1 is 115-135 ℃, and the curing time is 80-100 min; then naturally cooling, and taking out from the oven when the temperature is lower than 100 ℃. And (5) checking whether glue leakage and cavities exist at the glue dispensing position of the pin 11 under a microscope.
In step a, the component 21 is mounted on the PCB board. Attaching elements 21 such as resistors, capacitors and the like to the PCB according to a surface mounting process; the component 21 and the internal circuit of the PCB board are electrically connected by self-reflow soldering. In the step a, lead-free tin paste is used, so that the environmental protection grade is improved. The automatic reflow soldering is adopted, air or nitrogen is heated to a high enough temperature and then blown to the PCB board with the attached element 21, the lead-free solder paste is melted to electrically connect the element 21 and an internal circuit of the PCB board, automatic control of feeding, temperature and the like is realized, an oxidation circuit is avoided in the soldering process, and the manufacturing cost is low. In step a, the component 21 may be mounted on the PCB by die bonding or flip chip bonding.
In the step a, oval slotted holes 23 are formed in the periphery of the PCB, the lead bridge 22 stretches across the slotted holes 23, the resin flows up and down well during encapsulation, the encapsulation quality of the chip is good, and hollow structures and the like in the chip are avoided. The chip is required to be made into a round shape and/or the PCB is made into a round shape, and a plurality of slot holes 23 are distributed on the PCB along the circumference; the chip needs to be made square and/or the PCB is square, and the periphery of the PCB is provided with slotted holes 23.
In the step b, the stacking precision of the laminated plates 2 and the base plate 1 is controlled, so that the lead bridges 22 of the upper laminated plate 2 and the lower laminated plate 2 correspond to each other in the vertical direction, and the corresponding deviation of the positions of the upper lead bridge 22 and the lower lead bridge 22 is controlled within 0.2 mm. The positioning rod 3 is used for positioning and clamping the laminated body, the positioning rod 3 penetrates through the laminated plate 2 and the bottom plate 1, and the positioning rod 3 is clamped on the jig.
In the step b, the stacked body is placed in an oven to be baked, wherein the baking temperature is 115-135 ℃, and the baking time is 80-100 min; and (3) taking out the stacked body after cooling, detecting whether the pins 11 and the lead bridge 22 have deformation deviation and the like, controlling the corresponding deviation of the positions of the upper lead bridge 22 and the lower lead bridge 22 within 0.2mm, and judging whether the stacking precision meets the requirements.
In the step c, the stacked body is arranged in a filling and sealing mould, an opening is reserved in the filling and sealing mould, and resin is filled into the opening surface; because the PCB is provided with the slotted hole 23, the resin in the encapsulating mold flows uniformly, and the hollow chip is avoided; and after the resin is filled, heating and curing. Resin is filled between two adjacent laminate plates in the stacked body, and the filling pressure is 0.9-1.1 MPa; curing in an oven at the curing temperature of 140-160 ℃ for 80-100 min; then naturally cooling, and taking out from the oven when the temperature is lower than 100 ℃. Preferably, the glue filling pressure is 0.95-1.05 MPa, and the curing temperature is 148-155 ℃.
And d, cutting the first forming module on a cutting machine according to the external dimension of the finished chip product to obtain a second forming module with the cutting precision of +/-0.05 mm. The chip is made into a square shape, four positions of the forming module I, namely the left, the right, the front and the rear are cut, the shape of the forming module II is determined, and the side surfaces of the forming module II are the front, the rear, the left and the right surfaces of the forming module II; and the chip is made into a round shape, and the side surface of the molding module II is the cylindrical surface of the molding module II.
In the side surface coating process of the step e, firstly, chemical plating is carried out to obtain a coating with the thickness of 1-4 um; then electroplating is carried out to ensure that the thickness of the side coating is 10-20 um. The five surfaces of the module are connected into a whole by metal plating. Firstly, chemically plating a thin layer to ensure that metal in electroplating can be better attached to the existing plating layer; the side coating process is good in quality, rapid, uniform, and small or no pinhole. Chemical plating, in which metal ions in the plating solution are reduced into metal by a proper reducing agent under the condition of no external current and are deposited on the side surface, and the plating layer is uniform and has small pinholes. Electroplating, under the condition of applying direct current, plating a thin layer of metal on the side surface by utilizing the electrolysis principle.
In the side surface plating process of the step e, firstly plating a layer of nickel with the thickness of 18-22 um for enhancing the adhesive force; and plating a layer of gold with the thickness of 18-22 um for protecting the surface plating layer, wherein the surface plating layer is not easy to oxidize. The five surfaces of the module are connected into a whole by metal plating.
And f, using a high-precision automatic laser engraving machine to instantly melt and gasify the processing material under the laser irradiation so as to achieve the purpose of processing. And (3) connecting the metal coatings in a partitioning manner, wherein lead bridges 22 between the laminated plates 2 accord with the setting of a chip circuit, the reserved coating lines are carved to be used as connecting lines, and the lead bridges 22 between the laminated plates 2 are interconnected according to the setting of the chip circuit, so that the laminated plates 2 are correctly electrically connected. Firstly, laser line engraving is carried out, and then the line groove is filled.
And g, in the second encapsulation, the thickness of the resin encapsulated on the side surface is 1.7-2.3 mm, and the thickness of the resin encapsulated on the top surface is 0.3-0.5 mm. The glue filling pressure is 1.8-2.2 MPa; curing in an oven at the curing temperature of 110-140 ℃ for 80-120 min; then naturally cooling, and taking out from the oven when the temperature is lower than 100 ℃. Preferably, the glue filling pressure is 1.9-2.1 MPa, and the curing temperature is 115-130 ℃. Epoxy resin is selected for both the two times of encapsulation, and a certain encapsulation pressure is selected; based on the first encapsulation, the second encapsulation selects the encapsulation pressure and the curing temperature, the outer layer of the packaged chip is reliably adsorbed on the first encapsulation to form a compact pressure-resistant and wear-resistant protective layer, and the inner layer is greatly prevented from being affected with damp, damaged, loosened, cracked and the like.
And g, in the surface painting, the thickness of the side paint layer is 1.7-2.3 mm, and the thickness of the top paint layer is 0.3-0.5 mm.
The above embodiments are only for illustrating the technical solutions of the present invention and are not limited thereto, and any modification or equivalent replacement without departing from the spirit and scope of the present invention should be covered within the technical solutions of the present invention.
Claims (8)
1. A surface-protecting three-dimensional packaging method is characterized by comprising the following steps: step a, performing electric fitting, wherein a component (21) is assembled on a PCB, and lead bridges (22) electrically connected with the corresponding component (21) are arranged on the PCB to obtain a laminated plate (2); clamping pins (11) and lead bridges (22) on the jig, and connecting one ends of a plurality of pins (11) through resin encapsulation to obtain a bottom plate (1);
step b, stacking, namely, mounting laminated plates (2) and a bottom plate (1) on a jig, wherein the laminated plates (2) are vertically arranged in a layered manner, every two adjacent layers of laminated plates (2) are separated, and the bottom plate (1) is distributed at the lowest end to obtain a stacked body;
step c, first encapsulation molding, namely encapsulating resin between two adjacent laminate plates in the stacked body, and removing the jig after the resin is cured and molded to obtain a molding module I;
d, cutting and forming, namely cutting the forming module I according to the designed outline dimension of the chip to obtain a forming module II with a smooth side surface, wherein the side surface of the forming module II is exposed out of the section of the lead bridge (22) of the laminated plate (2);
e, performing surface metallization treatment on the side surface of the side surface plating layer and the side surface of the forming module II to obtain a metal plating layer, wherein lead bridges (22) between the laminated plates (2) are electrically connected;
f, connecting and molding, namely engraving the metal coating to electrically connect lead bridges (22) between the laminated plates (2) according to the setting of the chip circuit to obtain a third molding module;
step g, surface painting, coating paint on the side surface of the forming module III, wherein the paint comprises 30-60% of acrylic epoxy resin, 10-25% of curing agent, 1-4% of active agent and 1-5% of dispersing agent.
2. The surface-protected three-dimensional volumetric encapsulation method according to claim 1, characterized in that: the paint comprises 40-50% of acrylic epoxy resin, 10-18% of curing agent, 2-3% of active agent and 3-4% of dispersing agent.
3. The surface-protected three-dimensional volumetric encapsulation method according to claim 1, characterized in that: in the step a, the curing temperature of the bottom plate (1) is 115-135 ℃, and the curing time is 80-100 min.
4. The surface-protected three-dimensional volumetric encapsulation method according to claim 1, characterized in that: and in the step b, the stacked body is baked at the baking temperature of 115-135 ℃, and deformation deviation of the pins (11) and the lead bridges (22) is detected.
5. The surface-protected three-dimensional volumetric encapsulation method according to claim 1, characterized in that: in the step c, the glue filling pressure is 0.9-1.1 MPa.
6. The surface-protected three-dimensional volumetric encapsulation method according to claim 1, characterized in that: in the step c, the curing temperature is 140-160 ℃; in the step g, the curing temperature of the paint layer is 110-140 ℃.
7. The surface-protected three-dimensional volumetric encapsulation method according to claim 1, characterized in that: in the step e, firstly, chemical plating is carried out to obtain a plating layer with the thickness of 1-4 um; then, electroplating is performed.
8. The surface-protected three-dimensional stereo packaging method according to claim 1 or 6, wherein: in the step g, the thickness of the paint layer coated on the side face is 1.7-2.3 mm.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5514907A (en) * | 1995-03-21 | 1996-05-07 | Simple Technology Incorporated | Apparatus for stacking semiconductor chips |
| US6313522B1 (en) * | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
| CN101072474A (en) * | 2006-05-10 | 2007-11-14 | 三星电机株式会社 | Method of manufacturing build-up printed circuit board |
| CN101308842A (en) * | 2007-01-25 | 2008-11-19 | 三星电子株式会社 | Stacked package, method of manufacturing the same, and memory card having the stacked package |
-
2018
- 2018-09-17 CN CN201811081741.1A patent/CN109411366B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5514907A (en) * | 1995-03-21 | 1996-05-07 | Simple Technology Incorporated | Apparatus for stacking semiconductor chips |
| US6313522B1 (en) * | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
| CN101072474A (en) * | 2006-05-10 | 2007-11-14 | 三星电机株式会社 | Method of manufacturing build-up printed circuit board |
| CN101308842A (en) * | 2007-01-25 | 2008-11-19 | 三星电子株式会社 | Stacked package, method of manufacturing the same, and memory card having the stacked package |
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