CN109360829B

CN109360829B - Pixel array substrate

Info

Publication number: CN109360829B
Application number: CN201811137554.0A
Authority: CN
Inventors: 苏志中; 陈亦伟
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2018-07-09
Filing date: 2018-09-28
Publication date: 2020-09-25
Anticipated expiration: 2038-09-28
Also published as: CN109360829A; TWI683298B; TW202006696A

Abstract

A pixel array substrate comprises a substrate and a plurality of pixel structures. The substrate has an active region. The pixel electrodes are disposed on the active region of the substrate. Each pixel structure comprises a scanning line, a data line, a thin film transistor, a first insulating layer, a common electrode, a second insulating layer, a pixel electrode, a third insulating layer and an auxiliary electrode. The second contact window of the second insulating layer is overlapped with the first contact window of the first insulating layer and is positioned in the first opening of the common electrode. The pixel electrode is arranged on the second insulating layer and is electrically connected to the second end of the thin film transistor through the first contact window. The auxiliary electrode is disposed on the third insulating layer and electrically connected to the common electrode. The auxiliary electrode has a second opening overlapping with the pixel electrode, and the first solid part of the auxiliary electrode shields the first opening.

Description

Pixel array substrate

Technical Field

The present invention relates to a substrate, and more particularly, to a pixel array substrate.

Background

In recent years, there has been an increasing demand for high-resolution display panels. However, as the resolution of the display panel increases, which means that the pixel size in the display panel must be reduced, it is tested whether the process capability meets the more stringent design rule (design rule). In order to reduce the load of the process tool and increase the feasibility of the process, it is an important issue to design an appropriate pixel layout (pixel layout).

In a high-resolution pixel structure, the size of each pixel becomes smaller, and thus the storage capacitance of each pixel structure becomes smaller, resulting in a decrease in the ability to maintain the brightness of the pixel. At present, in order to increase the size of the storage capacitor, the common electrode and the auxiliary electrode are usually disposed above and below the pixel electrode in design to increase the electrode area of the storage capacitor for improvement. However, the above designs encounter a number of significant challenges to overcome.

For example, the pixel structure sequentially includes, from bottom to top, a thin film transistor, a first insulating layer, a common electrode, a second insulating layer, a pixel electrode, a third insulating layer, and an auxiliary electrode. The first insulating layer and the second insulating layer are respectively provided with a first contact window and a second contact window for electrically connecting the pixel electrode and the thin film transistor. The first contact and the second contact partially overlap without affecting the aperture ratio (aperture ratio) of the pixel structure. However, when the second insulating material layer is patterned to form the second contact hole, the top surface and the sidewall of a portion of the first insulating layer are easily removed during the formation of the second contact hole, which causes a collapse phenomenon, and the auxiliary electrode on the uppermost layer is in contact with the pixel electrode and is shorted, thereby generating a display abnormality. Therefore, a pixel structure design that can increase the storage capacitance and solve the short-circuit problem is needed.

Disclosure of Invention

The invention provides a pixel array substrate with good display quality.

The pixel array substrate comprises a substrate, a plurality of pixel structures and auxiliary electrodes. The substrate has an active region. The pixel structures are arranged on the active area of the substrate, and each pixel structure comprises a scanning line, a data line, a thin film transistor, a first insulating layer, a common electrode, a second insulating layer, a pixel electrode, a third insulating layer and an auxiliary electrode. The scanning lines and the data lines are arranged in a staggered mode. The thin film transistor is provided with a first end, a control end and a second end, wherein the first end of the thin film transistor is electrically connected to the data line, and the control end of the thin film transistor is electrically connected to the scanning line. The first insulating layer is disposed on the thin film transistor and has a first contact window overlapping the second end of the thin film transistor. The common electrode is disposed on the first insulating layer and has a first opening, and the first opening of the common electrode overlaps the first contact window of the first insulating layer. The second insulating layer is disposed on the common electrode and has a second contact window, and the second contact window overlaps the first contact window of the first insulating layer and is located in the first opening of the common electrode. The pixel electrode is arranged on the second insulating layer and is electrically connected to the second end of the thin film transistor through the first contact window of the first insulating layer. The third insulating layer is disposed on the pixel electrode. The auxiliary electrode is disposed on the third insulating layer and electrically connected to the common electrode, wherein the auxiliary electrode has a second opening, the second opening of the auxiliary electrode overlaps the pixel electrode, and the first solid portion of the auxiliary electrode shields the first opening of the common electrode.

In an embodiment of the invention, the plurality of pixel structures are arranged in a row along a direction, and the plurality of first openings of the plurality of common electrodes of the plurality of pixel structures on the row are communicated with each other to form a trench extending in the direction.

In an embodiment of the invention, the plurality of pixel structures include a first pixel structure, a second pixel structure and a third pixel structure sequentially arranged in a direction, and the trench overlaps a portion of the first data line of the first pixel structure, a portion of the second data line of the second pixel structure and a portion of the third data line of the third pixel structure.

In an embodiment of the invention, the pixel electrode has a contact portion overlapping with the first opening of the common electrode, and the contact portion of the pixel electrode overlaps with the first solid portion of the auxiliary electrode.

In an embodiment of the invention, the second solid portion of the auxiliary electrode is located outside the first opening of the common electrode and defines a second opening of the auxiliary electrode, the pixel electrode has a display portion located outside the first opening of the common electrode, and an edge of the display portion of the pixel electrode overlaps the second solid portion of the auxiliary electrode.

In an embodiment of the invention, the second solid portion of the auxiliary electrode is located outside the first opening of the common electrode and defines the second opening of the auxiliary electrode, and the second solid portion of the auxiliary electrode overlaps the third solid portion of the common electrode.

In an embodiment of the invention, the vertical projection of the first contact window and the vertical projection of the second contact window are located in the vertical projection of the first opening of the common electrode.

In an embodiment of the invention, the second contact is located in the first contact.

In an embodiment of the invention, the substrate further has a peripheral region outside the active region, the first insulating layer further has a third contact window located in the peripheral region, the pixel array substrate further includes a peripheral trace disposed in the peripheral region of the substrate and having a reference potential, wherein the common electrode is electrically connected to the peripheral trace through the third contact window.

In an embodiment of the invention, the second insulating layer further has a fourth contact hole located in the peripheral region, the third insulating layer has a fifth contact hole located in the peripheral region, and the auxiliary electrode is electrically connected to the common electrode through the fourth contact hole and the fifth contact hole.

Based on the above, the pixel array substrate of an embodiment of the invention includes a plurality of pixel structures, wherein the first openings of the pixel structures form a trench design in a direction. That is, the common electrode has no edge crossing the extending direction of the trench in the display region. Therefore, when designing the placing position of the first contact window, the distance (spacing) between the first contact window and the common electrode in the extending direction of the groove can not be considered. Therefore, the limitation of the layout of the first contact window is reduced, so that the process margin of the pixel array substrate is improved, and the short circuit problem of the auxiliary electrode and the pixel electrode is further improved. In addition, because the short circuit problem between the auxiliary electrode and the pixel electrode is improved, the auxiliary electrode partially overlapped with the pixel electrode can be arranged above the groove of the common electrode, so that the storage capacitance of the whole pixel structure is increased.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic top view of a pixel array substrate 1 according to an embodiment of the invention.

Fig. 2 is a schematic cross-sectional view of the pixel array substrate 1 according to the cross-sectional lines I-I ', II-II ', and III-III ' of fig. 1.

Fig. 3 is a schematic top view of the auxiliary electrode 160 of the pixel array substrate 1 of fig. 1.

Description of reference numerals:

1: pixel array substrate

10: substrate

100: pixel structure

100A: first pixel structure

100B: second pixel structure

100C: third pixel structure

110: a first insulating layer

110C 1: first contact window

110C 2: third contact window

120: common electrode

120P: first opening

130: a second insulating layer

130C 1: second contact window

130C 2: the fourth contact window

140: pixel electrode

142: contact part

144: display unit

144 a: branch of

150: a third insulating layer

150C: the fifth contact window

160: auxiliary electrode

160P: second opening

162: a first solid part

164: second solid part

AA: active region

BL 1: first barrier layer

BL 2: second barrier layer

BL 3: third barrier layer

BL 4: a fourth barrier layer

BL 5: the fifth barrier layer

CH: semiconductor layer

D: drain electrode

DL: data line

DL 1: first data line

DL 2: second data line

DL 3: third data line

G1, G2: grid electrode

GI: gate insulating layer

Ha: first contact hole

Hb: second contact hole

I-I ', II-II ', III-III ': cutting line

K: distance between two adjacent plates

L: peripheral wiring

S: source electrode

And SA: peripheral zone

SL, SL1, SL 2: scanning line

SM: shielding pattern

P: groove

T: thin film transistor

x, y, z: direction of rotation

Detailed Description

Fig. 1 is a schematic top view of a pixel array substrate 1 according to an embodiment of the invention. FIG. 2 is a cross-sectional view of the pixel array substrate 1 depicted by the cross-sectional lines I-I ', II-II ', and III-III ' of FIG. 1. Fig. 3 is a schematic top view of the auxiliary electrode 160 of the pixel array substrate 1 of fig. 1.

Referring to fig. 1 and 2, the pixel array substrate 1 includes a substrate 10 and a plurality of pixel structures 100. The substrate 10 has an active area AA and a peripheral area SA outside the active area AA. The pixel structures 100 are disposed on the active area AA of the substrate 10. Each pixel structure 100 includes a scan line SL, a data line DL interlaced with the scan line SL, and a thin film transistor T. In the present embodiment, the scan lines SL1 and SL2 extend in the direction x, and the first data line DL1, the second data line DL2, and the third data line DL3 extend in the direction y. The scan lines SL2 and SL1 are sequentially arranged along a direction y, and the first data line DL1, the second data line DL2 and the third data line DL3 are sequentially arranged along a direction x, wherein the direction x is staggered with the direction y. For example, in the embodiment, the direction x and the direction y may be substantially perpendicular, but the invention is not limited thereto. In this embodiment, the pixel array substrate 1 may further include a first blocking layer BL1 (shown in fig. 2) disposed on the substrate 10 and a second blocking layer BL2 (shown in fig. 2) disposed on the first blocking layer BL1, and the scan line SL, the data line DL and the thin film transistor T may be disposed on the stack layer formed by the first blocking layer BL1 and the second blocking layer BL 2.

For example, in the present embodiment, the thin film transistor T may include a semiconductor layer CH located on the second blocking layer BL2, a third blocking layer BL3 (shown in fig. 2) covering the semiconductor layer CH, a gate insulating layer GI (shown in fig. 2) located on the third blocking layer BL3, gates G1 and G2 (also called control end of the thin film transistor T) located on the gate insulating layer GI, a fourth blocking layer BL4 (shown in fig. 2) covering the gates G1 and G2, a fifth blocking layer BL5 (shown in fig. 2) located on the fourth blocking layer BL4, and a source S (also called first end of the thin film transistor T) and a drain D (also called second end of the thin film transistor T) located on the fifth blocking layer BL 5. In this embodiment, the third blocking layer BL3 and the gate insulating layer GI on the third blocking layer BL3 can be used together as a gate insulating layer, and a portion of the semiconductor layer CH overlapping the gates G1 and G2 in the direction z can be regarded as a channel of the tft T. In the present embodiment, the gate electrodes G1 and G2 may be selectively located above the semiconductor layer CH, and the thin film transistor T may be a top gate thin film transistor (top gate TFT). In addition, in the present embodiment, the thin film transistor T may have two gate electrodes G1 and G2 respectively overlapping with two different regions of the semiconductor layer CH, and the thin film transistor T may be a dual gate thin film transistor (dual gate TFT). However, the invention is not limited thereto, and in other embodiments, the thin film transistor T may also be a bottom gate thin film transistor (bottom gate TFT) or other suitable type of thin film transistor. In this embodiment, the pixel array substrate 1 may further include a shielding pattern SM, wherein the shielding pattern SM is located between the substrate 10 and the first blocking layer BL1 and overlaps the gate electrodes G1 and G2 in the direction y to shield a portion of the semiconductor layer CH overlapping the gate electrodes G1 and G2 and serving as a channel, so that the portion of the semiconductor layer CH is not easily irradiated by a light beam emitted from a backlight module (not shown) to affect the electrical property of the thin film transistor T.

In the present embodiment, the materials of the first blocking layer BL1, the second blocking layer BL2, the gate insulating layer GI, the third blocking layer BL3, the fourth blocking layer BL4, and the fifth blocking layer BL5 may be inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, etc.), organic materials, or a combination thereof.

The gates G1 and G2 of each pixel structure 100 are electrically connected to the scan line SL. In the embodiment, the gates G1 and G2 may be part of the scan line SL, and the gates G1 and G2 are formed by the same layer as the scan line SL. However, the invention is not limited thereto, and in other embodiments, the gate electrodes G1, G2 and the scan line SL may be formed by different films. The material of the scan line SL and the gates G1 and G2 may be metal or other conductive materials, such as: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials. The source S of each pixel structure 100 is electrically connected to the data line DL. In the present embodiment, the source S may be a portion of the data line DL, and the source S, the drain D and the data line DL may be formed by using the same film. However, the invention is not limited thereto, and in other embodiments, the source S, the drain D and the data line DL may be formed by different films. The source S, the drain D and the data line DL may be made of metal or other conductive materials, such as: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials.

For example, in the present embodiment, the thin film transistor T may further have a first contact hole Ha and a second contact hole Hb, wherein the source S of the thin film transistor T is electrically connected to one region of the semiconductor layer CH through the first contact hole Ha, and the drain D of the thin film transistor T is electrically connected to another region of the semiconductor layer CH through the second contact hole Hb (shown in fig. 2). Referring to fig. 2, in the embodiment, the first contact hole Ha may be composed of a through hole of the third blocking layer BL3, a through hole of the gate insulating layer GI, a through hole of the fourth blocking layer BL4, and a through hole of the fifth blocking layer BL5, which are overlapped with each other, and the second contact hole Hb may be composed of another through hole of the third blocking layer BL3, another through hole of the gate insulating layer GI, another through hole of the fourth blocking layer BL4, and another through hole of the fifth blocking layer BL5, which are overlapped with each other, but the invention is not limited thereto.

Referring to fig. 1 and fig. 2, in the present embodiment, the pixel structure 100 further includes a first insulating layer 110 (shown in fig. 2) disposed on the thin film transistor T and a common electrode 120 disposed on the first insulating layer 110. In the present embodiment, the first insulating layer 110 has a first contact 110C1, and the first contact 110C1 of the first insulating layer 110 overlaps the drain D of the thin film transistor T; the common electrode 120 has a first opening 120P, and the first opening 120P of the common electrode 120 overlaps the first contact 110C1 of the first insulating layer 110.

Referring to fig. 1, in the present embodiment, the plurality of pixel structures 100 are arranged in a row along the direction x, and the plurality of first openings 120P of the plurality of common electrodes 120 of the plurality of pixel structures 100 on the same row are communicated with each other to form a trench P extending in the direction x. For example, in the present embodiment, the first pixel structure 100A, the second pixel structure 100B and the third pixel structure 100C are sequentially arranged in the direction x, the first openings 120P of the first pixel structure 100A, the second pixel structure 100B and the third pixel structure 100C are communicated with each other to form a trench P extending in the direction x, and the entity of the common electrode 120 is disposed in a region other than the trench P. In the present embodiment, the trench P of the common electrode 120 overlaps a portion of the first data line DL1 of the first pixel structure 100A, a portion of the second data line DL2 of the second pixel structure 100B, and a portion of the third data line DL3 of the third pixel structure 100C. Forming a trench P extending in the direction x due to the plurality of first openings 120P of the plurality of common electrodes 120 of the plurality of pixel structures 100 located on the same row communicating with each other; that is, in the active area AA, the common electrode 120 has no edge crossing the direction x, and therefore, the space (spacing) between the first contact 110C1 and the common electrode 120 in the direction x may not be considered when designing the placement position of the first contact 110C 1. Thereby, the layout (layout) of the first contact 110C1 is reduced, so that the process window (process window) of the pixel array substrate 1 is increased.

In the present embodiment, the pixel structure 100 further includes a second insulating layer 130 (shown in fig. 2) disposed on the common electrode 120 and a pixel electrode 140 disposed on the second insulating layer 130. The second insulating layer 130 has a second contact 130C1, and the second contact 130C1 overlaps the first contact 110C1 of the first insulating layer 110 and is located in the first opening 120P of the common electrode 120 and the first contact 110C 1. The pixel electrode 140 is electrically connected to the drain D of the tft T through the first contact hole 110C1 of the first insulating layer 110. In the present embodiment, the vertical projection of the first contact window 110C1 and the vertical projection of the second contact window 130C1 are both located within the vertical projection of the first opening 120P of the common electrode 120. In the present embodiment, the vertical projection of the second contact window 130C1 is also located within the vertical projection of the first contact window 110C 1. That is, the periphery of the second contact 130C1 and the periphery of the first contact 110C1 are maintained at a proper distance K, and the entity of the second insulating layer 130 covers the sidewalls 110b defining the periphery of the first contact 110C1 and the top surface 110a of the first insulating layer 110 beside the sidewalls 110 b. Therefore, in the process of forming the second contact 130C1 of the second insulating layer 130, the portion of the first insulating layer 110 having the sidewall 110b and the top surface 110a is not easily removed during the formation of the second contact 130C1, and thus the collapse phenomenon occurs. Therefore, the risk of short circuit between the film layers due to collapse of the first insulating layer 110 can be reduced, and the yield of the pixel array substrate 1 can be improved.

In the present embodiment, the pixel electrode 140 has a contact portion 142 overlapping the first opening 120P of the common electrode 120 and a display portion 144 located outside the first opening 120P. For example, in the present embodiment, the contact portion 142 of the pixel electrode 140 may have a rectangular shape or other suitable shapes, and the display portion 144 includes a plurality of branches 144 a. However, the present invention is not limited thereto, and in other embodiments, the contact portion 142 and the display portion 144 may be designed in other suitable shapes according to actual requirements. In the present embodiment, the edge of the display portion 144 of the pixel electrode 140 and the third solid portion 122 of the common electrode 120 under the pixel electrode 140 may form a Fringe Field Switching (Fringe-Field Switching), and the display panel using the pixel array substrate 1 may be a Fringe-Field Switching (Fringe-Field Switching), but the invention is not limited thereto. In the present embodiment, the pixel electrode 140 can be a transmissive, reflective, or partially transmissive and partially reflective pixel electrode 140. The pixel electrode 140 may be made of a transparent conductive material, an opaque conductive material, or a combination thereof. For example, the transparent conductive material can be a metal oxide (e.g., indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium oxide, other suitable materials, or a stack of at least two of the foregoing materials), and the opaque conductive material can be a metal or other suitable materials, but the invention is not limited thereto.

Referring to fig. 1, fig. 2 and fig. 3, in the present embodiment, the pixel structure 100 further includes a third insulating layer 150 (shown in fig. 2) disposed on the pixel electrode 140 and an auxiliary electrode 160 disposed on the third insulating layer 150. Referring to fig. 2 and 3, the auxiliary electrode 160 has a second opening 160P, and the second opening 160P of the auxiliary electrode 160 overlaps the display portion 144 of the pixel electrode 140. In the present embodiment, the auxiliary electrode 160 includes a first solid portion 162 and a second solid portion 164. The first solid portion 162 of the auxiliary electrode 160 shields the first opening 120P of the common electrode 120. The second solid portion 164 of the auxiliary electrode 160 is located outside the first opening 120P of the common electrode 120, and the second solid portion 164 defines the range of the second opening 160P. An edge region of the display part 144 of the pixel electrode 140 and an edge region of the second solid part 164 of the auxiliary electrode 160 may overlap. The contact portion 142 of the pixel electrode 140 overlaps the first solid portion 162 of the auxiliary electrode 160. The common electrode 120 has a third solid portion 122 located outside the first opening 120P, and the second solid portion 164 of the auxiliary electrode 160 partially overlaps the third solid portion 122 of the common electrode 120. Therefore, in addition to the second solid portion 164 of the auxiliary electrode 160 and the third solid portion 122 of the common electrode 120 forming a storage capacitor, the first solid portion 162 of the auxiliary electrode 160 and the contact portion 142 of the pixel electrode 140 also form an additional storage capacitor, thereby improving the overall storage capacitor of the pixel structure 100, which helps to improve the performance of the pixel array substrate 1.

Referring to fig. 1 and fig. 2, in the present embodiment, the first insulating layer 110, the second insulating layer 130 and the third insulating layer 150 further have a third contact 110C2, a fourth contact 130C2 and a fifth contact 150C respectively located in the peripheral region SA. In the present embodiment, the pixel array substrate 1 has a peripheral trace L located in the peripheral region SA of the substrate 10, the peripheral trace L has a reference potential, the common electrode 120 is electrically connected to the peripheral trace L through the third contact hole 110C2, and the auxiliary electrode 160 is electrically connected to the common electrode 120 through the fourth contact hole 130C2 and the fifth contact hole 150C. In the present embodiment, the peripheral trace L and the data line DL (e.g., the second metal layer) can be selectively formed on the same film layer. However, the invention is not limited thereto, and in another embodiment, the peripheral trace L and the scan line SL (e.g., the first metal layer) may be formed on the same film; alternatively, the peripheral trace L may be composed of a plurality of portions (e.g., a portion of the first metal layer and a portion of the second metal layer) of the two conductive layers to which the scan line SL and the data line DL belong.

In summary, the pixel array substrate of an embodiment of the invention includes a plurality of pixel structures, wherein a trench is formed in a direction of the first openings of the plurality of pixel structures. That is, the common electrode has no edge crossing the extending direction of the trench in the display region. Therefore, when designing the placing position of the first contact window, the distance (spacing) between the first contact window and the common electrode in the extending direction of the groove can not be considered. Therefore, the limitation of the layout of the first contact window is reduced, and the process margin of the pixel array substrate is improved.

In addition, in an embodiment, the second contact window of the second insulating layer is located in the first contact window of the first insulating layer. That is, the periphery of the second contact hole and the periphery of the first contact hole are kept at a proper distance, and the entity of the second insulating layer covers a plurality of side walls defining the periphery of the first contact hole and the top surface of the first insulating layer beside the plurality of side walls. Therefore, in the process of forming the second contact of the second insulating layer, the portion of the first insulating layer having the sidewall and the top surface is not easily removed in the process of forming the second contact, so that the collapse phenomenon is not easily generated. Therefore, the risk of short circuit between the film layers caused by the collapse of the first insulating layer can be reduced.

Although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A pixel array substrate, comprising:

a substrate having an active region; and

a plurality of pixel structures disposed on the active region of the substrate, each pixel structure comprising:

a scanning line and a data line, which are arranged in a staggered manner;

the thin film transistor is provided with a first end, a control end and a second end, the first end of the thin film transistor is electrically connected to the data line, and the control end of the thin film transistor is electrically connected to the scanning line;

a first insulating layer disposed on the thin film transistor and having a first contact window overlapping the second end of the thin film transistor;

a common electrode disposed on the first insulating layer and having a first opening, wherein the first opening of the common electrode overlaps the first contact window of the first insulating layer;

a second insulating layer disposed on the common electrode and having a second contact window overlapping the first contact window of the first insulating layer and located in the first opening of the common electrode;

a pixel electrode disposed on the second insulating layer and electrically connected to the second end of the thin film transistor through the first contact window of the first insulating layer;

a third insulating layer disposed on the pixel electrode; and

an auxiliary electrode disposed on the third insulating layer and electrically connected to the common electrode, wherein the auxiliary electrode has a second opening, the second opening of the auxiliary electrode overlaps the pixel electrode, and a first solid portion of the auxiliary electrode covers the first opening of the common electrode,

the plurality of pixel structures are arranged in a row along a direction, and a plurality of first openings of a plurality of common electrodes of the plurality of pixel structures on the row are communicated with each other to form a groove extending in the direction.

2. The pixel array substrate of claim 1, wherein the plurality of pixel structures includes a first pixel structure, a second pixel structure, and a third pixel structure arranged in sequence in the direction, and the trench overlaps a portion of a first data line of the first pixel structure, a portion of a second data line of the second pixel structure, and a portion of a third data line of the third pixel structure.

3. The pixel array substrate of claim 1, wherein the pixel electrode has a contact portion overlapping the first opening of the common electrode, and the contact portion of the pixel electrode overlaps the first solid portion of the auxiliary electrode.

4. The pixel array substrate of claim 1, wherein a second solid portion of the auxiliary electrode is disposed outside the first opening of the common electrode and defines the second opening of the auxiliary electrode, the pixel electrode has a display portion disposed outside the first opening of the common electrode, and an edge of the display portion of the pixel electrode overlaps the second solid portion of the auxiliary electrode.

5. The pixel array substrate of claim 1, wherein a second substantial portion of the auxiliary electrode is disposed outside the first opening of the common electrode and defines the second opening of the auxiliary electrode, and the second substantial portion of the auxiliary electrode overlaps a third substantial portion of the common electrode.

6. The pixel array substrate of claim 1, wherein a vertical projection of the first contact window and a vertical projection of the second contact window are within a vertical projection of the first opening of the common electrode.

7. The pixel array substrate of claim 1, wherein the second contact window is located within the first contact window.

8. The pixel array substrate of claim 1, wherein the substrate further has a peripheral region outside the active region, the first insulating layer further has a third contact window in the peripheral region, the pixel array substrate further comprising:

a peripheral trace disposed in the peripheral region of the substrate and having a reference potential, wherein the common electrode is electrically connected to the peripheral trace through the third contact hole.

9. The pixel array substrate of claim 8, wherein the second insulating layer further has a fourth contact hole in the peripheral region, the third insulating layer has a fifth contact hole in the peripheral region, and the auxiliary electrode is electrically connected to the common electrode through the fourth contact hole and the fifth contact hole.