CN109360829A - pixel array substrate - Google Patents
pixel array substrate Download PDFInfo
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- CN109360829A CN109360829A CN201811137554.0A CN201811137554A CN109360829A CN 109360829 A CN109360829 A CN 109360829A CN 201811137554 A CN201811137554 A CN 201811137554A CN 109360829 A CN109360829 A CN 109360829A
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- insulating layer
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- 239000000758 substrate Substances 0.000 title claims abstract description 56
- 239000010409 thin film Substances 0.000 claims abstract description 38
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 230000005611 electricity Effects 0.000 claims 2
- 239000007787 solid Substances 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 30
- 239000010408 film Substances 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 8
- 239000007769 metal material Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 230000000873 masking effect Effects 0.000 description 5
- 230000012447 hatching Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- -1 aluminium tin-oxide Chemical compound 0.000 description 1
- JYMITAMFTJDTAE-UHFFFAOYSA-N aluminum zinc oxygen(2-) Chemical compound [O-2].[Al+3].[Zn+2] JYMITAMFTJDTAE-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
A pixel array substrate comprises a substrate and a plurality of pixel structures. The substrate has an active region. The pixel electrodes are disposed on the active region of the substrate. Each pixel structure comprises a scanning line, a data line, a thin film transistor, a first insulating layer, a common electrode, a second insulating layer, a pixel electrode, a third insulating layer and an auxiliary electrode. The second contact window of the second insulating layer is overlapped with the first contact window of the first insulating layer and is positioned in the first opening of the common electrode. The pixel electrode is arranged on the second insulating layer and is electrically connected to the second end of the thin film transistor through the first contact window. The auxiliary electrode is disposed on the third insulating layer and electrically connected to the common electrode. The auxiliary electrode has a second opening overlapping with the pixel electrode, and the first solid part of the auxiliary electrode shields the first opening.
Description
Technical field
The present invention relates to a kind of substrates, and in particular to a kind of image element array substrates.
Background technique
In recent years, demand of the people to high-res display panel is gradually promoted.However, the resolution when display panel increases
Add, that is, representing the Pixel Dimensions in display panel must try to reduce, thus test technological ability whether meet it is more harsh
Design rule (design rule).In order to reduce the load of technique board and increase the feasibility of technique, picture appropriate is designed
Element layout (pixel layout) becomes important project.
In the dot structure of high-res, each pixel is become smaller in size, thus makes the storage of each dot structure
Capacitor also becomes smaller therewith, and the ability for maintaining pixel intensity is caused to reduce.It at this stage, is the size for increasing storage capacitors, in design
It generallys use common electrode and auxiliary electrode is set to the over and under of pixel electrode, to increase the electrode area of storage capacitors
To improve.However, above-mentioned design, which encounters many severe challenges, to be overcome.
For example, dot structure sequentially includes thin film transistor (TFT), the first insulating layer, common electrode, second from the bottom to top
Insulating layer, pixel electrode, third insulating layer and auxiliary electrode.First insulating layer is respectively provided with first with second insulating layer and contacts
Window and the second contact hole, be electrically connected pixel electrode and thin film transistor (TFT).In the aperture opening ratio for not influencing dot structure
Under the considering of (aperture ratio), the first contact hole can be partly be overlapped with the second contact hole.However, in patterning second
When insulation material layer is to form the second contact hole, the top surface of the first insulating layer of part and side wall are easy forming the second contact hole
It is removed in forming process and avalanche phenomenon occurs, cause the auxiliary electrode positioned at top layer to contact with pixel electrode and short-circuit,
It is abnormal thus to generate display.Therefore, need to develop one kind at present can increase storage capacitors, can also solve the pixel of above-mentioned short circuit problem
Structure design.
Summary of the invention
The present invention provides a kind of image element array substrates, and display quality is good.
Image element array substrates of the invention include substrate, multiple dot structures and auxiliary electrode.Substrate has active region.
Multiple dot structures are configured on the active region of substrate, and each dot structure includes scan line, data line, thin film transistor (TFT),
One insulating layer, common electrode, second insulating layer, pixel electrode, third insulating layer and auxiliary electrode.Scan line and data line
It is staggered.Thin film transistor (TFT) has first end, control terminal and second end, and the first end of thin film transistor (TFT) is electrically connected to number
According to line, the control terminal of thin film transistor (TFT) is electrically connected to scan line.First insulating layer is set on thin film transistor (TFT) and has the
One contact hole, the first contact hole are overlapped in the second end of thin film transistor (TFT).Common electrode is set on the first insulating layer and has
First opening, the first superposition of end gap of common electrode is in the first contact hole of the first insulating layer.Second insulating layer is set to shared
On electrode and there is the second contact hole, the second contact hole is overlapped in the first contact hole of the first insulating layer and is located at common electrode
In first opening.Pixel electrode is set in second insulating layer, and is electrically connected to through the first contact hole of the first insulating layer
The second end of thin film transistor (TFT).Third insulating layer is set on pixel electrode.Auxiliary electrode be set on third insulating layer and with
Common electrode is electrically connected, and wherein auxiliary electrode has the second opening, and the second opening of auxiliary electrode is Chong Die with pixel electrode, and
First opening of the first instance portion masking common electrode of auxiliary electrode.
In one embodiment of this invention, above-mentioned multiple dot structures are in line along a direction, multiple on the row
Multiple first openings of multiple common electrodes of dot structure communicate with each other and form the groove extended in this direction.
In one embodiment of this invention, above-mentioned multiple dot structures include the first pixel of the sequential on direction
Structure, the second dot structure and third dot structure, and groove is overlapped in the part of the first data line of the first dot structure,
The part of the third data line of the part and third dot structure of second data line of two dot structures.
In one embodiment of this invention, above-mentioned pixel electrode has and the contact of the first superposition of end gap of common electrode
Portion, and the contact portion of pixel electrode is Chong Die with the first instance portion of auxiliary electrode.
In one embodiment of this invention, the second instance portion of above-mentioned auxiliary electrode is located at the first opening of common electrode
The second opening that is outer and defining auxiliary electrode, pixel electrode have a display unit outside the first opening of common electrode, and picture
The edge of the display unit of plain electrode is Chong Die with the second instance portion of auxiliary electrode.
In one embodiment of this invention, the second instance portion of above-mentioned auxiliary electrode is located at the first opening of common electrode
The second opening that is outer and defining auxiliary electrode, and the second instance portion of auxiliary electrode is Chong Die with the third entity portion of common electrode.
In one embodiment of this invention, the vertical throwing of the upright projection of the first above-mentioned contact hole and the second contact hole
Shadow is located in the upright projection of the first opening of common electrode.
In one embodiment of this invention, the second above-mentioned contact hole is located in the first contact hole.
In one embodiment of this invention, above-mentioned substrate also has the peripheral region outside active region, and the first insulating layer also has
There is the third contact hole positioned at peripheral region, image element array substrates further include periphery cabling, are set to the peripheral region of substrate and have
Reference potential, wherein common electrode is electrically connected to periphery cabling through third contact hole.
In one embodiment of this invention, above-mentioned second insulating layer also has one the 4th contact hole positioned at peripheral region,
Third insulating layer has the 5th contact hole positioned at peripheral region, and auxiliary electrode is electrical through the 4th contact hole and the 5th contact hole
It is connected to common electrode.
Based on above-mentioned, the image element array substrates of one embodiment of the invention include multiple dot structures, plurality of pixel knot
Multiple first openings of structure form a trench design in a direction.Also that is, in viewing area, common electrode does not have and groove
The staggered edge of extending direction.Therefore, when designing the placement position of the first contact hole, the first contact hole can not be considered and shared
The spacing (spacing) on groove extending direction of electrode.Whereby, the limitation of the layout of the first contact hole reduces, and makes
The process margin of image element array substrates is able to promote and then improve the short circuit problem of auxiliary electrode and pixel electrode.Further, since
The short circuit problem of auxiliary electrode and pixel electrode is improved, therefore, common electrode groove on can setting unit weight
It is laminated on the auxiliary electrode of pixel electrode, to increase the storage capacitors of dot structure entirety.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the schematic top plan view of the image element array substrates 1 of one embodiment of the invention.
Fig. 2 is to be illustrated according to the section of hatching line I-I ', II-II ' and the III-III ' of Fig. 1 image element array substrates 1 shown
Figure.
Fig. 3 shows the schematic top plan view of film layer belonging to the auxiliary electrode 160 of the image element array substrates 1 of Fig. 1.
Description of symbols:
1: image element array substrates
10: substrate
100: dot structure
100A: the first dot structure
100B: the second dot structure
100C: third dot structure
110: the first insulating layers
110C1: the first contact hole
110C2: third contact hole
120: common electrode
120P: the first opening
130: second insulating layer
130C1: the second contact hole
130C2: the four contact hole
140: pixel electrode
142: contact portion
144: display unit
144a: branch
150: third insulating layer
150C: the five contact hole
160: auxiliary electrode
160P: the second opening
162: first instance portion
164: second instance portion
AA: active region
BL1: the first barrier layer
BL2: the second barrier layer
BL3: third barrier layer
BL4: the four barrier layer
BL5: the five barrier layer
CH: semiconductor layer
D: drain electrode
DL: data line
DL1: the first data line
DL2: the second data line
DL3: third data line
G1, G2: grid
GI: gate insulating layer
Ha: the first contact hole
Hb: the second contact hole
I-I ', II-II ', III-III ': hatching line
K: distance
L: periphery cabling
S: source electrode
SA: peripheral region
SL, SL1, SL2: scan line
SM: masking pattern
P: groove
T: thin film transistor (TFT)
X, y, z: direction
Specific embodiment
Fig. 1 is the schematic top plan view of the image element array substrates 1 of one embodiment of the invention.Fig. 2 is the hatching line I- according to Fig. 1
The diagrammatic cross-section for the image element array substrates 1 that I ', II-II ' and III-III ' are drawn.Fig. 3 shows the pixel array base of Fig. 1
The schematic top plan view of film layer belonging to the auxiliary electrode 160 of plate 1.
Fig. 1 and Fig. 2 is please referred to, image element array substrates 1 include substrate 10 and multiple dot structures 100.Substrate 10 has master
The dynamic area AA and peripheral region SA outside active region AA.Multiple dot structures 100 are configured on the active region AA of substrate 10.It is each
Dot structure 100 includes the data line DL and thin film transistor (TFT) T that scan line SL and scan line SL are staggered.In this implementation
In example, scan line SL1, SL2 extends on the x of direction, and the first data line DL1, the second data line DL2, third data line DL3 are in side
Extend on y.Scan line SL2, SL1 is set in sequence along direction y, the first data line DL1, the second data line DL2, third data line
DL3 is set in sequence along direction x, and wherein direction x and direction y are staggered.For example, in the present embodiment, direction x and direction y
Generally can be vertical, but invention is not limited thereto.In the present embodiment, image element array substrates 1 may also include configuration in substrate
The first barrier layer BL1 (being shown in Fig. 2) on 10 and the second barrier layer BL2 on the first barrier layer BL1 (are shown in figure
2), and scan line SL, data line DL and thin film transistor (TFT) T may be provided at and be made of the first barrier layer BL1 and the second barrier layer BL2
Stack layer on.
For example, in the present embodiment, thin film transistor (TFT) T may include the semiconductor layer on the second barrier layer BL2
CH, third barrier layer BL3 (being shown in Fig. 2), the gate insulating layer GI on third barrier layer BL3 for covering semiconductor layer CH
(being shown in Fig. 2), the grid G 1 on gate insulating layer GI, G2 (control terminal that thin film transistor (TFT) T can also be claimed), covering grid
The 4th barrier layer BL4 (being shown in Fig. 2), the 5th barrier layer BL5 (being shown in Fig. 2) on the 4th barrier layer BL4 of G1, G2
And the source S (first end that can also claim thin film transistor (TFT) T) on the 5th barrier layer BL5 and drain D (also claim film brilliant
The second end of body pipe T).In the present embodiment, the third barrier layer BL3 and gate insulating layer GI being located on third barrier layer BL3
It can be considered thin film transistor (TFT) in the part of semiconductor layer CH for being overlapped in grid G 1, G2 on the z of direction collectively as gate insulating layer
The channel of T.In the present embodiment, grid G 1, G2 are selectively positioned at the top of semiconductor layer CH, and thin film transistor (TFT) T can
To be top gate-type thin film transistor (top gate TFT).In addition, in the present embodiment, thin film transistor (TFT) T can have point
Two grid Gs 1, G2 of two area overlappings not different from semiconductor layer CH's, and thin film transistor (TFT) T can be double-gate film crystal
It manages (dual gate TFT).However, the invention is not limited thereto, in other embodiments, thin film transistor (TFT) T can also be bottom gate
The thin film transistor (TFT) of polar form thin film transistor (TFT) (bottom gate TFT) or other appropriate patterns.In the present embodiment, pixel battle array
Column substrate 1 may also include masking pattern SM, wherein masking pattern SM is located between substrate 10 and the first barrier layer BL1, and in side
It is Chong Die with grid G 1, G2 on y, using masking be overlapped in grid G 1, G2 and as the part of semiconductor layer CH in channel, make the portion
Semiconductor layer CH is divided to be not easily susceptible to the electrical property that the light beam that backlight module (not shown) is issued irradiates and influence thin film transistor (TFT) T.
In the present embodiment, the first barrier layer BL1, the second barrier layer BL2, gate insulating layer GI, third barrier layer BL3,
4th barrier layer BL4, the 5th barrier layer BL5 material can for inorganic material (such as: silica, silicon nitride, silicon oxynitride etc.),
The combination of organic material or above-mentioned material.
Grid G 1, G2 and the scan line SL of each dot structure 100 are electrically connected.In the present embodiment, grid G 1, G2 can
For a part of scan line SL, grid G 1, G2 and scan line SL are formed using same film layer.However, invention is not limited thereto,
In other embodiments, grid G 1, G2 can also be used different film layers from scan line SL and formed.Scan line SL and grid G 1, G2
Material can be metal or other conductive materials, such as: alloy, the nitride of metal material, the oxide of metal material, metal material
The nitrogen oxides or metal material of material and the stack layer of other conductive materials.The source S and data of each dot structure 100
Line DL is electrically connected.In the present embodiment, source S can be a part of data line DL, and source S, drain D and data line DL can benefits
It is formed with same film layer.However, invention is not limited thereto, in other embodiments, source S, drain D and data line DL can also
It is formed using different film layers.The material of source S, drain D and data line DL can be metal or other conductive materials, such as: alloy,
The nitride of metal material, the oxide of metal material, the nitrogen oxides of metal material or metal material and other conduction materials
The stack layer of material.
For example, in the present embodiment, thin film transistor (TFT) T can also have the first contact hole Ha and the second contact hole Hb,
The source S of thin film transistor (TFT) T is electrically connected to an area of semiconductor layer CH, the leakage of thin film transistor (TFT) T through the first contact hole Ha
Pole D is electrically connected to another area of semiconductor layer CH through the second contact hole Hb (being shown in Fig. 2).Referring to figure 2., in this implementation
In example, the first contact hole Ha can be by a perforation of the third barrier layer BL3 to coincide with one another, a perforation of gate insulating layer GI, the
A perforation of four barrier layer BL4 and a perforation of the 5th barrier layer BL5 are formed, the second contact hole Hb can by coincide with one another
Another perforation of three barrier layer BL3, another perforation of gate insulating layer GI, another perforation of the 4th barrier layer BL4 and the 5th resistance
Another perforation of exhausted layer BL5 is formed, but invention is not limited thereto.
Referring to Figure 1 and Fig. 2, in the present embodiment, dot structure 100 further includes be set on thin film transistor (TFT) T
One insulating layer 110 (being shown in Fig. 2) and the common electrode 120 being set on the first insulating layer 110.In the present embodiment,
There is one insulating layer 110 first contact hole 110C1, the first contact hole 110C1 of the first insulating layer 110 to be overlapped in thin film transistor (TFT)
The drain D of T；There is common electrode 120 first opening 120P, the first opening 120P of common electrode 120 to be overlapped in the first insulation
First contact hole 110C1 of layer 110.
Referring to Figure 1, in the present embodiment, multiple dot structures 100 are in line along direction x, and on a same row
Multiple first opening 120P of multiple common electrodes 120 of multiple dot structures 100 communicate with each other and are formed on the x of direction and extend
Groove P.For example, in the present embodiment, sequential the first dot structure 100A, the second pixel knot on the x of direction
Structure 100B and third dot structure 100C, and the first dot structure 100A, the second dot structure 100B and third dot structure
The respective first opening 120P of 100C communicates with each other and is formed in the groove P extended on the x of direction, and the entity of common electrode 120 is then
It is set to the region other than groove P.In the present embodiment, the groove P of common electrode 120 is overlapped in the first dot structure 100A's
A part of first data line DL1, the second dot structure 100B the second data line DL2 a part and third dot structure
A part of the third data line DL3 of 100C.Due to being located at multiple common electrodes with multiple dot structures 100 in a line
120 multiple first opening 120P communicate with each other and are formed in the groove P extended on the x of direction；Also that is, in active region AA, altogether
Do not have edge staggered with direction x with electrode 120, therefore, when designing the placement position of the first contact hole 110C1, can not examine
The spacing (spacing) on the x of direction of one contact hole 110C1 of flow control and common electrode 120.Whereby, the first contact hole 110C1
Layout (layout) limit and reduce, and the process margin (process window) of image element array substrates 1 is promoted.
In the present embodiment, dot structure 100 further includes the (mark of second insulating layer 130 being set in common electrode 120
In Fig. 2) and it is set to pixel electrode 140 in second insulating layer 130.Second insulating layer 130 has the second contact hole
130C1, the second contact hole 130C1 are overlapped in the first contact hole 110C1 of the first insulating layer 110 and are located at common electrode 120
In first opening 120P and the first contact hole 110C1.First contact hole 110C1 of the pixel electrode 140 through the first insulating layer 110
It is electrically connected to the drain D of thin film transistor (TFT) T.In the present embodiment, the upright projection of the first contact hole 110C1 is contacted with second
The upright projection of window 130C1 is respectively positioned in the upright projection of the first opening 120P of common electrode 120.In the present embodiment,
The upright projection of two contact hole 130C1 is also located in the upright projection of the first contact hole 110C1.Also that is, the second contact hole 130C1
Surrounding and the surrounding of the first contact hole 110C1 maintains appropriately distance K, and the entity of second insulating layer 130 can cover calmly
Multiple side wall 110b of the surrounding of the first contact hole 110C1 of justice and the top surface of the first insulating layer 110 by multiple side wall 110b
110a.Therefore, during forming the second contact hole 130C1 of second insulating layer 130, there is side wall 110b and top surface 110a
The first insulating layer of part 110 be not easy in the forming process of the second contact hole 130C1 be removed and there is a phenomenon where avalanches.It borrows
This, short-circuit risks caused by capable of reducing between each film layer due to 110 avalanche of the first insulating layer, and make the good of image element array substrates 1
Rate is promoted.
In the present embodiment, pixel electrode 140 has the contact portion Chong Die with the first opening 120P of common electrode 120
142 and positioned at first opening 120P outside display unit 144.For example, in the present embodiment, the contact portion of pixel electrode 140
142 shape can be rectangle or other suitable shapes, and display unit 144 includes multiple branch 144a.However, the present invention is not limited to
This, in other embodiments, also visual actual demand is designed as other suitable shapes for contact portion 142 and display unit 144.In this reality
It applies in example, the edge of the display unit 144 of pixel electrode 140 and the third for the common electrode 120 for being located at 140 lower section of pixel electrode are real
Body portion 122 can form fringe field, and the display panel of image element array substrates 1 is used to can be fringing field switching (Fringe-
Field Switching), but invention is not limited thereto.In the present embodiment, pixel electrode 140 can be penetration, reflection
The pixel electrode 140 of formula or partial penetration partially reflecting.The material of pixel electrode 140 can be transparent conductive material, opaque
Conductive material or combinations thereof.For example, transparent conductive material can for metal oxide (such as: indium tin oxide, indium zinc oxidation
Object, aluminium tin-oxide, aluminium zinc oxide, indium gallium oxide, other suitable materials or be above-mentioned stack layer both at least),
Opaque conductive material can be metal or other suitable materials, but invention is not limited thereto.
Referring to Figure 1, Fig. 2 and Fig. 3, in the present embodiment, dot structure 100 further include being set on pixel electrode 140
Third insulating layer 150 (being shown in Fig. 2) and the auxiliary electrode 160 that is set on third insulating layer 150.Refer to Fig. 2 and
Fig. 3, auxiliary electrode 160 have the second opening 160P, the display of the second opening 160P and pixel electrode 140 of auxiliary electrode 160
Portion 144 is overlapped.In the present embodiment, auxiliary electrode 160 includes first instance portion 162 and second instance portion 164.Auxiliary electrode
Cover the first opening 120P of common electrode 120 in 160 first instance portion 162.164, the second instance portion of auxiliary electrode 160
In outside the first opening 120P of common electrode 120, second instance portion 164 defines the range of the second opening 160P.Pixel electrode
The fringe region in the second instance portion 164 of the fringe region and auxiliary electrode 160 of 140 display unit 144 can be overlapped.Pixel electrode
140 contact portion 142 is Chong Die with the first instance portion 162 of auxiliary electrode 160.Common electrode 120, which has, is located at the first opening
Third entity portion 122 outside 120P, and the third entity portion in the second instance portion 164 of auxiliary electrode 160 and common electrode 120
122 are partly overlapped.Therefore, in addition to the third entity portion 122 in the second instance portion 164 of auxiliary electrode 160 and common electrode 120
It can be formed outside storage capacitors, the first instance portion 162 of auxiliary electrode 160 and the contact portion 142 of pixel electrode 140 can also form volume
Outer storage capacitors, to promote the whole storage capacitors of dot structure 100, this helps to promote image element array substrates 1
Performance.
Fig. 1 and Fig. 2 is please referred to, in the present embodiment, the first insulating layer 110, second insulating layer 130 and third insulating layer
150 are also respectively provided with third contact hole 110C2, the 4th contact hole 130C2 and the 5th contact hole 150C positioned at peripheral region SA.?
In the present embodiment, there is image element array substrates 1 the periphery cabling L of the peripheral region SA positioned at substrate 10, periphery cabling L to have reference
Current potential, common electrode 120 is electrically connected to periphery cabling L through third contact hole 110C2, and auxiliary electrode 160 penetrates the 4th
Contact hole 130C2 and the 5th contact hole 150C are electrically connected to common electrode 120.In the present embodiment, cabling L in periphery may be selected
Property same film layer is formed in data line DL (such as: second metal layer).However, the invention is not limited thereto, in another implementation
In example, periphery cabling L can also be formed in same film layer with scan line SL (such as: the first metal layer)；Alternatively, periphery cabling L
Can as with two conductive layers belonging to scan line SL and data line DL multiple portions (such as: a part of the first metal layer and
A part of two metal layers) it is formed.
In conclusion the image element array substrates of one embodiment of the invention include multiple dot structures, plurality of pixel knot
Multiple first openings of structure form a groove in a direction.Also that is, in viewing area, common electrode does not have the extension with groove
The staggered edge in direction.Therefore, when designing the placement position of the first contact hole, the first contact hole and common electrode can not be considered
The spacing (spacing) on groove extending direction.Whereby, the limitation of the layout of the first contact hole reduces, and makes pixel
The process margin of array substrate is promoted.
In addition, in one embodiment, the second contact hole of second insulating layer is located in the first contact hole of the first insulating layer.
Also that is, the surrounding of the surrounding of the second contact hole and the first contact hole maintains appropriately distance, and the entity meeting of second insulating layer
Multiple side walls of the surrounding of the first contact hole of overlay defining and the top surface of the first insulating layer by the multiple side wall.Therefore,
During forming the second contact hole of second insulating layer, the first insulating layer of part with the side wall and the top surface is not
It is removed easily in the forming process of the second contact hole and avalanche phenomenon occurs.Whereby, it can reduce between each film layer because first is exhausted
The avalanche of edge layer and caused by short-circuit risks.
Although the present invention is disclosed as above by embodiment, embodiment is not intended to limit the invention, any affiliated
Those of ordinary skill in technical field, without departing from the spirit and scope of the present invention, should can make it is certain change and retouch,
Therefore protection scope of the present invention should be subject to appended claim range institute defender.
Claims (10)
1. a kind of image element array substrates, comprising:
One substrate has an active region；And
Multiple dot structures are configured on the active region of the substrate, and each dot structure includes:
Scan line and a data line, are staggered；
One thin film transistor (TFT), has a first end, a control terminal and a second end, and the first end of the thin film transistor (TFT) is electrical
It is connected to the data line, the control terminal of the thin film transistor (TFT) is electrically connected to the scan line；
One first insulating layer is set on the thin film transistor (TFT) and has one first contact hole, which is overlapped in this
The second end of thin film transistor (TFT)；
One common electrode is set on first insulating layer and has one first opening, the first opening weight of the common electrode
It is laminated on first contact hole of first insulating layer；
One second insulating layer, is set in the common electrode and has one second contact hole, second contact hole be overlapped in this
First contact hole of one insulating layer and be located at the common electrode this first opening in；
One pixel electrode is set in the second insulating layer, and is electrically connected through first contact hole of first insulating layer
To the second end of the thin film transistor (TFT)；
One third insulating layer, is set on the pixel electrode；And
One auxiliary electrode is set on the third insulating layer and is electrically connected with the common electrode, and wherein the auxiliary electrode has
Second opening of one second opening, the auxiliary electrode is Chong Die with the pixel electrode, and a first instance portion of the auxiliary electrode
Cover first opening of the common electrode.
2. image element array substrates as described in claim 1, wherein multiple dot structure is in line along a direction, on the row
Multiple dot structure multiple common electrodes it is multiple first opening communicate with each other and form one extended in this direction
Groove.
3. image element array substrates as claimed in claim 2, wherein multiple dot structure includes sequential in this direction
One first dot structure, one second dot structure and a third dot structure, and the groove is overlapped in first dot structure
A part of one first data line, second dot structure one second data line a part and the third dot structure
A third data line a part.
4. image element array substrates as described in claim 1, wherein the pixel electrode has first opens with this of the common electrode
A salty folded contact portion, and the contact portion of the pixel electrode is Chong Die with the first instance portion of the auxiliary electrode.
5. image element array substrates as described in claim 1, wherein a second instance portion of the auxiliary electrode is located at the shared electricity
First opening of pole is outer and defines second opening of the auxiliary electrode, the pixel electrode have positioned at the common electrode should
A display unit outside first opening, and the second instance portion of the edge of the display unit of the pixel electrode and auxiliary electrode weight
It is folded.
6. image element array substrates as described in claim 1, wherein a second instance portion of the auxiliary electrode is located at the shared electricity
First opening of pole is outer and defines second opening of the auxiliary electrode, and the second instance portion of the auxiliary electrode is total with this
It is overlapped with a third entity portion of electrode.
7. image element array substrates as described in claim 1, the wherein upright projection of first contact hole and second contact
The upright projection of window is located in the upright projection of first opening of the common electrode.
8. image element array substrates as described in claim 1, wherein second contact hole is located in first contact hole.
9. image element array substrates as described in claim 1, wherein the substrate also has the peripheral region outside the active region, this
One insulating layer also has the third contact hole positioned at the peripheral region, the image element array substrates further include:
One periphery cabling is set to the peripheral region of the substrate and has a reference potential, wherein the common electrode through this
Three contact holes are electrically connected to the periphery cabling.
10. image element array substrates as claimed in claim 9, wherein the second insulating layer also has one positioned at the peripheral region
Four contact holes, which has one the 5th contact hole positioned at the peripheral region, and the auxiliary electrode connects through the 4th
Touching window and the 5th contact hole are electrically connected to the common electrode.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107123667A TWI683298B (en) | 2018-07-09 | 2018-07-09 | Pixel array substrate |
| TW107123667 | 2018-07-09 |
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| CN109360829A true CN109360829A (en) | 2019-02-19 |
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| CN110941364A (en) * | 2019-06-14 | 2020-03-31 | 友达光电股份有限公司 | Touch control device |
| CN111007687A (en) * | 2019-05-21 | 2020-04-14 | 友达光电股份有限公司 | Active element substrate and driving method thereof |
| CN112151568A (en) * | 2019-06-28 | 2020-12-29 | 群创光电股份有限公司 | Electronic device |
| CN112259578A (en) * | 2020-03-02 | 2021-01-22 | 友达光电股份有限公司 | Array substrate |
| TWI750763B (en) * | 2019-08-20 | 2021-12-21 | 友達光電股份有限公司 | Electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11646320B2 (en) | 2020-08-03 | 2023-05-09 | Au Optronics Corporation | Pixel array substrate |
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Also Published As
| Publication number | Publication date |
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| CN109360829B (en) | 2020-09-25 |
| TWI683298B (en) | 2020-01-21 |
| TW202006696A (en) | 2020-02-01 |
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