CN113325647B

CN113325647B - Display panel and display device

Info

Publication number: CN113325647B
Application number: CN202110625861.9A
Authority: CN
Inventors: 楼腾刚
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2021-06-04
Filing date: 2021-06-04
Publication date: 2023-04-25
Anticipated expiration: 2041-06-04
Also published as: CN113325647A

Abstract

The invention discloses a display panel and a display device, which belong to the technical field of display, wherein the display panel comprises a first substrate, a plurality of thin film transistors, a plurality of electrode parts and a common electrode are arranged on the substrate of the first substrate, and the thin film transistors comprise a grid electrode, a source electrode, a drain electrode and an active part; in the direction perpendicular to the plane of the substrate, the common electrode comprises a hollowed-out part, and the orthographic projection of the hollowed-out part to the substrate overlaps with the orthographic projection of the thin film transistor to the substrate; the orthographic projection of the electrode part to the substrate at least partially surrounds the orthographic projection of the active part to the substrate, and the orthographic projection of the electrode part to the substrate is not overlapped with the orthographic projection of the channel region of the thin film transistor to the substrate; the orthographic projection of the electrode portion onto the substrate at least partially overlaps with the orthographic projection of the gate electrode onto the substrate. The display device comprises the display panel. The invention can solve the problem of light leakage caused by the existence of the hollowed-out part of the public electrode above the grid electrode of the thin film transistor, and is also beneficial to improving the aperture opening ratio of the display panel.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device.

Background

Flat panel displays are one of the most commonly used displays, such as liquid crystal display panels, organic light emitting display panels, plasma display panels, electronic papers, etc. Since the thin film transistor liquid crystal display (TFT-LCD, thin Film Transistor Liquid Crystal Display) has the characteristics of small size, low power consumption, no radiation, etc., it has been rapidly developed in recent years, and is dominant in the current flat panel display market. The liquid crystal panel is one of the most important components in the TFT-LCD, and mainly includes an array substrate and a color film substrate that are aligned together and sandwich liquid crystal molecules therebetween. The array substrate is provided with a thin film transistor array layer, and the color film substrate is provided with a color film layer and a black matrix pattern for shielding light leakage.

However, in the prior art, a certain distance is provided between the array substrate and the color film substrate, and the black matrix pattern needs to cover a larger area to prevent light leakage, so that the aperture ratio of the display panel is easily reduced. In addition, the alignment precision of the array substrate and the color film substrate during box forming is difficult to control accurately, so that the relative positions of the array substrate and the color film substrate during box forming are easy to deviate, and partial areas of the metal layers in the array substrate are exposed due to inaccurate alignment. For example, after the cell is shifted, the gate of the thin film transistor on the array substrate is partially exposed, so that an electric field is generated between the exposed gate of the thin film transistor and other conductive structures (such as a pixel electrode or a common electrode of a transparent conductive electrode), and the generated electric field easily influences the deflection of liquid crystal molecules, so that a light leakage phenomenon occurs in the exposed gate region. Although the light leakage phenomenon occurring when the alignment deviation is solved by increasing the area of the black matrix pattern, this approach may further decrease the aperture ratio of the display panel due to further increasing the area of the black matrix pattern.

Therefore, the present invention provides a display panel and a display device that can solve the problem of light leakage caused by misalignment of the case and avoid reducing the aperture ratio of the display panel, and is a technical problem to be solved by those skilled in the art.

Disclosure of Invention

In view of this, the present invention provides a display panel and a display device, so as to solve the problem in the prior art that the alignment accuracy of the array substrate and the color film substrate is difficult to precisely control when the array substrate and the color film substrate are in a box, and the relative position is easy to deviate, so that a light leakage phenomenon occurs.

The invention discloses a display panel, which comprises a first substrate; the first substrate at least comprises a substrate, a plurality of thin film transistors and a plurality of electrode parts, wherein the thin film transistors are arranged on the substrate, and each thin film transistor comprises a grid electrode, a source electrode, a drain electrode and an active part; the first substrate further comprises a common electrode, the common electrode comprises a hollowed-out part in the direction perpendicular to the plane of the substrate, and the orthographic projection of the hollowed-out part to the substrate overlaps with the orthographic projection of the thin film transistor to the substrate; the orthographic projection of the electrode part to the substrate at least partially surrounds the orthographic projection of the active part to the substrate, and the orthographic projection of the electrode part to the substrate is not overlapped with the orthographic projection of the channel region of the thin film transistor to the substrate; the orthographic projection of the electrode portion onto the substrate at least partially overlaps with the orthographic projection of the gate electrode onto the substrate.

Based on the same inventive concept, the invention also discloses a display device, which comprises the display panel.

Compared with the prior art, the display panel and the display device provided by the invention have the advantages that at least the following effects are realized:

the display panel at least comprises a first substrate, wherein a plurality of thin film transistors and a plurality of electrode parts are arranged on the substrate of the first substrate, and the thin film transistors comprise grid electrodes, source electrodes, drain electrodes and active parts. The first substrate further comprises a common electrode, the common electrode comprises a hollowed-out portion, the hollowed-out portion can penetrate through the common electrode along the thickness direction of the common electrode, orthographic projection of the hollowed-out portion on the substrate overlaps orthographic projection of the thin film transistor on the substrate, namely the common electrode is provided with the hollowed-out portion which can at least partially expose the area where the thin film transistor is located. The display panel further comprises an electrode part, the orthographic projection of the electrode part to the substrate at least partially surrounds the orthographic projection of the active part to the substrate, the orthographic projection of the electrode part to the substrate and the orthographic projection of the channel region of the thin film transistor to the substrate are not overlapped, the potential of the electrode part can be prevented from influencing the channel region of the thin film transistor, leakage current is prevented from increasing, or characteristic drift of the thin film transistor is prevented from being caused, and further the performance of the thin film transistor is prevented from being influenced by the potential of the electrode part. The invention also provides that the orthographic projection of the electrode part to the substrate and the orthographic projection of the grid electrode to the substrate are at least partially overlapped, so that an overlapping area exists between the orthographic projection of the electrode part to the substrate and the orthographic projection of the grid electrode to the substrate, and the problem of light leakage caused by the existence of the hollowed-out part of the public electrode above the grid electrode of the thin film transistor can be solved. According to the invention, the electrode part shields the electric field possibly generated between the grid electrode of the thin film transistor and other conductive layers, so that the light leakage phenomenon of the display panel is avoided, the display quality of the display panel is improved, the black matrix layer of the display panel is not required to be too large, and the aperture ratio of the display panel is improved.

Of course, it is not necessary for any one product to practice the invention to achieve all of the technical effects described above at the same time.

Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic view showing a partial cross-sectional structure of a liquid crystal display panel according to the related art;

FIG. 2 is a schematic view showing another partial cross-sectional structure of a liquid crystal display panel according to the related art;

fig. 3 is a schematic plan view of a display panel according to an embodiment of the present invention;

FIG. 4 isbase:Sub>A schematic view of the cross-sectional structure in the direction A-A' in FIG. 3;

FIG. 5 is a schematic view of a partial cross-sectional structure of a first substrate and a second substrate opposite to each other according to an embodiment of the present invention;

fig. 6 is a schematic plan view of another display panel according to an embodiment of the present invention;

fig. 7 is a schematic plan view of a combination of the structure of the first substrate illustrated in fig. 3 and a black matrix layer on one side of the second substrate;

fig. 8 is a schematic view showing another planar structure in which the structure of the first substrate illustrated in fig. 3 is combined with a black matrix layer on one side of the second substrate;

Fig. 9 is a schematic view showing another planar structure in which the structure of the first substrate illustrated in fig. 3 is combined with a black matrix layer on one side of the second substrate;

FIG. 10 is a schematic diagram of a stacked structure of the electrode portion and the data line in FIG. 9;

fig. 11 is a schematic view showing another planar structure in which the structure of the first substrate illustrated in fig. 3 is combined with a black matrix layer on one side of the second substrate;

FIG. 12 is a schematic diagram of a stacked structure of the electrode portion and the data line in FIG. 11;

FIG. 13 is a schematic view showing a sectional structure in the direction B-B' in FIG. 3;

FIG. 14 is a schematic view of another cross-sectional structure in the direction B-B' in FIG. 3;

FIG. 15 is a schematic view of another cross-sectional structure in the direction B-B' in FIG. 3;

FIG. 16 is a schematic view of another cross-sectional structure in the direction B-B' in FIG. 3;

FIG. 17 is a schematic view of another cross-sectional structure in the direction B-B' in FIG. 3;

FIG. 18 is a schematic view of another cross-sectional structure in the direction B-B' in FIG. 3;

fig. 19 is a schematic view of another planar structure of a display panel according to an embodiment of the present invention;

FIG. 20 is a schematic view of the cross-sectional structure in the direction C-C' of FIG. 19;

FIG. 21 is a schematic view of another cross-sectional structure in the direction C-C' in FIG. 19;

FIG. 22 is a schematic view of another cross-sectional structure taken in the direction C-C' in FIG. 19;

FIG. 23 is a schematic view of another cross-sectional structure in the direction C-C' in FIG. 19;

FIG. 24 is a schematic view of another cross-sectional structure taken in the direction C-C' in FIG. 19;

FIG. 25 is a schematic view of another cross-sectional structure in the direction C-C' in FIG. 19;

FIG. 26 is a schematic view of another cross-sectional structure taken in the direction C-C' in FIG. 19;

FIG. 27 is a schematic view of another cross-sectional structure in the direction C-C' in FIG. 19;

fig. 28 is a schematic plan view of another display panel according to an embodiment of the present invention;

FIG. 29 is a schematic view of another cross-sectional structure taken in the direction C-C' in FIG. 19;

FIG. 30 is a schematic view of another cross-sectional structure taken in the direction C-C' in FIG. 19;

FIG. 31 is a schematic view of another cross-sectional structure in the direction C-C' in FIG. 19;

FIG. 32 is a schematic view of another cross-sectional structure in the direction C-C' in FIG. 19;

FIG. 33 is a schematic view of another cross-sectional structure in the direction B-B' in FIG. 3;

fig. 34 is a schematic plan view of a display device according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.

The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

In the related art, as shown in fig. 1 and 2, fig. 1 is a schematic view of a partial cross-sectional structure of a related art liquid crystal display panel, and fig. 2 is a schematic view of another partial cross-sectional structure of a related art liquid crystal display panel, the liquid crystal display panel generally includes at least an array substrate 10' and a color film substrate 20' disposed opposite to each other, and a liquid crystal layer 30' disposed between the array substrate 10' and the color film substrate 20 '. The array substrate 10' includes a first substrate 101', scan lines and data lines on the first substrate 101', and a sub-pixel region (not shown) defined by the intersection of the scan lines and the data lines. Wherein, the sub-pixel comprises a thin film transistor and a pixel electrode pixel' positioned above the thin film transistor. Grid electrode T of thin film transistor _G ' electrically connected to the scan line, one of the source/drain electrodes is electrically connected to the data line, and the other source/drain electrode is electrically connected to the pixel electrode (not shown). The color film substrate 20 'includes a second substrate 201', color resistors 202 'arranged in an array on the second substrate 201', and black matrix layers 203 'arranged between the color resistors 202' are spaced apart from each other. The black matrix layer 203' on the color film substrate 20' corresponds to the scanning lines and the data lines on the array substrate 10' and the regions of the thin film transistors, so as to prevent light leakage between the regions where the adjacent sub-pixels are located, and influence the display quality. Wherein, the thin film transistor is used as a switching device of the sub-pixel in the display panel, is connected to the grid scanning circuit by the scanning line, is connected to the integrated circuit chip (IC) by the data line, and applies data voltage to the pixel electrode by the data line, so that the pixel electrode pixel' and the common electrode comAn electric field is formed between the liquid crystal layer 30' and the liquid crystal molecules of the liquid crystal layer deflect in the electric field, so that whether light is emitted or not is controlled, and display of the display panel is realized.

In the related art, the alignment accuracy of the array substrate 10' and the color film substrate 20' during the box forming is difficult to be precisely controlled, so that the relative positions of the two substrates during the box forming are easy to deviate, and the grid T of the thin film transistor in the array substrate 10' due to inaccurate alignment is often generated _G ' partially exposed, gate T of thin film transistor _G The upper part of the 'exposed part (M1' region as illustrated in FIGS. 1 and 2) is not shielded by any shielding structure, resulting in a gate T of the thin film transistor _G The 'exposed portion and the pixel electrode pixel' above it (as shown in fig. 2) or the gate T of the thin film transistor _G An electric field (which is simply illustrated by a broken line K ' in fig. 1 and 2) is generated between the ' exposed portion and the common electrode com ' (shown in fig. 1) thereabove, and the generated electric field easily affects the deflection of the liquid crystal molecules, so that the gate electrode T _G The' exposed region exhibits a light leakage phenomenon. Although the light leakage phenomenon occurring at the time of the misalignment can be solved by increasing the area of the black matrix layer 203' (e.g., the black matrix portion corresponding to the increased dotted frame M2' in fig. 1 and 2), this approach may result in a further decrease in the aperture ratio of the display panel due to a further increase in the area of the black matrix layer 203 '.

Based on the above problems, the application provides a display panel and a display device, which can solve the problem of light leakage caused by alignment deviation of a finished box and avoid reducing the aperture opening ratio of the display panel. The specific embodiments of the display panel and the display device proposed in the present application are described in detail below.

Referring to fig. 3 and fig. 4 in combination, fig. 3 isbase:Sub>A schematic plan view ofbase:Sub>A display panel according to an embodiment of the present invention, fig. 4 isbase:Sub>A schematic cross-sectional view ofbase:Sub>A directionbase:Sub>A-base:Sub>A' in fig. 3 (it can be understood that, for clarity of illustrating the structure of the embodiment, fig. 3 only schematically illustrates four sub-pixel regions, fig. 3 is filled with transparency, and fig. 3 only illustratesbase:Sub>A partial plan view ofbase:Sub>A first substrate in the display panel), the display panel 000 according to the embodiment includes the first substrate 10;

the first substrate 10 includes at least a substrate 101, a plurality of thin film transistors T including a gate electrode T disposed on the substrate 101, and a plurality of electrode parts 40 _G Source T _S Drain electrode T _D And an active part T _A The method comprises the steps of carrying out a first treatment on the surface of the The first substrate 10 further comprises a common electrode 50 (not filled in the figure), and in a direction Z perpendicular to the plane of the substrate 101, the common electrode 50 comprises a hollowed-out portion 501, and the orthographic projection of the hollowed-out portion 501 to the substrate 101 overlaps with the orthographic projection of the thin film transistor T to the substrate 101;

the orthographic projection of the electrode portion 40 onto the substrate 101 at least partially surrounds the active portion T _A Orthographic projection onto substrate 101, orthographic projection onto substrate 101 of electrode portion 40 and channel region T of thin film transistor T _CA Orthographic projections onto the substrate 101 do not overlap; channel region T of thin film transistor T _CA Refers to an active portion T of a thin film transistor T _A And gate T _G An overlapping region;

orthographic projection of electrode portion 40 onto substrate 101 and gate T _G The orthographic projections onto the substrate 101 at least partially overlap.

Specifically, the display panel 000 provided in this embodiment may be a liquid crystal display panel, where the display panel 000 includes at least the first substrate 10, and optionally, the first substrate 10 may be an array substrate of the display panel 000, for setting an array of thin film transistors T, a scan line G, a data line S, and pixel electrodes 60, a common electrode 50, and so on. The first substrate 10 of the present embodiment includes at least a substrate 101, and the substrate 101 is used as a carrier substrate. A plurality of thin film transistors T and a plurality of electrode portions 40 are provided on a substrate 101, wherein the thin film transistors T include a gate electrode T _G Source T _S Drain electrode T _D And an active part T _A . Optionally, the scan line G and the data line S on the substrate 101 are cross-insulated to define a region where the sub-pixel is located; wherein the sub-pixel comprises a thin film transistor T and a pixel electrode 60 above the thin film transistor T, and a gate electrode T of the thin film transistor T _G Is electrically connected with the scanning line G and the source electrode T _S Is electrically connected with the data line S, the drain electrode T _D Is electrically connected to the pixel electrode 60. The first substrate 10 further includes a common electrode 50 perpendicular to the liner Alternatively, the common electrode 50 may be located on a side of the electrode part 40 remote from the substrate 101 in the direction Z of the plane in which the bottom 101 lies, i.e., the common electrode 50 is located above the electrode part 40. The common electrode 50 includes a hollowed-out portion 501, and the hollowed-out portion 501 may penetrate through the common electrode 50 along a thickness direction of the common electrode 50. The front projection of the hollowed-out portion 501 onto the substrate 101 overlaps with the front projection of the thin film transistor T onto the substrate 101, i.e. the common electrode 50 has the hollowed-out portion 501 at least partially exposing the region where the thin film transistor T is located, alternatively, the common electrode 50 has the gate T at least partially exposing the thin film transistor T _G The hollowed-out part 501 of the area is located.

The display panel 000 of the present embodiment further includes an electrode portion 40, and an orthographic projection of the electrode portion 40 onto the substrate 101 at least partially surrounds the active portion T _A Orthographic projection onto the substrate 101, i.e. the electrode portion 40 may be in a ring or semi-ring shape or other structure surrounding the active portion T of the thin film transistor T _A Active portion T of thin film transistor T _A May be any of semiconductor silicon and oxide semiconductor. That is, the thin film transistor T of the present embodiment may be a silicon transistor, and the silicon may be polysilicon deposited by a low temperature method, that is, LTPS (Low Temperature Poly-silicon) or low temperature polysilicon, and the thin film transistor T may also be an oxide semiconductor transistor, and an oxide semiconductor material, such as amorphous indium gallium zinc oxide, that is, IGZO (Indium Gallium Zinc Oxide), which may be selectively set according to the design requirements of the display panel when implemented. The present embodiment further provides the orthographic projection of the electrode portion 40 onto the substrate 101 and the channel region T of the thin film transistor T _CA The orthographic projections onto the substrate 101 do not overlap, i.e. the orthographic projection of the electrode portion 40 onto the substrate 101 surrounds the channel region T of the thin film transistor T _CA Is disposed toward the periphery of the orthographic projection of the substrate 101, and the electrode portion 40 is close to the channel region T of the thin film transistor T _CA One side edge F1 and the channel region T of the thin film transistor T _CA The front projection of the edge F2 on the side close to the electrode portion 40 on the substrate 101 is not in contact, i.e., the distance between the edge F1 and the edge F2 is greater than 0 in the direction parallel to the plane of the substrate 101 (as shown in fig. 3 and 4). The present embodiment provides orthographic projection of the electrode portion 40 onto the substrate 101 and the channel region T of the thin film transistor T _CA Toward the substrate 101The orthographic projections do not overlap, and the potential of the electrode portion 40 can be prevented from affecting the channel region T of the thin film transistor T _CA The leakage current is increased or the characteristic drift of the thin film transistor T is prevented, and the performance of the thin film transistor T is further affected by the potential of the electrode portion 40.

The embodiment also provides the orthographic projection of the electrode portion 40 onto the substrate 101 and the gate electrode T _G The front projection onto the substrate 101 at least partially overlaps, so that the front projection of the electrode portion 40 onto the substrate 101 can be made to coincide with the gate T _G The overlapping area exists in the orthographic projection to the substrate 101, and the problem of the grid electrode T of the thin film transistor T can be solved _G Light leakage caused by the existence of the hollowed-out portion 501 of the upper common electrode 50, the hollowed-out portion 501 of the common electrode 50 enables the gate electrode T of the thin film transistor T to be _G Is not shielded by the shielding structure above a partial region of the thin film transistor T, thereby facilitating the exposure of the grid electrode T of the thin film transistor T _G An electric field is formed between the pixel electrode 60 and other conductive layers of the display panel 000 to affect the deflection of liquid crystal molecules of a liquid crystal layer (not shown in fig. 4) above the first substrate 10, thereby generating a light leakage phenomenon and affecting the display effect.

The present embodiment shields the gate electrode T of the thin film transistor T by the electrode portion 40 _G And the electric field possibly generated between the conductive layer and other conductive layers, so that the light leakage phenomenon of the display panel 000 is avoided, and the display quality of the display panel 000 is improved. As shown in fig. 5, fig. 5 is a schematic diagram of a partial cross-sectional structure of the first substrate and the second substrate provided by the embodiment of the present invention, where after the electrode portion 40 is provided to shield an electric field, even if the first substrate 10 used as an array substrate and the second substrate 20 used as a color film substrate deviate during alignment, the black matrix layer 203 on the second substrate 20 side does not need to be too large due to the shielding effect of the electrode portion 40, which is further beneficial to improving the aperture ratio of the display panel 000.

Alternatively, as shown in fig. 3 and 4, the common electrode 50 may include a hollow portion 501 having a hole structure, and when the pixel electrode 60 of the display panel 000 is located on the side of the common electrode 50 away from the substrate 101 (as shown in fig. 4), the hollow portion is used to form a via hole to realize the drain electrode T of the thin film transistor T _D Is electrically connected with the pixelThe electrode 60 is electrically connected, and the hole-shaped hollowed-out portion 501 of the common electrode 50 at least partially exposes the area where the thin film transistor T is located. It should be understood that fig. 4 of the present embodiment only illustrates the pixel electrode 60 on the side of the common electrode 50 away from the substrate 101, but the present invention is not limited to this structure, and the pixel electrode 60 may be located on the side of the common electrode 50 close to the substrate 101 in practical implementation.

Alternatively, as shown in fig. 4 and fig. 6, fig. 6 is a schematic plan view of another plane structure of a display panel according to an embodiment of the present invention, in this embodiment, the common electrode 50 may be divided into a plurality of block structures, and the plurality of block structures divided at this time may be multiplexed into a touch electrode for use, and the hollowed-out portion 501 may include a first hollowed-out portion 5011 and a second hollowed-out portion 5012, where the first hollowed-out portion 5011 may be a hole structure for setting a via hole to realize the drain electrode T of the thin film transistor T _D The second hollowed-out portion 5012 is in a strip structure and is used for separating a plurality of block-shaped touch electrodes to realize a touch function when the common electrode 50 is reused as a touch electrode. Optionally, the second hollowed-out portion 5012 of the strip structure may at least partially expose the area where the thin film transistor T is located.

In this embodiment, the shape of the hollowed-out portion 501 is not particularly limited, and in a specific implementation, the shape of the hollowed-out portion 501 may be set according to a specific application of the common electrode 50, and only the requirement that the front projection of the hollowed-out portion 501 onto the substrate 101 and the front projection of the thin film transistor T onto the substrate 101 have overlapping areas is satisfied.

It should be noted that fig. 3 to fig. 6 of the present embodiment only illustrate the structure of the display panel 000, and in implementation, the structure of the display panel 000 may also include other structures capable of achieving a display effect, such as each insulating layer, a gate driving circuit at the periphery of the display area, a color blocking structure at one side of the color film substrate, etc., and in implementation, the structure of the liquid crystal display panel in the related art may be referred to for understanding, and the description of the present embodiment is omitted herein.

It should be further noted that, fig. 3 and fig. 6 of this embodiment only illustrate the specific structure around the tft T for clarity, so that the size of the tft T is drawn larger, but the actual size of the tft T is not indicated, and the pixel electrode 60 in fig. 3 and fig. 6 also does not indicate the actual shape, and in specific implementation, the actual shape of the pixel electrode 60 may be a comb-tooth structure (as shown in fig. 4, not illustrated in fig. 3), and the actual occupied size of the tft T in the display panel is smaller, so that the area of the sub-pixel opening area, i.e., the area where the pixel electrode 60 is located, is ensured to be larger, so as to achieve the effect of improving the aperture ratio of the display panel 000.

It will be appreciated that the position of the film layer of the electrode portion 40 is not specifically limited, the film layer of the electrode portion 40 may be located between the common electrode 50 and the pixel electrode 60, and insulating layers (not shown) are disposed between the electrode portion 40 and the common electrode 50 and between the electrode portion 40 and the pixel electrode 60, respectively, or the film layer of the electrode portion 40 may be located above the same insulating layer (not shown) as the common electrode 50, i.e. the lower surfaces of the electrode portion 40 and the common electrode 50 are directly contacted with the same insulating layer (as shown in fig. 4), the optional electrode portion 40 and the common electrode 50 may be overlapped or not overlapped, and only the electrode portion 40 and the common electrode 50 are not overlapped or not contacted with each other in fig. 4, or other arrangements may be adopted, and the embodiment of fig. 4 is not specifically limited, but only illustrates the position of the film layer of one electrode portion 40, but also can be selectively disposed according to practical requirements, in particular embodiments, only the requirement is satisfied that the electrode portion 40 at least partially surrounds the active portion T in a forward projection onto the substrate _A Orthographic projection onto substrate 101, orthographic projection onto substrate 101 of electrode portion 40 and channel region T of thin film transistor T _CA The front projection onto the substrate 101 does not overlap, and the front projection of the electrode portion 40 onto the substrate 101 and the gate electrode T _G The orthographic projections onto the substrate 101 may at least partially overlap, and this embodiment will not be described in detail.

In some alternative embodiments, please continue to refer to fig. 3-6, in this embodiment, the material of the electrode portion 40 disposed in the display panel 000 includes a metal material.

The embodiment illustrates that the electrode portion 40 may be made of metal, and the electrode portion 40 made of metal may also have a light shielding effect, so that the electrode portion 40 may shield the gate electrode T of the thin film transistor T _G The electric field possibly generated between the electrode part 40 and other conductive layers can avoid the light leakage phenomenon of the display panel 000, so that the display quality of the display panel 000 can be improved, the electrode part 40 can be made of a shading metal material, and even if the light leakage phenomenon exists, the electrode part 40 can be directly shaded in the area where the light leakage is possibly generated, namely, the channel area T surrounding the thin film transistor T _CA And with grid T _G Overlapping area for solving the problem of exposed grid electrode T of thin film transistor T _G An electric field is formed between the structure of the other conductive layer of the display panel 000 to affect the deflection of the liquid crystal molecules of the liquid crystal layer above the first substrate 10, thereby generating a problem of light leakage.

In some alternative embodiments, please refer to fig. 3, fig. 5 and fig. 7 in combination, fig. 7 is a schematic plan view of the combination of the structure of the first substrate illustrated in fig. 3 and the black matrix layer on the side of the second substrate (for clarity of illustrating the technical solution of the present embodiment, the structure of the second substrate is not illustrated in fig. 3, only the structure of the black matrix layer is illustrated on the side of the second substrate in fig. 7, the rest of the structures are not illustrated, and the common electrode structure on the side of the first substrate is removed, transparency filling is performed, and other structures on the side of the second substrate can be understood with reference to the cross-sectional view of fig. 5), in this embodiment, the display panel 000 further includes a second substrate 20 disposed opposite to the first substrate 10, and the second substrate 20 includes a black matrix layer 203; wherein the orthographic projection of the black matrix layer 203 onto the substrate 101 covers the active portion T _A Orthographic projection onto the substrate 101, optionally orthographic projection of the black matrix layer 203 onto the substrate 101 also covers at least orthographic projection of the scan lines G and the data lines S onto the substrate 101.

The embodiment illustrates that the display panel 000 further includes a second substrate 20 disposed opposite to the first substrate 10, where the second substrate 20 may be a color film substrate, and the second substrate 20 includes at least a second substrate 201, and a black matrix layer 203 and a color resistor 202 disposed on the second substrate 201, where the orthographic projection of the black matrix layer 203 to the substrate 101 at least covers the orthographic projection of the scan line G and the data line S to the substrate 101, so as to prevent light leakage between adjacent sub-pixels and affect the display quality. And the orthographic projection of the black matrix layer 203 onto the substrate 101 also covers at least the active portion T _A Orthographic projection onto the substrate 101, since orthographic projection of the electrode portion 40 of the present embodiment onto the substrate 101 at least partially surrounds the active portion T _A Orthographic projection onto the substrate 101, i.e. the electrode portion 40 may be in a ring or semi-ring shape or other structure surrounding the active portion T of the thin film transistor T _A Electrode portion 40 and channel region T of thin film transistor T _CA There is no overlapping area, so at least the active portion T of the thin film transistor T can be covered by orthographic projection of the black matrix layer 203 onto the substrate 101 on the side of the second substrate 20 _A The black matrix layer 203 can shield stray light between sub-pixels by forward projection onto the substrate 101, thereby reducing light exposure to the active portion T of the thin film transistor T _A Influence of the properties.

Alternatively, since the electrode portion 40 of the present embodiment may be made of a metal light shielding material, that is, the electrode portion 40 may be expanded to be light shielding, only the region where the electrode portion 40 is located on the first substrate 10 side is needed, and the black matrix layer 203 at the position corresponding to the region where the thin film transistor T is located on the second substrate 20 side may be hollowed (not shown in the drawings) to further increase the aperture ratio. However, in order to better ensure the performance of the thin film transistor T, the size of the black matrix layer 203 is set to be at least enough that the orthographic projection of the black matrix layer 203 onto the substrate 101 covers the active portion T of the thin film transistor T _A Orthographic projection onto the substrate 101.

Optionally, please refer to fig. 3, fig. 5 and fig. 8 in combination, fig. 8 is another schematic plan view of the combination of the structure of the first substrate and the black matrix layer on the second substrate side illustrated in fig. 3 (for clarity in illustrating the technical scheme of the embodiment, the structure of the second substrate is not illustrated in fig. 3, only the structure of the black matrix layer is illustrated on the second substrate side illustrated in fig. 8, the other structures are not illustrated, and the common electrode structure on the first substrate side is removed, transparency filling is performed, and the other structures on the second substrate side can be understood with reference to the cross-sectional view of fig. 5), in this embodiment, the orthographic projection of the black matrix layer 203 onto the substrate 101 may also completely cover the orthographic projection of the area of the thin film transistor T onto the substrate 101, and the annular surrounding the active portion T _A The electrode part 40 can be opened, namely the electrode part 40 can be etched and divided into a plurality of unconnected subsectionsThe opening position (40A position in fig. 8) is a position where the black matrix layer 203 exceeds the area where the thin film transistor T is located, that is, even if the opening of the electrode portion 40 is disconnected at the position where the black matrix layer 203 completely covers the thin film transistor T, the light leakage problem will not occur in this embodiment, which is beneficial to reducing the setting area of the conductive structure in the display panel 000.

In some alternative embodiments, please continue to refer to fig. 3, in this embodiment, two adjacent electrode portions 40 of the region where any two adjacent thin film transistors T are located are not connected independently.

The present embodiment explains that each region where the thin film transistor T is located may be correspondingly provided with one electrode portion 40, and two adjacent electrode portions 40 in any adjacent region where two thin film transistors T are located may be of mutually independent and unconnected structures, so that the design difficulty may be reduced.

In some alternative embodiments, please continue to refer to fig. 3, 5 and 8 in combination, in this embodiment, each electrode portion 40 includes at least a first subsection 401 and a second subsection 402 that are not connected independently of each other.

The present embodiment illustrates that the electrode portion 40 may be an active portion T surrounding only a portion of the thin film transistor T _A The electrode part 40 may be configured to have a non-annular structure, and may include at least a first subsection 401 and a second subsection 402 that are independent from each other, and the first subsection 401 and the second subsection 402 may be disconnected through an opening, so as to achieve that the opening is disconnected in a region (e.g., a 40A position where the black matrix layer 203 is sufficiently large in fig. 8) where shielding of the electrode part 40 is not required, which can achieve an effect of reducing the material usage amount of the electrode part 40.

In some alternative embodiments, please refer to fig. 3, fig. 5 and fig. 9 in combination, fig. 9 is another schematic plane structure of the combination of the structure of the first substrate and the black matrix layer on the second substrate side illustrated in fig. 3 (for clarity of illustration of the technical scheme of the embodiment, the structure of the second substrate is not illustrated in fig. 3, only the structure of the black matrix layer is illustrated on the second substrate side in fig. 9, the rest of the structures are not illustrated, and the common electrode structure on the first substrate side is removed, and transparency filling is performed, see fig. 5Other structures on the second substrate side are understood in the cross-sectional view), in this embodiment, the display panel 000 includes a plurality of data lines S, and optionally, a plurality of scan lines G, and a source T of the thin film transistor T _S Is electrically connected with the data line S; each electrode portion 40 includes at least a first opening 40B;

the front projection of the first opening 40B onto the substrate 101 at least partially overlaps with the front projection of the data line S onto the substrate 101.

In this embodiment, it is explained that an electrode portion 40 may be disposed in the area where each thin film transistor T is disposed, where each electrode portion 40 includes at least a first opening 40B, where the front projection of the first opening 40B onto the substrate 101 and the front projection of the data line S onto the substrate 101 overlap at least partially, and optionally, as shown in fig. 10, fig. 10 is a schematic diagram of a stacked structure of the electrode portion 40 and the data line S in fig. 9, the front projection of the first opening 40B onto the substrate 101 may overlap with the front projection of the data line S onto the substrate 101, that is, the edge of the front projection of the first opening 40B onto the substrate 101 contacts with the edge of the front projection of the data line S onto the substrate 101 at the position, that is, the electrode portion 40 may be disposed in a non-annular structure, and the first opening 40B may be disposed at the overlapping position of the data line S to disconnect the annular electrode portion 40, because the data line S itself is made of a metal shielding material, and may also play a role of shielding an electric field, so that the front projection of the first opening 40B onto the substrate 101 and the data line S onto the substrate 101 overlap with the front projection of the data line S onto the substrate 101, that the metal shielding material may be directly disposed at the position where the electrode portion 40 is not required.

Alternatively, as shown in fig. 11 and 12, fig. 11 is a schematic plan view of the combination of the structure of the first substrate and the black matrix layer on the second substrate side illustrated in fig. 3, and fig. 12 is a schematic plan view of the stacked structure of the electrode portion 40 and the data line S in fig. 11, where the front projection of the first opening 40B onto the substrate 101 may overlap only with the front projection of a portion of the data line S onto the substrate 101, that is, the edge of the data line S at the position is still provided with a portion of the electrode portion 40 overlapping therewith, so as to avoid the light leakage phenomenon under the possible offset condition caused by the alignment deviation or the limitation of the process precision, thereby further playing a role of completely shielding light.

In some alternative embodiments, please refer to fig. 3, fig. 13 and fig. 14 in combination, fig. 13 is a schematic cross-sectional structure of the direction B-B 'in fig. 3, fig. 14 is another schematic cross-sectional structure of the direction B-B' in fig. 3 (it is understood that, for clarity of illustrating the structure of the present embodiment, fig. 3 illustrates only four sub-pixel regions schematically, fig. 3 is filled with transparency, and fig. 3 illustrates only a partial planar structure of the first substrate in the display panel, fig. 13 and fig. 14 illustrate structures of the first substrate and the second substrate), the first substrate 10 of the present embodiment includes a substrate 101, and further includes a first metal layer 102, an active layer 103, a second metal layer 104, a third metal layer 105, a first electrode layer 106, and a second electrode layer 107 on one side of the first metal layer 102 away from the substrate 101, the first electrode layer 106 on one side of the second metal layer 104 away from the first metal layer 102, and the second electrode layer 107 on one side of the second electrode layer 106 on the other side of the first substrate 101;

The first electrode layer 106 includes a first electrode 1061, and the second electrode layer 107 includes a second electrode 1071;

grid T _G Located in the first metal layer 102, the active portion T _A Located in the active layer 103, source T _S And drain electrode T _D The electrode portion 40 is located in the second metal layer 104 and the third metal layer 105.

The embodiment illustrates that the first substrate 10 used as the array substrate in the display panel 000 may further include a first metal layer 102, an active layer 103, a second metal layer 104, a third metal layer 105, a first electrode layer 106, and a second electrode layer 107 disposed on the substrate 101, wherein the second metal layer 104 is disposed on a side of the first metal layer 102 away from the substrate 101, optionally the third metal layer 105 is disposed on a side of the second metal layer 104 away from the substrate 101, the first electrode layer 106 is disposed on a side of the second metal layer 104 away from the first metal layer 102, the second electrode layer 107 is disposed on a side of the first electrode layer 106 away from the second metal layer 104, i.e. the second metal layer 104 is disposed above the first metal layer 102, the third metal layer 105 is disposed above the second metal layer 104, the first electrode layer 106 is disposed above the second metal layer 104, and the second electrode layerLayer 107 is over the first electrode layer 106, the gate electrode T of the thin film transistor T _G An active part T of the thin film transistor T is positioned on the first metal layer 102 _A A source electrode T of the thin film transistor T positioned on the active layer 103 _S And drain electrode T _D The electrode portion 40 is located on the second metal layer 104, and the electrode portion 40 for shielding the electric field to solve the light leakage problem is located on the third metal layer 105.

It will be appreciated that the first electrode layer 106 of the present embodiment includes the first electrode 1061, the second electrode layer 107 includes the second electrode 1071, the first electrode 1061 may be used as the pixel electrode 60 in fig. 3, the second electrode 1071 may be used as the common electrode 50 in fig. 3 (as shown in fig. 13), or the first electrode 1061 may be used as the common electrode 50 in fig. 3, the second electrode 1071 may be used as the pixel electrode 60 in fig. 3 (as shown in fig. 14), that is, the common electrode 50 of the display panel 000 and the film layer where the pixel electrode 60 is located may be replaced up and down, so as to realize various different film layer structures of the display panel.

In some alternative embodiments, please continue to refer to fig. 3, 13 and 14, in this embodiment, a first insulating layer 701 is disposed on a side of the first electrode layer 106 near the substrate 101;

the third metal layer 105 and the first electrode layer 106 are both in direct contact with the first insulating layer 701, and the first electrode 1061 and the electrode portion 40 do not overlap in the direction Z perpendicular to the plane of the substrate 101.

The present embodiment explains that the second electrode layer 107 is located on the side of the first electrode layer 106 away from the second metal layer 104, and the side of the first electrode layer 106 close to the substrate 101 is provided with the first insulating layer 701 for insulating isolation. The surfaces of the electrode portion 40 of the third metal layer 105 and the first electrode 1061 of the first electrode layer 106 facing the substrate 101 in this embodiment may both be in direct contact with the first insulating layer 701, i.e. when the film structure on the first substrate 10 side is fabricated, the first electrode layer 106 may be deposited first and etched to form the first electrode 1061, then the third metal layer 105 may be deposited and etched to form the electrode portion 40 above the first insulating layer 701; alternatively, the third metal layer 105 may be deposited first and etched to form the electrode portion 40, and then the first electrode layer 106 may be deposited and etched to form the first electrode 1061 (the process step is not specifically limited in this embodiment), where the first electrode 1061 may be the pixel electrode 60 (the pixel electrode 60 is below the common electrode 50 as shown in fig. 13), or the first electrode 1061 may be the common electrode 50 (the pixel electrode 60 is above the common electrode 50 as shown in fig. 14). In this embodiment, the third metal layer 105 and the first electrode layer 106 are both in direct contact with the first insulating layer 701, which is beneficial to reducing the thickness of the film layer of the display panel, and avoiding the thickness of the display panel from being affected by the added third metal layer 105. In this embodiment, the first electrode 1061 and the electrode portion 40 are insulated from each other in the direction Z perpendicular to the plane of the substrate 101, and since the common electrode 50 and the pixel electrode 60 are made of ITO (indium tin oxide semiconductor transparent conductive film, indium Tin Oxides), the first electrode 1061 is not in contact with the electrode portion 40, so that the electrode portion 40 does not occupy the light-transmitting area of the first electrode 1061 when the electrode portion 40 is made of metal, and further, the light transmittance of the display panel 000 is prevented from being affected by the arrangement of the electrode portion 40.

Alternatively, as shown in fig. 15 and 16, fig. 15 is a schematic view of another cross-sectional structure in the direction B-B 'in fig. 3, and fig. 16 is a schematic view of another cross-sectional structure in the direction B-B' in fig. 3, the display panel 000 of the embodiment may further include an insulating cover layer 702 (OC layer), and the surfaces of the electrode portion 40 of the third metal layer 105 and the first electrode 1061 of the first electrode layer 106 facing the substrate 101 may be both in direct contact with the insulating cover layer 702, where the insulating cover layer 702 is used to protect the metal film and also helps to improve the flatness of the film. The embodiment explains that the electrode portion 40 and the first electrode 1061 are fabricated on the insulating cover layer 702 with high flatness and in direct contact therewith, which is advantageous for improving the deposition effect during the process.

It can be appreciated that, in manufacturing the film structure on the first substrate 10 side, the first electrode layer 106 may be deposited over the insulating cover layer 702, and etched to form the first electrode 1061, and then the third metal layer 105 may be deposited, and etched to form the electrode portion 40; alternatively, the third metal layer 105 may be deposited first, and etched to form the electrode portion 40, then the first electrode layer 106 may be deposited, and etched to form the first electrode 1061.

In some alternative embodiments, please refer to fig. 3, 17 and 18 in combination, fig. 17 is another schematic cross-sectional structure of the direction B-B 'in fig. 3, fig. 18 is another schematic cross-sectional structure of the direction B-B' in fig. 3 (it is understood that, for clarity of illustrating the structure of the present embodiment, fig. 3 only schematically illustrates four sub-pixel regions, fig. 3 is filled with transparency, and fig. 3 only illustrates a partial planar structure of the first substrate in the display panel, fig. 17 and 18 illustrate structures of the first substrate and the second substrate), in the display panel 000 of the present embodiment, the second electrode layer 107 is provided with the second insulating layer 703 near the substrate 101 side; optionally, the third metal layer 105 is located on a side of the first electrode layer 106 away from the substrate 101, where the third metal layer 105 and the second electrode layer 107 are both in direct contact with the second insulating layer 703, and the second electrode 1071 does not overlap with the electrode portion 40 in a direction Z perpendicular to the plane of the substrate 101.

The present embodiment explains that the second electrode layer 107 is located on the side of the first electrode layer 106 away from the second metal layer 104, and the side of the second electrode layer 107 close to the substrate 101 is provided with the second insulating layer 703 for functioning as insulating and isolating the first electrode layer 106 and the second electrode layer 107. The third metal layer 105 of the present embodiment is located on a side of the first electrode layer 106 away from the substrate 101, i.e. the third metal layer 105 is located above the first electrode layer 106. The surfaces of the electrode portion 40 of the third metal layer 105 and the second electrode 1071 of the second electrode layer 107 facing the substrate 101 may both be in direct contact with the second insulating layer 703, i.e. when the film structure on the first substrate 10 side is fabricated, the second electrode layer 107 may be deposited first and etched to form the second electrode 1071, then the third metal layer 105 may be deposited and etched to form the electrode portion 40 above the second insulating layer 703; alternatively, the third metal layer 105 may be deposited first and etched to form the electrode portion 40, and then the second electrode layer 107 may be deposited and etched to form the second electrode 1071 (the process step is not specifically limited in this embodiment), where the second electrode 1071 may be the pixel electrode 60 (the pixel electrode 60 is above the common electrode 50 as shown in fig. 17), or the second electrode 1071 may be the common electrode 50 (the pixel electrode 60 is below the common electrode 50 as shown in fig. 18). In this embodiment, the third metal layer 105 and the second electrode layer 107 are both in direct contact with the second insulating layer 703, which is favorable for reducing the film thickness of the display panel, and avoids the thickness of the display panel from being affected by the added third metal layer 105. In this embodiment, the second electrode 1071 and the electrode portion 40 are insulated from each other in the direction Z perpendicular to the plane of the substrate 101, and since the common electrode 50 and the pixel electrode 60 are made of ITO (indium tin oxide semiconductor transparent conductive film, indium Tin Oxides), the second electrode 1071 is not in contact with the electrode portion 40, so that the electrode portion 40 does not occupy the light-transmitting area of the second electrode 1071 when the electrode portion 40 is made of metal, and the light transmittance of the display panel 000 is prevented from being affected by the arrangement of the electrode portion 40.

In some alternative embodiments, please refer to fig. 19 and fig. 20, fig. 21, fig. 22, fig. 23 in combination, fig. 19 is another schematic plan view of the display panel provided in the embodiment of the present invention, fig. 20 is a schematic view of a cross-sectional structure of a C-C 'direction in fig. 19, fig. 21 is a schematic view of a cross-sectional structure of a C-C' direction in fig. 19, fig. 22 is a schematic view of a cross-sectional structure of a C-C 'direction in fig. 19, fig. 23 is a schematic view of a cross-sectional structure of a C-C' direction in fig. 19, fig. 19 only schematically illustrates four sub-pixel regions, fig. 19 is filled with transparency, fig. 19 only illustrates a partial plan view of a first substrate in the display panel, fig. 20-23 illustrates a structure of a first substrate and a second substrate, in the embodiment, a third metal layer 105 is located on one side of the first electrode layer 106 near the second electrode layer 107, or a third metal layer 105 is located on one side of the first electrode layer 106 near the second metal layer 104, wherein the portion 40 overlaps with the first electrode 101 in a vertical direction 1061, and the portion of the electrode 101 is in a vertical direction.

The present embodiment explains that the second electrode layer 107 is located on the side of the first electrode layer 106 away from the second metal layer 104, in which case the third metal layer 105 may be located on the side of the first electrode layer 106 close to the second electrode layer 107 (as shown in fig. 21 and 23), the third metal layer 105 may also be located on the side of the first electrode layer 106 close to the second metal layer 104 (as shown in fig. 20 and 22), and the electrode portion 40 is overlapped with the first electrode 1061 to be in direct contact. The electrode portion 40 of the third metal layer 105 and the first electrode 1061 of the first electrode layer 106 in this embodiment may be in direct contact, that is, when the film layer structure on one side of the first substrate 10 is fabricated, as shown in fig. 20, the third metal layer 105 may be deposited on the insulating layer above the second metal layer 104, and etched to form the electrode portion 40, and then the first electrode layer 106 may be directly deposited on the third metal layer 105, and etched to form the first electrode 1061; alternatively, as shown in fig. 21, the first electrode layer 106 may be deposited on the insulating layer above the second metal layer 104, and etched to form the first electrode 1061, then the third metal layer 105 is directly deposited on the first electrode layer 106, and etched to form the electrode portion 40, where the process steps are not specifically limited in this embodiment, the first electrode 1061 may be the common electrode 50 (as shown in fig. 20 and 21, the pixel electrode 60 is above the common electrode 50), or the first electrode 1061 may be the pixel electrode 60, as shown in fig. 22 and 23, the pixel electrode 60 is below the common electrode 50, and the third metal layer 105 is located on a side of the first electrode layer 106 close to the second electrode layer 107 in fig. 23, that is, the first electrode layer 106 is deposited and then the third metal layer 105 is deposited in fig. 23; in fig. 22, the third metal layer 105 is located on the side of the first electrode layer 106 close to the second metal layer 104, i.e. in fig. 22, the third metal layer 105 is deposited first and then the first electrode layer 106 is deposited.

In this embodiment, the third metal layer 105 is disposed on a side of the first electrode layer 106 near the second electrode layer 107, or the third metal layer 105 is disposed on a side of the first electrode layer 106 near the second metal layer 104, and the electrode portion 40 is directly and electrically connected to the first electrode 1061, and since the electrode portion 40 is made of metal, the common electrode 50 and the pixel electrode 60 are generally made of ITO (indium tin oxide semiconductor transparent conductive film, indium Tin Oxides), and the resistivity of ITO is higher than that of metal, and thus the electrode portion 40 made of metal is directly connected to the first electrode 1061 made of ITO in this embodiment, the resistance can be reduced. In this embodiment, the first electrode 1061 is only partially overlapped with the electrode portion 40 in the direction Z perpendicular to the plane of the substrate 101, so that excessive overlapping area of the first electrode 1061 and the electrode portion 40 can be avoided, the light transmittance of the first electrode 1061 is affected by excessive overlapping area of the electrode portion 40 made of metal materials, and the aperture ratio of the display panel is further affected. It is to be understood that the size of the overlapping contact area between the first electrode 1061 and the electrode portion 40 is not limited in this embodiment, and it is only required that the overlapping contact area between the first electrode 1061 and the electrode portion 40 can be electrically connected.

Optionally, as shown in fig. 24-27, fig. 24 is another schematic cross-sectional structure of the C-C 'direction in fig. 19, fig. 25 is another schematic cross-sectional structure of the C-C' direction in fig. 19, fig. 26 is another schematic cross-sectional structure of the C-C 'direction in fig. 19, and fig. 27 is another schematic cross-sectional structure of the C-C' direction in fig. 19, where the display panel 000 of the embodiment may further include an insulating cover 702 (OC layer), where the insulating cover 702 may be located on a side of the second metal layer 104 near the first electrode layer 106, and the insulating cover 702 is used to protect the metal film and also helps to improve the flatness of the film. The embodiment illustrates that the first electrode 1061 is formed on the insulating cover layer 702 with high flatness and is in direct contact with the insulating cover layer, which is advantageous for improving the deposition effect during the process.

It can be understood that, in manufacturing the film structure on the first substrate 10 side, as shown in fig. 24 and 26, the first electrode layer 106 may be deposited over the insulating cover layer 702, and etched to form the first electrode 1061, and then the third metal layer 105 may be deposited directly on the first electrode layer 106, and etched to form the electrode portion 40; alternatively, as shown in fig. 25 and 27, the third metal layer 105 may be deposited over the insulating cover layer 702, and etched to form the electrode portion 40, then the first electrode layer 106 may be directly deposited on the third metal layer 105, and etched to form the first electrode 1061, where in fig. 24 and 25 of this embodiment, the pixel electrode 60 is over the common electrode 50, and in fig. 26 and 27, the pixel electrode 60 is under the common electrode 50, and this embodiment is not limited to the specific process steps, and may be flexibly selected when the specific process is implemented.

In some alternative embodiments, please refer to fig. 20, 21, 24, 25 and 28, fig. 28 is another schematic plan view of a display panel according to an embodiment of the present invention (it is understood that, for clarity of illustration of the structure of this embodiment, fig. 28 only schematically illustrates four sub-pixel regions, fig. 28 is filled with transparency, and fig. 28 only illustrates a part of the plan view structure of the first substrate in the display panel), in this embodiment, the third metal layer 105 is located on a side of the first electrode layer 106 near the second electrode layer 107, or the third metal layer 105 is located on a side of the first electrode layer 106 near the second metal layer 104, where the electrode portion 40 contacts the first electrode 1061, and the first electrode 1061 only partially overlaps the electrode portion 40 in a direction Z perpendicular to the plane of the substrate 101;

when the first electrode 1061 is the common electrode 50 (as shown in fig. 20, 21, 24, and 25), the adjacent two electrode portions 40 are connected to each other (as shown in fig. 28).

The present embodiment explains that when the first electrode 1061 is used as the common electrode 50, the first electrode 1061 and the electrode portion 40 are only partially overlapped (as shown in fig. 20 and 21) in the direction Z perpendicular to the plane in which the substrate 101 is present by providing the electrode portion 40 to be in contact with the first electrode 1061, and at this time, the adjacent two electrode portions 40 can be connected to each other; alternatively, two adjacent electrode portions 40 are connected to each other through a connecting portion 400, and the connecting portion 400 may be disposed on the same layer as the electrode portions 40, so as to facilitate thinning of the display panel. In this embodiment, two adjacent electrode portions 40 are connected to each other, and the overlapping contact between the electrode portion 40 and the first electrode 1061 corresponds to the electrical connection between the electrode portion 40 and the first electrode 1061, i.e. the electrode portion 40 also has the potential signal of the first electrode 1061, so that when the first electrode 1061 is used as the common electrode 50, the resistance of the whole common electrode 50 is further reduced, and the display quality is further improved.

In some alternative embodiments, please refer to fig. 19, fig. 29, fig. 30, fig. 31, fig. 32 in combination, fig. 29 is another schematic cross-sectional structure of the first substrate in fig. 19, fig. 30 is another schematic cross-sectional structure of the first substrate in fig. 19 in the C-C 'direction, fig. 31 is another schematic cross-sectional structure of the first substrate in fig. 19 in the C-C' direction, fig. 32 is another schematic cross-sectional structure of the first electrode layer in fig. 19 (it is understood that, for clarity of illustrating the structure of the present embodiment, fig. 19 only schematically illustrates four sub-pixel regions, fig. 19 is transparent filled, and fig. 19 only illustrates a partial planar structure of the first substrate in the display panel, fig. 29-32 illustrates a structure of the first substrate and the second substrate), in the present embodiment, the third metal layer 105 is located on a side of the second electrode layer 107 close to the first electrode layer 106 (as illustrated in fig. 30 and fig. 32), or the third metal layer 105 is located on a side of the second electrode layer 107 far from the first electrode layer 106 (as illustrated in fig. 29 and fig. 31), wherein the second electrode 1071 is overlapped with the second electrode 10740 in a vertical direction on the second electrode 10740 in the contact portion of the first electrode 1071.

The present embodiment explains that the second electrode layer 107 is located on the side of the first electrode layer 106 away from the second metal layer 104, in which case the third metal layer 105 may be located on the side of the second electrode layer 107 close to the first electrode layer 106 (as shown in fig. 30 and 32), the third metal layer 105 may also be located on the side of the second electrode layer 107 away from the first electrode layer 106 (as shown in fig. 29 and 31), and the electrode portion 40 is overlapped with the second electrode 1071 to be in direct contact. In this embodiment, the electrode portion 40 of the third metal layer 105 and the second electrode 1071 of the second electrode layer 107 may be in direct contact, that is, when the film structure on one side of the first substrate 10 is fabricated, as shown in fig. 29, the second electrode layer 107 may be deposited on the insulating layer above the first electrode layer 106, and the second electrode 1071 is formed by etching, and then the third metal layer 105 is directly deposited on the second electrode layer 107, and the electrode portion 40 is formed by etching; alternatively, as shown in fig. 30, the third metal layer 105 may be deposited on the insulating layer above the first electrode layer 106, and etched to form the electrode portion 40, then the second electrode layer 107 is directly deposited on the third metal layer 105, and etched to form the second electrode 1071, where the process step is not specifically limited, the first electrode 1061 may be the common electrode 50, the second electrode 1071 may be the pixel electrode 60 (as shown in fig. 29 and 30, the pixel electrode 60 is above the common electrode 50), or the first electrode 1061 may be the pixel electrode 60, the second electrode 1071 may be the common electrode 50, as shown in fig. 31 and 32, the pixel electrode 60 is below the common electrode 50, and the third metal layer 105 is located on a side of the second electrode layer 107 away from the first electrode layer 106 in fig. 31, i.e. the second electrode layer 107 is deposited before the third metal layer 105 is deposited in fig. 31; in fig. 32, the third metal layer 105 is located on the side of the second electrode layer 107 near the first electrode layer 106, i.e. in fig. 32, the third metal layer 105 is deposited before the second electrode layer 107 is deposited.

In this embodiment, the third metal layer 105 is disposed on the side of the second electrode layer 107 close to the first electrode layer 106, or the third metal layer 105 is disposed on the side of the second electrode layer 107 far from the first electrode layer 106, and the electrode portion 40 is directly and electrically connected to the second electrode 1071, and since the electrode portion 40 is made of metal, the common electrode 50 and the pixel electrode 60 are generally made of ITO (indium tin oxide semiconductor transparent conductive film, indium Tin Oxides), and the resistivity of ITO is higher than that of metal, and thus the electrode portion 40 made of metal is directly connected to the second electrode 1071 made of ITO in this embodiment, so that the resistance can be reduced. In this embodiment, the second electrode 1071 is only partially overlapped with the electrode portion 40 in the direction Z perpendicular to the plane of the substrate 101, so that excessive overlapping area between the second electrode 1071 and the electrode portion 40 can be avoided, and the light transmittance of the second electrode 1071 is affected by excessive electrode portion 40 made of metal material, thereby affecting the aperture ratio of the display panel. It is to be understood that the size of the area where the second electrode 1071 and the electrode portion 40 overlap and contact is not limited in this embodiment, and it is only required that the second electrode 1071 and the electrode portion 40 overlap and can be electrically connected.

In some alternative embodiments, please continue to refer to fig. 28, 31 and 32, in this embodiment, the third metal layer 105 is located on a side of the second electrode layer 107 close to the first electrode layer 106, or the third metal layer 105 is located on a side of the second electrode layer 107 away from the first electrode layer 106, wherein the electrode portion 40 is in contact with the second electrode 1071, and the second electrode 1071 only partially overlaps the electrode portion 40 in a direction Z perpendicular to the plane of the substrate 101;

when the second electrode 1071 is the common electrode 50 (as shown in fig. 31 and 32), the adjacent two electrode parts 40 are connected to each other.

The present embodiment explains that when the second electrode 1071 is used as the common electrode 50, the second electrode 1071 and the electrode portion 40 are only partially overlapped (as shown in fig. 31 and 32) in the direction Z perpendicular to the plane in which the substrate 101 is present by providing the electrode portion 40 to be in contact with the second electrode 1071, and at this time, the adjacent two electrode portions 40 can be connected to each other; optionally, two adjacent electrode portions 40 are also connected to each other through a connection portion 400, and the connection portion 400 may be disposed on the same layer as the electrode portions 40, so as to facilitate thinning of the display panel. It will be appreciated that the electrode portion 40 of the present embodiment is in contact with the second electrode 1071, and the second electrode 1071 is used as the common electrode 50, the structure of the interconnection between the adjacent two electrode portions 40 is not shown in the drawings, but the connection manner of the adjacent two electrode portions 40 may refer to the structure shown in fig. 28, except that the electrode portion 40 is in contact with the first electrode 1061 used as the common electrode in fig. 28, and the electrode portion 40 is in contact with the second electrode 1071 used as the common electrode in the present embodiment, but the structure of the interconnection between the adjacent two electrode portions 40 is the same, and the connection portion 400 is used.

In this embodiment, two adjacent electrode portions 40 are connected to each other, and the overlapping contact between the electrode portion 40 and the second electrode 1071 corresponds to the electrical connection between the electrode portion 40 and the second electrode 1071, i.e. the electrode portion 40 also has the potential signal of the second electrode 1071, so that when the second electrode 1071 is used as the common electrode 50, the resistance of the whole common electrode 50 is further reduced, and the display quality is further improved.

In some alternative embodiments, please continue to refer to fig. 28, in this embodiment, the display panel 000 includes a plurality of scan lines G and a plurality of data lines S, and the connection portion 400 at least partially overlaps the scan lines G and/or the data lines S in a direction Z perpendicular to the plane of the substrate 101.

The present embodiment further illustrates that the connection portion 400 connecting the adjacent two electrode portions 40 to each other may be disposed such that the connection portion 400 at least partially overlaps the scan line G and/or the data line S in the direction Z perpendicular to the plane of the substrate 101, i.e., the connection portion 400 may at least partially overlap the scan line G or the connection portion 400 may at least partially overlap the data line S in the direction Z perpendicular to the plane of the substrate 101, or the connection portion 400 may overlap both the scan line G and the data line S (as shown in fig. 28), respectively, so that the aperture ratio of the display panel 000 may be prevented from being affected as much as possible when the electrode portions 40 are made of metal materials.

In some alternative embodiments, please continue to refer to fig. 3 and fig. 13-32, the thin film transistor T in this embodiment may be a transistor with a bottom gate structure, i.e. the active layer 103 is located between the first metal layer 102 and the second metal layer 104.

The present embodiment illustrates that the active layer 103 of the display panel 000 is located between the first metal layer 102 and the second metal layer 104, i.e. in the direction Z perpendicular to the plane of the substrate 101, the active portion T of the thin film transistor T _A Is positioned at the grid T _G And source T _S Drain electrode T _D Between them. The present embodiment explains that the gate electrode T of the thin film transistor T is shielded by the electrode portion 40 _G The structure that may generate an electric field with other conductive layers, and thus avoid the light leakage phenomenon of the display panel 000 may be applied to the display panel 000 including the thin film transistor T with a bottom gate structure, and for the thin film transistor with a top gate structure (i.e., the gate electrode is located between the active portion and the source/drain electrode), the gate electrode with the top gate structure may be covered by the common electrode layer disposed on the whole surface, so as to solve the light leakage problem, which is not described herein in detail.

In some alternative embodiments, please refer to fig. 3 and 33 in combination, fig. 33 is a schematic diagram illustrating another cross-sectional structure in the direction B-B' in fig. 3, and in this embodiment, the third metal layer 105 is located between the first metal layer 102 and the substrate 101.

The present embodiment further explains that the third metal layer 105 in the above embodiment may be disposed between the first metal layer 102 and the substrate 101, that is, the electrode portion 40 may be located at the gate electrode T of the thin film transistor T _G And the substrate 101, since the display panel 000 is a liquid crystal display surfaceWhen the panel does not emit light, the working principle is that the rotation of liquid crystal molecules of the liquid crystal layer is controlled by applying driving voltage on the array substrate and the color film substrate, the polarization state of light rays of the backlight module is changed, and the light rays of the backlight module are finally refracted to generate pictures by controlling the light quantity by penetrating and blocking light paths through upper polarizing plates and lower polarizing plates arranged outside the liquid crystal display panel. Therefore, the electrode portion 40 of the present embodiment can be disposed on the gate electrode T of the thin film transistor T _G The electrode portion 40 may be made of light-shielding metal at the position between the substrate 101, so that light emitted from the backlight module to the display panel in the light leakage region can be shielded by the electrode portion 40, and the grid electrode T of the thin film transistor T can be further solved _G There is a problem in that an electric field may be generated between the exposed region and other conductive layers, and thus light leakage occurs.

In some alternative embodiments, please refer to fig. 34, fig. 34 is a schematic plan view of a display device according to an embodiment of the present invention, and the display device 111 according to the present embodiment includes the display panel 000 according to the above embodiment of the present invention. The embodiment of fig. 34 is only an example of a mobile phone, and the display device 111 is described, and it is to be understood that the display device 111 provided in the embodiment of the present invention may be other display devices 111 having a display function, such as a computer, a television, and a vehicle-mounted display device, which is not particularly limited in the present invention. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention, and the specific description of the display panel 000 in the above embodiments may be referred to specifically, and this embodiment is not repeated here.

As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, comprising a first substrate;

the first substrate at least comprises a substrate, a plurality of thin film transistors and a plurality of electrode parts, wherein the thin film transistors are arranged on the substrate, and each thin film transistor comprises a grid electrode, a source electrode, a drain electrode and an active part; the first substrate further comprises a common electrode, and the common electrode comprises a hollowed-out part in the direction perpendicular to the plane of the substrate, wherein the orthographic projection of the hollowed-out part to the substrate overlaps with the orthographic projection of the thin film transistor to the substrate;

the orthographic projection of the electrode part to the substrate at least partially surrounds the orthographic projection of the active part to the substrate, and the orthographic projection of the electrode part to the substrate is not overlapped with the orthographic projection of the channel region of the thin film transistor to the substrate;

The orthographic projection of the electrode part to the substrate at least partially overlaps with the orthographic projection of the grid to the substrate;

each electrode part at least comprises a first subsection and a second subsection which are mutually independent and are not connected;

the display panel comprises a plurality of data lines, and the source electrode of the thin film transistor is electrically connected with the data lines;

each of the electrode portions includes at least a first opening;

an orthographic projection of the first opening onto the substrate at least partially overlaps an orthographic projection of the data line onto the substrate.

2. The display panel according to claim 1, wherein a material of the electrode portion comprises a metal material.

3. The display panel according to claim 1, further comprising a second substrate disposed opposite to the first substrate, the second substrate comprising a black matrix layer;

the orthographic projection of the black matrix layer onto the substrate covers the orthographic projection of the active portion onto the substrate.

4. The display panel according to claim 1, wherein adjacent two of the electrode portions are not connected independently of each other.

5. The display panel of claim 1, wherein the display panel comprises,

The first substrate further comprises a first metal layer, an active layer, a second metal layer, a third metal layer, a first electrode layer and a second electrode layer which are positioned on one side of the substrate, the second metal layer is positioned on one side of the first metal layer away from the substrate, the first electrode layer is positioned on one side of the second metal layer away from the first metal layer, and the second electrode layer is positioned on one side of the first electrode layer away from the second metal layer;

the first electrode layer includes a first electrode, and the second electrode layer includes a second electrode;

the grid electrode is positioned on the first metal layer, the active part is positioned on the active layer, the source electrode and the drain electrode are positioned on the second metal layer, and the electrode part is positioned on the third metal layer.

6. The display panel of claim 5, wherein the display panel comprises,

the first electrode is a pixel electrode, and the second electrode is the common electrode; or alternatively, the process may be performed,

the first electrode is the common electrode, and the second electrode is a pixel electrode.

7. The display panel of claim 6, wherein the third metal layer is located on a side of the second metal layer remote from the substrate.

8. The display panel according to claim 7, wherein a first insulating layer is provided on a side of the first electrode layer close to the substrate;

the third metal layer and the first electrode layer are both in direct contact with the first insulating layer, and the first electrode and the electrode portion do not overlap in a direction perpendicular to a plane in which the substrate is located.

9. The display panel according to claim 7, wherein a second insulating layer is provided on a side of the second electrode layer close to the substrate;

the third metal layer and the second electrode layer are both in direct contact with the second insulating layer, and the second electrode and the electrode portion do not overlap in a direction perpendicular to a plane in which the substrate is located.

10. The display panel according to claim 7, wherein the third metal layer is located on a side of the first electrode layer close to the second electrode layer, the electrode portion is in contact with the first electrode, and the first electrode and the electrode portion are only partially overlapped in a direction perpendicular to a plane in which the substrate is located.

11. The display panel according to claim 10, wherein when the first electrode is the common electrode, adjacent two of the electrode portions are connected to each other.

12. The display panel according to claim 7, wherein the third metal layer is located on a side of the second electrode layer away from the first electrode layer, the electrode portion is in contact with the second electrode, and the second electrode only partially overlaps the electrode portion in a direction perpendicular to a plane in which the substrate is located.

13. The display panel according to claim 12, wherein when the second electrode is the common electrode, adjacent two of the electrode portions are connected to each other.

14. A display panel according to any one of claims 11 or 13, wherein adjacent two of the electrode portions are connected to each other by a connecting portion provided in the same layer as the electrode portions.

15. The display panel according to claim 14, wherein the display panel includes a plurality of scan lines and a plurality of data lines, and the connection portion at least partially overlaps the scan lines and/or the data lines in a direction perpendicular to a plane in which the substrate is located.

16. The display panel of claim 5, wherein the active layer is located between the first metal layer and the second metal layer.

17. The display panel of claim 6, wherein the third metal layer is located between the first metal layer and the substrate.

18. The display panel according to claim 1, wherein a material for manufacturing the active portion includes any one of silicon and an oxide semiconductor.

19. A display device comprising the display panel of any one of claims 1-18.