CN109358680B

CN109358680B - Three-phase AC voltage stabilizer

Info

Publication number: CN109358680B
Application number: CN201811355958.7A
Authority: CN
Inventors: 周维龙; 凌云; 文定都; 刘建华; 杨兴果
Original assignee: Hunan University of Technology
Priority date: 2018-11-15
Filing date: 2018-11-15
Publication date: 2020-10-30
Anticipated expiration: 2038-11-15
Also published as: CN109358680A

Abstract

A three-phase alternating current voltage stabilizing device comprises a self-coupling compensation type three-phase main circuit unit, a compensation control unit, a trigger unit and a protection driving unit; the compensation control unit consists of three compensation control circuits including a sampling comparison circuit, a delay protection circuit, a trigger gating configuration circuit and an error detection judging circuit, and is used for respectively sampling voltages of three-phase voltages and outputting three-phase trigger control signals, non-trigger area control signals and trigger gating control value judging signals; the protection driving unit judges whether the signal is effective or not according to the input three-phase trigger gating control value to protect the three-phase thyristor switch group in the main circuit. The alternating current voltage stabilizer can adjust the partition quantity of voltage in the fluctuation range of the phase voltage of an input alternating current power supply, and change the compensation mode and the compensation precision; when the interlocking control is realized, the thyristor switch group is protected by judging whether the logic error occurs in the control circuit or not, and the protection strength aiming at the abnormity of the working process is effectively enhanced.

Description

Three-phase AC voltage stabilizer

Technical Field

The invention relates to the technical field of power supplies, in particular to a three-phase alternating-current voltage stabilizing device.

Background

The existing compensation type single-phase and three-phase AC voltage stabilizer has the advantages of wide voltage stabilizing range, almost no distortion of waveform, high efficiency of the whole machine and strong load adaptability. The principle is that switching of different winding coils of a primary winding on a compensation transformer is automatically controlled according to the high-low condition of input voltage, bidirectional multi-gear voltage compensation is provided by utilizing the transformation ratio relation of a primary side working winding and a secondary winding or by adjusting the voltage applied to the primary winding, and therefore the purpose of voltage regulation and stabilization is achieved.

The existing compensation type alternating current voltage stabilizer has the following defects: when the motor is adopted to control the carbon brush to move to change the application of different voltages to the excitation coil of the compensation transformer, the carbon brush is easy to wear and often fails. Switching different winding coils of a primary winding on a compensation transformer by adopting an electronic switch switching mode, or when voltage applied to the primary winding is adjusted, the delayed turn-off of the electronic switch is easy to cause a power supply short-circuit fault; when the electronic switch is controlled to be switched by adopting a program mode of a singlechip, a PLC and the like, the problems of program runaway, dead halt and the like can also cause the failure of the voltage stabilizer or cause the short-circuit fault of a power supply due to the error of control logic.

Disclosure of Invention

In order to solve the problems of the existing compensation type alternating current voltage stabilizer, the invention provides a three-phase alternating current voltage stabilizer which comprises a self-coupling compensation type three-phase main circuit unit, a compensation control unit, a trigger unit and a protection driving unit. Each phase main circuit of the self-coupling compensation type three-phase main circuit unit comprises a compensation transformer, a self-coupling transformer, a thyristor switch group and a relay protection circuit; the compensation control unit outputs a three-phase trigger control signal to the trigger unit; the trigger unit sends a trigger signal to the self-coupling compensation type three-phase main circuit unit according to an input trigger control signal to control the on-off of the thyristors in the three-phase thyristor switch group; the compensation control unit simultaneously outputs a three-phase non-triggering area control signal and a three-phase triggering gating control value judging signal to the protection driving unit, the protection driving unit starts/stops protection of the three-phase thyristor switch group according to whether the input three-phase triggering gating control value judging signal is effective or not, and simultaneously controls a power supply of the triggering unit according to whether the three-phase triggering gating control value judging signal is effective or not and whether the three-phase non-triggering area control signal is effective or not.

The compensation control unit consists of three compensation control circuits with the same structure; the three compensation control circuits respectively carry out voltage sampling on the voltage of the three-phase alternating current power supply and output a three-phase trigger control signal, a three-phase non-trigger area control signal and a three-phase trigger gating control value judgment signal.

The compensation control circuit of each phase comprises a sampling comparison circuit, a delay protection circuit, a trigger gating configuration circuit and an error detection judging circuit, wherein the delay protection circuit of each phase has the same function and structure, the sampling comparison circuit of each phase has the same function and structure, the trigger gating configuration circuit of each phase has the same function and structure, and the error detection judging circuit of each phase has the same function and structure. In each phase compensation control circuit, a sampling comparison circuit samples the voltage of an alternating current power supply phase voltage, outputs a trigger gating control value and sends the trigger gating control value to a delay protection circuit; the delay protection circuit outputs a non-trigger area control signal and a delayed trigger gating control value; the delayed trigger gating control value is sent to a trigger gating configuration circuit and an error detection judging circuit; the trigger gating configuration circuit outputs a trigger control signal; the error detection judging circuit inputs the delayed trigger gating control value, judges whether the delayed trigger gating control value is effective or not, and outputs a trigger gating control value judging signal.

The trigger gating control value of each phase is an M-bit binary value; in each phase of compensation control circuit, the basis of judging whether the input trigger gating control value is effective or not by the error detection judging circuit is that the trigger gating control value is effective when only one bit is effective in M-bit binary values of the trigger gating control value; otherwise, the trigger gating control value is invalid. The bit in the trigger gating control value is 1 valid and 0 invalid, namely the high level in the trigger gating control value signal is valid and the low level is invalid; or, the bit in the trigger gating control value is 0 valid and 1 invalid, that is, the low level in the trigger gating control value signal is valid and the high level is invalid; a total of M trigger strobe control values are valid.

In each phase, the sampling comparison circuit comprises an alternating current power supply phase voltage sampling circuit and a multi-interval voltage comparator circuit, and the alternating current power supply phase voltage sampling circuit converts an alternating current power supply phase voltage effective value into an alternating current power supply phase voltage sampling value.

In each phase, the multi-interval voltage comparator circuit comprises m-1 comparators, compares input voltage with m-1 different threshold voltages and outputs m-bit comparison output values; and m-1 comparators are all powered by a positive single power supply. m-1 different threshold voltages are respectively connected to the inverting input ends of m-1 comparators, and the input voltage is simultaneously connected to the non-inverting input ends of the m-1 comparators; the high level of the m-bit comparison output values output by the multi-interval voltage comparator is effective, and only one of the m-bit comparison output values is effective; in m-1 comparators, the comparator with the highest threshold voltage is directly powered by a positive single power supply, and other comparators are powered by controllable power supplies; when the comparator is powered by a controllable power supply, the controllable power supply supplies power to the positive power supply end of the comparator only when all the comparators with the threshold voltages higher than the threshold voltages output low levels, otherwise, the controllable power supply stops supplying power to the positive power supply end of the comparator; the comparator adopts a controllable power supply to supply power, and outputs a low level when the controllable power supply stops supplying power to the positive power supply end; the m-bit comparison output value consists of the output values of m-1 comparators and the minimum interval judgment value; and when all the output values of the m-1 comparators are at low level, the lowest interval judgment value is at high level, otherwise, the lowest interval judgment value is at low level.

In each phase, the voltage in the fluctuation interval range of the alternating current power supply phase voltage is adjusted to M voltage grade intervals, and the sampling comparison circuit is adjusted to realize the voltage regulation; further, the method is realized by adjusting parameters of the multi-interval voltage comparator circuit. In each phase, the multi-interval voltage comparator circuit also comprises a multi-threshold voltage output circuit consisting of an upper threshold potentiometer, a lower threshold potentiometer and a plurality of intermediate divider resistors, and m-1 different threshold voltages are provided for m-1 comparators; adjusting the parameter values of the upper limit threshold potentiometer and the lower limit threshold potentiometer, and adjusting the voltage in the fluctuation interval range of the alternating-current power supply phase voltage into M voltage class intervals, wherein the M voltage class intervals correspond to M effective M-bit trigger gating control values output by the sampling comparison circuit one by one; the M-bit trigger gating control value consists of the lower M bits in the M-bit comparison output value, namely the M-bit trigger gating control value consists of the output of M-1 comparators with the lowest threshold voltage in the multi-interval voltage comparator circuit and the lowest interval judgment value; the M-1 lowest threshold voltages are respectively voltage sampling values of the voltage values of the alternating current power supply which are separated by M voltage grade intervals. M is not less than 3, and M is not less than 2 and not more than M.

When the comparator is powered by a controllable power supply, the output end of the comparator is connected with a pull-down resistor, the controllable power supply supplies power to the positive power supply end of the comparator only when all the comparators with the threshold voltages higher than the threshold voltages output low levels, and otherwise, the controllable power supply stops supplying power to the positive power supply end of the comparator. The positive power supply end of the comparator is connected to the output end of the NOR gate, and the input end of the NOR gate is respectively connected to the output ends of the comparators with the threshold voltages higher than that of the NOR gate.

The comparators in the multi-interval voltage comparator circuit preferably adopt a low-power-consumption rail-to-rail operational amplifier powered by a single power supply.

In each phase, triggering gating control values to control the on-off combined state of thyristors in the thyristor switch group; controlling the on-off combined state of the thyristors in the thyristor switch group to select 0 or 1 or overlapping of a plurality of output voltages of the phase autotransformer as the excitation coil voltage of the phase compensation transformer, and realizing the voltage compensation state corresponding to the voltage grade interval; each voltage level interval of the alternating current power supply phase voltage corresponds to a voltage compensation state. In each phase, the trigger gating configuration circuit comprises a diode trigger configuration matrix; the trigger gating configuration circuit is used for selecting and enabling a corresponding trigger control signal to be effective by a diode trigger configuration matrix according to an effective trigger gating control value, and controlling the on-off combination state of the thyristors in the in-phase thyristor switch group of the self-coupling compensation type three-phase main circuit unit.

In each phase, the thyristor switch group has N thyristors; the diode trigger configuration matrix comprises m trigger control row lines and N trigger drive column lines; the N triggering driving column lines correspond to the N thyristors one by one, and one triggering driving column line effectively corresponds to enable a triggering control signal of one thyristor to be effective; a configuration branch consisting of a diode and a configuration switch in series connection is arranged at the crossing position of each trigger control row line and each trigger driving column line, and the configuration switch can be connected in series with the cathode end of the diode or the anode end of the diode; when the trigger control row line signal is active at a low level, the cathode side of the diode of the configuration branch is connected to the trigger control row line, and the anode side of the diode of the configuration branch is connected to the trigger driving column line; when the trigger control row line signal is high level and effective, the anode side of the diode of the configuration branch is connected to the trigger control row line, and the cathode side of the diode is connected to the trigger drive column line; and N is an integer greater than or equal to 4.

In each phase, the configuration method of the configuration switch in the configuration branch is that M of M trigger control row lines is selected as a trigger gating control row line; m triggering gating control row lines are in one-to-one correspondence with M bit triggering gating control values, and one effective triggering gating control value is effective corresponding to one triggering gating control row line; when each trigger gating control row line signal is effective, the trigger gating control row line signal corresponds to the on-off combination state of a thyristor in one thyristor switch group, the trigger driving row line signal of the trigger driving row line corresponding to the thyristor to be conducted in the on-off combination state is effective, in the configuration branches of the trigger gating control row line and the N trigger driving row lines, the configuration switches in the configuration branches between the trigger gating control row line and the trigger driving row line signal effective are configured to be in an on state, and the configuration switches in other configuration branches are configured to be in an off state.

In each phase, one trigger driving column line signal is effective and corresponding to enable a trigger control signal of one thyristor to be effective, namely, N trigger driving column line signals are directly used as trigger control signals of N thyristors in a one-to-one correspondence mode; a trigger driving column line signal is effective and corresponds to a method for enabling a trigger control signal of a thyristor to be effective, or the trigger gating configuration circuit further comprises a trigger control signal driving circuit; the input of the trigger control signal driving circuit is N signals for triggering and driving the column lines, and the output is trigger control signals of N thyristors in one-to-one correspondence.

In each phase, when the voltage level interval is changed due to the fluctuation of the phase voltage of the alternating current power supply, so that the trigger gating control value is changed and the on-off combination state of the thyristors in the thyristor switch group needs to be switched, one non-trigger area time is maintained between 2 different on-off combination states of the thyristors in the thyristor switch group, and all the thyristors in the thyristor switch group are switched off. Maintaining a no-trigger zone time is achieved by a no-trigger zone control signal; controlling the control signal of the non-trigger area to output a single pulse after the trigger gating control value is changed; the no-trigger area control signal is active during the output of a single pulse and inactive during the non-output of a single pulse. Further, after the trigger gating control value is changed, the width time of a single pulse in the non-trigger area control signal is selected from 10ms to 30 ms.

In each phase, in the delay protection circuit, the change time of the delayed trigger gating control value signal is later than the leading edge time of a single pulse in the non-trigger area control signal after the trigger gating control value is changed and is earlier than the trailing edge time of the single pulse in the non-trigger area control signal after the trigger gating control value is changed.

The specific method for starting/stopping the protection of the three-phase thyristor switch group by the protection driving unit according to the fact that whether the input three-phase trigger gating control value judging signal is effective or not is that when one or more than one of the three-phase trigger gating control value judging signals are ineffective, the input side power supply voltage of all autotransformers in three phases is controlled to be cut off to enable the three-phase thyristor switch group to be in a protection state. When the three-phase thyristor switch group is in a protection state and the three-phase trigger gating control value judging signals are all recovered to be effective, the protection driving unit automatically stops the protection state of the three-phase thyristor switch group.

The specific method for controlling the power supply of the trigger unit by the protection driving unit according to the fact that whether the three-phase trigger gating control value judging signal is effective or not and whether the three-phase non-trigger area control signal is effective or not is that when one or more than one of the three-phase trigger gating control value judging signals are ineffective, the power supply of a three-phase trigger circuit in the trigger unit is controlled to be disconnected; when the three-phase trigger gating control value judging signals are all effective, in each phase, if the control signal of the non-trigger area is effective, the power supply of the in-phase trigger circuit in the trigger unit is switched off, otherwise, the power supply of the in-phase trigger circuit in the trigger unit is switched on, the in-phase trigger circuit works normally, and a trigger pulse is sent out according to the input trigger control signal.

The thyristors in the three-phase thyristor switch group are bidirectional thyristors or thyristor alternating current switches formed by connecting 2 unidirectional thyristors in reverse parallel.

The invention has the beneficial effects that: the resistance values of an upper limit threshold potentiometer and a lower limit threshold potentiometer in the sampling comparison circuit are adjusted and changed, meanwhile, configuration switches in a diode trigger configuration matrix are configured differently to change the on-off combination state of thyristors in a thyristor switch group corresponding to a trigger gating control value, so that the adjustment of different partition numbers is realized, when the requirement on voltage stabilization precision is low, fewer partition numbers can be configured, and the frequency of gear shifting switching of a voltage stabilization device is reduced, so that the impact frequency of the gear shifting voltage to a load is reduced; when the requirement of voltage stabilization precision is higher, more partitions can be configured to meet the precision requirement. The three-phase alternating-current voltage stabilizing device for performing voltage compensation by adopting the compensation transformer bank and the thyristor switch bank adopts the diode trigger configuration matrix to ensure that the thyristors at the same side in each phase of thyristor switch bank are not conducted simultaneously, thereby realizing the interlocking control of the thyristors, and simultaneously stopping sending trigger pulses and performing the protection of the three-phase thyristor switch bank under the condition that an invalid trigger gating control value is output by mistake possibly occurring in a sampling comparison circuit, thereby effectively strengthening the protection strength of the three-phase alternating-current voltage stabilizing device against the abnormity of the working process; when the three-phase thyristor switch group is in the protection state, if the three-phase trigger gating control values are all recovered to be effective, the protection state of the three-phase thyristor switch group can be automatically stopped and the three-phase thyristor switch group is enabled to be in the compensation working state again. The three-phase alternating current voltage stabilizing device does not adopt a program mode of a singlechip, a PLC and the like to control the on-off switching of the thyristor, thereby avoiding the voltage stabilizer faults caused by the problems of program runaway, dead halt and the like. The three-phase alternating current voltage stabilizing device is more stable and reliable in work due to the functions.

Drawings

FIG. 1 is a block diagram of a system configuration of a three-phase AC voltage stabilizer;

FIG. 2 is a block diagram of the A-phase compensation control circuit;

FIG. 3 is a schematic diagram of the A-phase main circuit of the embodiment 1 of the self-coupled compensated three-phase main circuit unit;

FIG. 4 is a schematic diagram of the A-phase main circuit of embodiment 2 of the self-coupled compensated three-phase main circuit unit;

FIG. 5 shows a sampling comparison circuit in the A-phase compensation control circuit in embodiment 1;

FIG. 6 shows a sampling comparison circuit of embodiment 2 of the A-phase compensation control circuit;

FIG. 7 is a block diagram of an embodiment of an A-phase delay protection circuit;

fig. 8 is a circuit diagram of embodiment 1 of the delay detection circuit for the a-phase trigger strobe control value signal Y11 in the delay detection module;

fig. 9 is a circuit embodiment 2 of the delay detection circuit for the a-phase trigger strobe control value signal Y11 in the delay detection module;

fig. 10 is a circuit diagram of embodiment 3 of the delay detection circuit for the a-phase trigger strobe control value signal Y11 in the delay detection module;

FIG. 11 is a block diagram of an embodiment of an A-phase no-trigger area control signal generation module;

FIG. 12 is a diagram of a portion of related waveforms in the phase A delay protection circuit;

FIG. 13 is an embodiment of a trigger circuit in the trigger unit for triggering the triac SR1 in the phase A main circuit;

FIG. 14 shows an embodiment 1 of the phase A trigger strobe control unit;

FIG. 15 shows an embodiment 2 of the phase A trigger strobe control unit;

FIG. 16 shows an embodiment 1 of the A-phase error detection and discrimination circuit;

FIG. 17 shows an embodiment 2 of the A-phase error detection and discrimination circuit;

fig. 18 is a protection drive unit embodiment.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

Fig. 1 is a block diagram of a system of a three-phase ac voltage stabilizer, in which a compensation control unit outputs a three-phase trigger control signal P5 to a trigger unit, and a three-phase trigger control signal P5 is composed of a phase a, a phase B, and a phase C trigger control signals P5A, P5B, and P5C; the trigger unit sends a trigger signal P6 to the self-coupling compensation type three-phase main circuit unit according to an input three-phase trigger control signal to control the on-off of the bidirectional thyristor in the A, B, C three-phase main circuit thyristor switch group. The compensation control unit simultaneously outputs a three-phase non-trigger area control signal P4 and a three-phase trigger gating control value judging signal P7 to the protection driving unit, the three-phase non-trigger area control signal P4 comprises A-phase, B-phase and C-phase non-trigger area control signals P4A, P4B and P4C, and the three-phase trigger gating control value judging signal P7 comprises A-phase, B-phase and C-phase A-phase trigger gating control value judging signals P7A, P7B and P7C; the protection driving unit judges whether the signal is effective or not according to the input three-phase trigger gating control value to start/stop the protection of the three-phase thyristor switch group, and simultaneously judges whether the signal is effective or not and whether the three-phase non-trigger area control signal is effective or not according to the three-phase trigger gating control value to control the power supply of the trigger unit.

The compensation control unit consists of A, B, C three-phase compensation control circuits, fig. 2 is a block diagram of an A-phase compensation control circuit, and the sampling comparison circuit samples the voltage of an A-phase alternating-current power supply phase voltage and outputs an A-phase trigger gating control value P2A; the delay protection circuit inputs an A-phase trigger gating control value P2A and outputs a delayed A-phase trigger gating control value P3A and an A-phase non-trigger area control signal P4A; the trigger gating configuration circuit inputs the delayed A-phase trigger gating control value P3A and outputs an A-phase trigger control signal P5A; the error detection judging circuit judges whether the input A-phase trigger strobe control value P3A is effective or not, and outputs an A-phase trigger strobe control value judging signal P7A. The structure, function and control logic of the B-phase and C-phase compensation control circuits are the same as those of the A-phase, voltage sampling and control are respectively carried out on the B-phase alternating current power supply phase voltage and the C-phase alternating current power supply phase voltage, B-phase and C-phase trigger control signals P5B and P5C are output, B-phase and C-phase non-trigger area control signals P4B and P4C and B-phase and C-phase A-phase trigger gating control value judging signals P7B and P7C are output.

Fig. 3 is an a-phase main circuit in an embodiment 1 of the self-coupling compensation type three-phase main circuit unit, which includes a compensation transformer TB1 and a self-coupling transformer TB2, 6 bidirectional thyristors SR1-SR6 jointly form an a-phase thyristor switch group, and a fuse FU1, a relay normally-open switch KA-1 and a relay normally-closed switch KA-2 form an a-phase successive electrical appliance protection circuit.

In fig. 3, the compensation coil of the compensation transformer TB1 is connected in series to the phase line a, where the input end of the phase line is L1A and the output end is L2A. The voltage on the excitation coil of TB1 is controlled by the A-phase thyristor switch group. The autotransformer TB2 is provided with 3 output taps C1, C2 and C3, one ends of bidirectional thyristors SR1, SR3 and SR5 are connected in parallel and then connected to one end of a TB1 excitation coil, and the other ends of SR1, SR3 and SR5 are connected to taps C1, C2 and C3 respectively; one ends of the bidirectional thyristors SR2, SR4 and SR6 are connected in parallel and then connected to the other end of the excitation coil of TB1, and the other ends of SR2, SR4 and SR6 are respectively connected to taps C1, C2 and C3. The output voltage U12 between a tap C1 and a tap C2 of the autotransformer TB2 is different from the output voltage U23 between a tap C2 and a tap C3, and the voltage U23 is 2 times of the voltage U12; the thyristor switch group has 6 excitation coil voltage compensation modes of a forward direction U12, a forward direction U23, a forward direction U12+ U23, a reverse direction U12, a reverse direction U23 and a reverse direction U12+ U23 at most, and a0 voltage compensation mode when an input voltage is within a normal range is additionally applied, so that an alternating current power supply phase voltage input by an A-phase line input end L1A can be divided into 7 voltage intervals for compensation control at most. In fig. 3, N is a zero line, and G11, G12 to G61, and G62 are trigger signal input terminals of the triacs SR1 to SR6, respectively. In fig. 3, the bidirectional thyristors SR1, SR3, and SR5 constitute the same-side thyristor, and the bidirectional thyristors SR2, SR4, and SR6 constitute the other same-side thyristor; in order to avoid short circuit, 2 or more than 2 thyristors in the thyristors at the same time can not be conducted simultaneously; for example, SR1, SR3 cannot be turned on simultaneously, SR4, SR6 cannot be turned on simultaneously, and so on.

Fig. 4 is an a-phase main circuit in an embodiment 2 of the self-coupling compensation type three-phase main circuit unit, which includes a compensation transformer TB1 and a self-coupling transformer TB2, 8 bidirectional thyristors SR1-SR8 jointly form an a-phase thyristor switch group, and a fuse FU1, a relay normally-open switch KA-1 and a relay normally-closed switch KA-2 form an a-phase successive electrical appliance protection circuit.

In fig. 4, the compensation coil of the compensation transformer TB1 is connected in series to the phase line a, where the input end of the phase line is L1A and the output end is L2A. The voltage on the excitation coil of TB1 is controlled by the thyristor switch group. The autotransformer TB2 is provided with 4 output taps C1, C2, C3 and C4, one ends of the bidirectional thyristors SR1, SR3, SR5 and SR7 are connected in parallel and then connected to one end of a TB1 excitation coil, and the other ends of the SR1, SR3, SR5 and SR7 are respectively connected to the taps C1, C2, C3 and C4; one ends of the bidirectional thyristors SR2, SR4, SR6 and SR8 are connected in parallel and then connected to the other end of the excitation coil of TB1, and the other ends of the SR2, SR4, SR6 and SR8 are respectively connected to the taps C1, C2, C3 and C4. The output voltage U12 between a tap C1 and a tap C2 of an autotransformer TB2, the output voltage U23 between C2 and C3, and the output voltage U34 between C3 and C4 are different from each other, the voltage U23 is 3 times of the voltage U12, and the voltage U34 is 2 times of the voltage U12; the thyristor switch group comprises 12 excitation coil voltage compensation modes including a forward direction U12, a forward direction U23, a forward direction U34, a forward direction U12+ U23, a forward direction U23+ U34, a forward direction U12+ U23+ U34, a reverse direction U12, a reverse direction U23, a reverse direction U34, a reverse direction U12+ U23, a reverse direction U23+ U34 and a reverse direction U12+ U23+ U34, and when an input voltage is within a normal range, the 0 voltage compensation mode is applied, and the A power supply alternating-phase voltage input by the phase line input end L1A can be divided into at most 13 voltage intervals for compensation control. In fig. 4, N is a zero line, and G11, G12 to G81, and G82 are trigger signal input terminals of the triacs SR1 to SR8, respectively. In fig. 4, the bidirectional thyristors SR1, SR3, SR5 and SR7 constitute the same-side thyristor, and the bidirectional thyristors SR2, SR4, SR6 and SR8 constitute the other same-side thyristor; in order to avoid short circuit, 2 or more than 2 thyristors in the thyristors at the same time can not be conducted simultaneously; for example, SR1, SR7 cannot be turned on simultaneously, SR4, SR8 cannot be turned on simultaneously, and so on.

Each of the triacs of fig. 3, 4 may be replaced with 2 antiparallel triacs. In fig. 3 and 4, the relay normally open switch and the relay normally closed switch form a relay protection switch.

The self-coupling compensation type three-phase main circuit unit is a three-phase four-wire system circuit, the A, B, C three-phase main circuits respectively compensate the phase voltage of A, B, C phases by adopting the same circuit structure and form, namely B, C two phases respectively compensate the phase voltage of B, C phases by adopting the same circuit structure and compensation form as the A-phase main circuit.

The voltage of the fluctuation interval range of the phase voltage of the A-phase alternating-current power supply is adjusted to M voltage grade intervals, an A-phase sampling comparison circuit carries out voltage sampling on the phase voltage of the A-phase alternating-current power supply to obtain a phase voltage sampling value of the A-phase alternating-current power supply, M or M-1 comparators compare the phase voltage sampling values of the A-phase alternating-current power supply and output an A-phase trigger gating control value formed by M-bit binary numbers; when the phase voltage of the A-phase alternating-current power supply is in one of the M voltage grade intervals, the M-bit A-phase triggers that one corresponding bit in the gating control value is valid, and other bits are invalid. The effective bit of the M-bit A-phase trigger gating control value is high level, namely binary 1; the invalid bit is low level, i.e. binary 0; or, the effective bit of the M-bit A-phase trigger gating control value is low level, namely binary 0; the invalid bit is high, i.e. binary 1.

Fig. 5 shows an embodiment 1 of a sampling comparison circuit in an a-phase compensation control circuit, where m is equal to 7, and compensation control is performed on an embodiment 1 of a self-coupling compensation type three-phase main circuit unit. In the alternating current power supply voltage sampling circuit, alternating current power supply voltage input from a phase line L1A and a zero line N is reduced by a transformer TV, rectified by a rectifier bridge consisting of diodes DV1-DV4, filtered by a capacitor CV1 and divided by resistors RV1 and RV2 to obtain an alternating current power supply voltage sampling value U1 which is in direct proportion to the effective value of the input alternating current power supply voltage.

In the multi-interval voltage comparator circuit shown in fig. 5, the upper threshold potentiometer RPH, the lower threshold potentiometer RPL, and the intermediate voltage-dividing resistors RF2-RF6 constitute a voltage-dividing circuit, and after voltage division of the power supply + VCC1, the obtained 6 threshold voltages UF2-UF7 are 6 intermediate division voltage values of the voltage sample values corresponding to the ac power supply voltage values divided into 7 voltage class intervals. The 6 comparators FA2-FA7 realize comparison between an alternating current power supply phase voltage sampling value U1 and 6 threshold voltages UF2-UF7, 7-bit comparison output values of the multi-section voltage comparator circuit are composed of output Y12-Y17 of the 6 comparators FA2-FA7 and a lowest section judgment value Y11, and the voltage in the alternating current power supply phase voltage fluctuation section range is divided into 7 voltage grade sections 1-7 at most. The sampled value U1 of the AC power supply voltage is simultaneously sent to the non-inverting input end of a comparator FA2-FA 7; the 6 threshold voltages UF2-UF7 are respectively supplied to the inverting inputs of the comparators FA2-FA 7. In fig. 5, the power supply + VCC1 may be replaced by another precision power supply, and the voltage divider circuit divides the precision power supply to make the threshold voltage more accurate. The comparators FA2-FA7 are preferably all low-power single-power-supply rail-to-rail operational amplifiers, for example, single-channel rail-to-rail operational amplifiers with the static working power supply current less than 1mA, such as OPA317, AD8517, MCP6291, TLV2450, TLV2451, TLV2460 and TLV2461, are selected.

In FIG. 5, the NOR gates FH2-FH6 constitute controllable power supplies for the comparators FA2-FA6, i.e., the power supplies for the comparators FA2-FA6 are controlled by the outputs Y13-Y17, respectively; the resistors RB2-RB6 are pull-down resistors of the outputs Y12-Y16 respectively, and when the power supply of the corresponding comparator is close to 0V and the output of the corresponding comparator is in a high-impedance state, the level is pulled to be low. The power supply of the comparator FA7 is connected to the power supply + VCC1, and is in a normal working state, and the output Y17 controls the power supplies of the comparators FA2-FA 6. For example, when the input ac power phase voltage is high and is in the highest voltage class section 7 of the 7 voltage class sections, Y17 outputs high level, all the outputs of nor gates FH2-FH6 are low level, all the single power supply sources of comparators FA2-FA6 are close to 0V, all the outputs are close to 0V or high impedance state, and resistors RB2-RB6 pull the outputs Y12-Y16 low level respectively. When the input alternating current power supply phase voltage is not in the highest voltage grade interval 7 of 7 voltage grade intervals, Y17 outputs low level, NOR gate FH6 outputs high level to provide power supply for comparator FA6, at this time, if the input alternating current power supply phase voltage is in voltage grade interval 6, Y16 outputs high level, NOR gates FH2-FH5 all output low level, single power supply for comparators FA2-FA5 all approach 0V, the output all approach 0V or high impedance state, and resistors RB2-RB5 respectively pull output Y12-Y15 low level. When the input alternating current power supply phase voltage is lower than a voltage grade interval 6, Y17 and Y16 both output low level, NOR gates FH6 and FH5 both output high level and respectively provide power supplies for comparators FA6 and FA5, at the moment, if the input alternating current power supply phase voltage is in a voltage grade interval 5, Y15 outputs high level, NOR gates FH2-FH4 all output low level, single power supply of comparators FA2-FA4 are all close to 0V, the outputs are all close to 0V or high resistance state, and resistors RB2-RB4 respectively pull the outputs Y12-Y14 to low level. By analogy, when the input alternating-current power supply voltage is in the voltage class interval 4, Y14 outputs a high level, and the other outputs are low levels; when the input alternating current power supply phase voltage is in a voltage class interval 3, Y13 outputs high level, and other outputs are low level; when the input alternating current power supply voltage is in a voltage level interval 2, Y12 outputs a high level, and the other outputs are low levels; only when the input ac power supply voltage is at or below the voltage class interval 1, the outputs Y12 to Y17 of the comparators FA2 to FA7 are all at the low level, and the lowest interval determination value Y11 of the nor gate FH1 is made at the high level. When the nor gate FH1-FH6 selects a 74HC series high-speed CMOS gate, for example, when the 8-input nor gate 74HC4078, the three-input nor gate 74HC27, the four-input nor gate 74HC02, etc. are selected, or when the nor gate function is realized by a 74HC series high-speed CMOS or nor gate, the high-level driving current of the 74HC series high-speed CMOS can reach 4mA, which is enough to drive a single-channel rail-to-rail operational amplifier with the static operating power supply current less than 1 mA. The power supply of the NOR gate FH1-FH6 is power supply + VCC 1.

The fluctuation range of the input alternating current power supply phase voltage is set to be 220V +/-10%, and the alternating current power supply phase voltage is required to be stabilized within the range of 220V +/-2% for output. With the sampling comparison circuit embodiment 1 of fig. 5, the voltage input between 242V and 198V can be divided into 7 voltage class intervals with the interval voltage size of 8V, i.e., M is equal to 7, and the trigger gate control value P2A is composed of the whole of Y11-Y17 included in the 7-bit comparison output value; the voltage of 3 voltage class intervals is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of the 3 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 8V is about 220V +/-1.82%, and the requirement that the output is controlled within 220V +/-2% is met; the actual alternating current power supply phase voltage fluctuation interval corresponding to the 7 voltage class intervals of 8V is 248V to 192V, and the actual fluctuation range of the input voltage is covered. When the a-phase main circuit in embodiment 1 of the auto-coupling compensation type three-phase main circuit unit of fig. 3 is used for compensation, the input voltage of the autotransformer TB2 is ac 220V, and the TB1 compensation voltage is 8V when the output voltage U12 is used as the excitation coil voltage of TB 1; when the output voltage U23 is only used as the excitation coil voltage of TB1, the TB1 compensation voltage is 16V; when the output voltages U12 and U23 are used as the excitation coil voltage of TB1, the compensation voltage of TB1 is 24V. The selection of the threshold voltage UF2-UF7 is related to the proportion between the sampled value U1 of the alternating current power phase voltage and the alternating current power phase voltage; setting the proportion of the alternating current power supply phase voltage sampling value U1 to the alternating current power supply phase voltage to be 0.01, namely setting the alternating current power supply phase voltage sampling value U1 to be 1% of the effective value of the alternating current power supply phase voltage, and setting the voltage sampling value range corresponding to the voltage input between 242V and 198V to be 2.42V to 1.98V; when the alternating current power supply phase voltage is divided into 7 voltage class intervals with interval voltage of 8V, 6 threshold voltages UF7-UF2 are respectively 2.40V, 2.32V, 2.24V, 2.16V, 2.08V and 2.00V and are 6 middle separation voltage values of voltage sampling values corresponding to the alternating current power supply voltage values separating the 7 voltage class intervals; the difference values of the 6 threshold voltages are the same and are all 0.08V; the middle voltage-dividing resistors RF2-RF6 select the same resistance value, and adjust the resistance values of the upper threshold potentiometer RPH and the lower threshold potentiometer RPL respectively, so that the 6 threshold voltages UF7-UF2 can be adjusted to the required values. In this example, when the voltage of the input ac power supply exceeds the range of the maximum voltage level interval, the output signal corresponding to the maximum voltage level interval in the output trigger gate control value is valid, that is, the output is Y17 valid; at the moment, the main circuit performs corresponding voltage reduction compensation according to the condition that the voltage of the input alternating current power supply is in the maximum voltage grade interval. When the input alternating current power supply phase voltage is lower than the range of the minimum voltage class interval, the Y11 output is effective, and the main circuit performs corresponding voltage boosting compensation according to the fact that the input alternating current power supply phase voltage is in the range of the minimum voltage class interval.

The fluctuation range of the input alternating current power supply phase voltage is set to be 220V +/-10%, and when the input alternating current power supply phase voltage is required to be stabilized within the range of 220V +/-4% for output, the number of voltage intervals can be reduced, and frequent adjustment is avoided. With the sampling comparison circuit embodiment 1 of fig. 5, the voltage input between 242V and 198V is divided into 3 voltage class intervals with the interval voltage size of 16V, i.e. M is equal to 3; the voltage of 1 voltage class interval is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of 1 voltage class interval is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage range of 16V is about 220V +/-3.64%, and the requirement that the output is controlled within 220V +/-4% is met; the actual alternating-current power supply voltage fluctuation interval corresponding to the 3 voltage class intervals of 16V is 244V to 196V, and the actual fluctuation range of the input voltage is covered. At this time, the a-phase main circuit in embodiment 1 of the auto-compensation type three-phase main circuit unit of fig. 3 is used for compensation, the input voltage of the auto-transformer TB2 is ac 220V, the field coil voltage of TB1 is made only by the output voltage U23, and the TB1 compensation voltage is 16V. And selecting the lowest interval judgment value Y11 and the outputs Y12-Y13 of the comparators FA2-FA3 to form the trigger gating control value P2A. The selection of the threshold voltage UF2-UF3 is related to the proportion between the sampled value U1 of the alternating current power phase voltage and the alternating current power phase voltage; setting the proportion of an alternating current power supply phase voltage sampling value U1 to an alternating current power supply phase voltage to be 0.01, and setting the voltage sampling value range corresponding to the voltage between 242V and 198V to be 2.42V to 1.98V; when the alternating current power supply phase voltage is divided into 3 voltage class intervals with the interval voltage of 16V, 2 threshold voltages UF3-UF2 are 2.28V and 2.12V respectively, and are 2 middle separation voltage values of voltage sampling values corresponding to the alternating current power supply voltage values separating the 3 voltage class intervals; the resistance values of the upper limit threshold potentiometer RPH and the lower limit threshold potentiometer RPL are respectively adjusted, so that the 2 threshold voltages UF3-UF2 can be adjusted to required values. At the moment, the comparators FA4-FA7 work simultaneously, but the threshold voltages of FA4-FA7 are 2.44V, 2.60V, 2.76V and 2.92V respectively, and only when the voltage of an input alternating current power supply exceeds 244V, the comparators FA4-FA7 can output effective high level; since the input ac power phase voltage is between 242V and 198V, it is impossible to output an active high level in Y14-Y17 among the outputs of the comparators FA4-FA7, and the trigger gate control value P2A is composed of Y11-Y13 included in the 7-bit comparison output value.

Since the compensation mode of the self-coupled compensation type three-phase main circuit unit embodiment 1 automatically has the schmitt characteristic, the comparator FA2 to the comparator FA7 do not constitute a schmitt comparator. The trigger strobe control value output in fig. 5 is active high; the output end of each of the comparators FA2-FA7 is added with a stage of inverter, and the NOR gate FH1 is changed into an OR gate, so that the output trigger gating control value is changed into low level and effective.

Embodiment 1 of fig. 5 may also be performed for the self-coupling compensation type three-phase main circuit unit embodiment 2, and in this case, it is necessary to divide the voltage in the ac power supply phase voltage fluctuation interval range into more voltage class intervals. For example, when the voltage of the ac power phase voltage fluctuation interval range is divided into 13 voltage class intervals, the circuit of fig. 5 should be extended to 12 comparators for comparison with 12 threshold voltages with different magnitudes; the output trigger strobe control value P2A will consist of up to 13 bits, e.g., Y11-Y113.

Fig. 6 shows an embodiment 2 of a sampling comparison circuit in an a-phase compensation control circuit, where m is equal to 10, and compensation control is performed on an embodiment 2 of a self-coupling compensation type three-phase main circuit unit. In fig. 6, FD1 is a true effective value detection device LTC1966, a transformer TV1, a capacitor CV2, and a capacitor CV3 constitute an ac power supply phase voltage sampling circuit, and ac power supply phase voltages input from a phase line L1A and a zero line N are measured to obtain an ac power supply phase voltage sampling value U2. UIN1 and UIN2 of LTC1966 are alternating voltage differential input terminals, USS is a negative power input terminal capable of being grounded, UDD is a positive power input terminal, GND is a ground terminal, EN is a low-level effective enable control input terminal, UOUT is a voltage output terminal, and COM is an output voltage return terminal.

In fig. 6, FD2, RD1, RD2 constitute a multi-interval voltage comparator circuit; FD2 is a 10-stage comparison display driver LM3914, which includes an internal divider circuit formed by connecting 10 precision resistors of 1k omega in series, forms 10 comparison threshold voltages and is respectively connected to the positive input ends of the internal 10 comparators, and divides the voltage in the fluctuation range of the alternating current power supply phase voltage into 10 voltage class intervals 1-10 at most. Pin 6 is the high end of the inner voltage divider circuit and is connected to the power supply + VCC1 through the upper threshold potentiometer RD 1; pin 4 is the low end of the internal voltage divider circuit and is connected to the ground through a lower threshold potentiometer RD 2; pin 8 is the low end of the internal standard power supply and is connected to the ground; pin 2 is a negative power supply end and is connected to the ground; pin 3 is a positive power supply terminal and is connected to a power supply + VCC 1; pin 5 is a signal input end, is connected to a voltage sampling value U2 of an alternating current power supply and is internally connected to the negative input ends of 10 comparators; signals Y110 to Y11 output by pins 10-18 and pin 1 are output results of 10 comparators, wherein Y110 has the highest comparison threshold voltage and is sequentially reduced, and Y11 has the lowest comparison threshold voltage; Y1-Y110 are all effective at low level to form a comparison output value with 10 effective at low level; the mode control end of the 9 pins is suspended to realize the dot output from Y11 to Y110, namely only a single low level output from Y11 to Y110 is effective; when the voltage of the input alternating current power supply is in a voltage level interval 10, Y110 outputs a low level, and other outputs are high levels; when the input alternating current power supply phase voltage is in a voltage level interval 9, Y19 outputs low level, and other outputs are high level; when the voltage of the input alternating current power supply is in a voltage level interval 5, Y15 outputs low level, and other outputs are high level; when the input ac power supply phase voltage is in voltage class interval 1, Y11 outputs a low level, and the other outputs are high levels.

The fluctuation range of the input alternating current power supply phase voltage is set to be 220V + 10% to 220V-20%, and the alternating current power supply phase voltage is required to be stabilized within the range of 220V +/-2% for output. With the sampling comparison circuit embodiment 2 of fig. 6, the voltage input between 242V and 176V is divided into 10 voltage class intervals with the interval voltage size of 7V, that is, M is equal to 10, and the trigger strobe control value P2A is composed of Y11-Y110 included in the 10-bit comparison output value as a whole; the voltage of 3 voltage class intervals is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of the 6 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 7V is 220V +/-1.6%, the requirement that the output is controlled within 220V +/-2% is met, the actual alternating current power supply phase voltage fluctuation interval corresponding to 10 voltage class intervals of 7V is 244.5V to 174.5V, and the actual range of voltage fluctuation is covered. When the a-phase main circuit in embodiment 2 of the auto-coupling compensation type three-phase main circuit unit of fig. 4 is used for compensation, the input voltage of the autotransformer TB2 is ac 220V, and the TB1 compensation voltage is 7V when the output voltage U12 is used as the excitation coil voltage of TB 1; when the output voltage U23 is only used as the excitation coil voltage of TB1, the TB1 compensation voltage is 21V; when the output voltage U34 is only used as the excitation coil voltage of TB1, the TB1 compensation voltage is 14V; meanwhile, when the output voltages U12 and U23 are used as the excitation coil voltage of TB1, the compensation voltage of TB1 is 28V; and so on. The selection of the threshold voltage is related to the proportion between the sampled value U2 of the AC power phase voltage and the AC power phase voltage; setting the proportion of the alternating current power supply phase voltage sampling value U2 to the alternating current power supply phase voltage to be 0.005, namely setting the alternating current power supply phase voltage sampling value U2 to be 0.5% of the effective value of the alternating current power supply phase voltage, and setting the voltage sampling value range corresponding to the voltage input between 242V and 176V to be 1.21V to 0.88V; when the alternating current power supply phase voltage is divided into 10 voltage grade intervals with the interval voltage of 7V, 10 threshold voltages are respectively 1.1875V, 1.1525V, 1.1175V, 1.0825V, 1.0475V, 1.0125V, 0.9775V, 0.9425V, 0.9075V and 0.8725V and respectively correspond to voltage sampling values for dividing the voltage in the range from 244.5V to 174.5V into 10 lower limit values of the voltage grade intervals; the voltage at the high end of the inner voltage divider circuit is connected to the positive input end of the highest comparator, so that the voltage at the 6 pin is 1.1875V. According to the magnitude of the internal standard power output VREF (1.2V or 1.25V) and the magnitude of the internal 10 precision resistors, 10 threshold voltages can be obtained by adjusting the resistance values of the upper threshold potentiometer RD1 and the lower threshold potentiometer RD 2. If the precision of voltage compensation is required to be improved or the fluctuation range of the input voltage is required to be larger, the sampling comparison circuit embodiment 2 in fig. 6 is required to divide the voltage class into more voltage class intervals, for example, when the voltage in the fluctuation range of the alternating-current power supply phase voltage needs to be divided into 15 voltage class intervals, 2 LM3914 can be adopted for implementation, and the inner voltage divider circuits in the 2 LM3914 are connected in series to form 20 comparison threshold voltages, so as to form a 20-stage comparator circuit; with 13 of the comparison outputs selected, the output trigger strobe control value P2A will consist of at most 13 bits, e.g., Y11-Y113.

In embodiment 2 of the sampling comparison circuit in the a-phase compensation control circuit shown in fig. 6, when the voltage of the ac power supply is higher than the maximum voltage level interval, the output trigger gating control value is that the output signal corresponding to the maximum voltage level interval is valid, that is, the output is Y110 valid, and the main circuit performs corresponding voltage step-down compensation according to the situation that the voltage of the ac power supply is in the maximum voltage level interval. When the input alternating current power supply phase voltage is lower than the minimum voltage level interval range, all signals in the output trigger gating control value are invalid, and the main circuit does not perform voltage compensation at the moment.

In fig. 6, 10 comparators out of 10 comparators in LM3914 are used to compare the ac power phase voltages into 10 voltage class intervals. Only 9 comparators in 10 comparators in LM3914 can be adopted to compare and divide the phase voltage of the alternating current power supply into 10 voltage class intervals; the comparison threshold voltages of the 9 comparators are 9 middle separation voltage values of the voltage sampling values corresponding to the voltage values of the alternating current power supply separated by 10 voltage level intervals; for example, the comparison threshold voltage of each comparator is not changed, the output of pin 1 of LM3914 in FIG. 6 is not used as Y11, Y11 is selected and generated by Y12-Y110 control in the trigger gate control value, namely Y11 is enabled when all Y12-Y110 are disabled, otherwise Y11 is disabled; at the moment, when the voltage of the input alternating current power supply is in or higher than the range of the maximum voltage level interval, the output trigger gating control value is Y110 valid, and the main circuit performs corresponding voltage reduction compensation according to the situation that the voltage of the alternating current power supply is in the maximum voltage level interval; when the voltage of the input alternating current power supply is in or lower than the range of the minimum voltage class interval, Y11 output is effective, and the main circuit performs corresponding voltage boosting compensation according to the fact that the voltage of the input alternating current power supply is in the range of the minimum voltage class interval.

The fluctuation range of the input alternating current power supply phase voltage is set to be 220V +/-15%, the alternating current power supply phase voltage is required to be stabilized within the range of 220V +/-3.5% for output, the requirement on voltage stabilization precision is lowered, the number of voltage intervals can be reduced at the moment, and frequent adjustment is avoided. With the sampling comparison circuit embodiment 2 of fig. 6, the voltage input between 253V and 187V is divided into 5 voltage class intervals with interval voltage size of 14V, i.e., M is equal to 5; the voltage of 2 voltage class intervals is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of 2 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 14V is less than 220V +/-3.2%, the requirement that the output is controlled within 220V +/-3.5% is met, the actual alternating current power supply phase voltage fluctuation interval corresponding to 5 voltage class intervals of 14V is 255V-185V, and the actual range of voltage fluctuation is covered. When the a-phase main circuit in embodiment 2 of the auto-coupling compensation type three-phase main circuit unit of fig. 4 is used for compensation, the input voltage of the autotransformer TB2 is ac 220V, and the TB1 compensation voltage is 14V when the output voltage U34 is used as the excitation coil voltage of TB 1; when the output voltages U12 and U23 are used as the excitation coil voltage of TB1, the compensation voltage of TB1 is 28V. The sampled value U2 of the phase voltage of the alternating current power supply is 0.5% of the effective value of the phase voltage of the alternating current power supply, and the sampled value range of the voltage corresponding to the voltage input between 253V and 187V is 1.265V to 0.935V; when the alternating current power supply phase voltage is divided into 5 voltage grade intervals with the interval voltage of 14V, 5 threshold voltages are respectively 1.205V, 1.135V, 1.065V, 0.995V and 0.925V and are respectively voltage sampling values corresponding to the lower limit values of the alternating current power supply phase voltage of 5 voltage grade intervals; adjusting the resistance values of an upper limit threshold potentiometer RD1 and a lower limit threshold potentiometer RD2 to enable the threshold voltages of 5 comparators with lower threshold voltages in the LM3914 to be the 5 threshold voltages, and signals Y15-Y1 output by pins 15-18 and 1 are output results of the 5 comparators, wherein Y15 has the highest comparison threshold voltage and is sequentially reduced, and Y11 has the lowest comparison threshold voltage; the 10-bit comparison output values are all active low, and the trigger strobe control value P2A is composed of Y11-Y15 included in the 10-bit comparison output values. At this time, the comparison threshold of the comparators outputting Y16 to Y110 is 1.275V or more, and the corresponding ac power supply voltage value is 255V, which is out of the actual input voltage range, and therefore, it is impossible for Y16 to Y110 in fig. 6 to output an effective low level.

The sampling comparison circuit embodiment 2 in fig. 6 can also perform compensation control on the a-phase main circuit in the self-coupling compensation type three-phase main circuit unit embodiment 1, and at this time, only the voltage in the fluctuation interval range of the input ac power phase voltage needs to be divided into intervals of no more than 7 voltage levels, that is, the comparison output of no more than 7 levels is selected.

In the embodiment 2 of the a-phase sampling comparison circuit in fig. 6, both the B-phase and the C-phase adopt sampling comparison circuits having the same structure and function as those of the a-phase, regardless of whether the embodiment 1 of the self-coupled compensation type three-phase main circuit unit or the embodiment 2 of the self-coupled compensation type three-phase main circuit unit is used for compensation control.

In addition to the embodiment of the a-phase sampling comparison circuit shown in fig. 5 or fig. 6, compensation control is performed on the embodiment 1 or the embodiment 2 of the self-coupled compensation type three-phase main circuit unit, and the three-phase sampling comparison circuit may also select another ac power supply phase voltage sampling circuit and comparison circuit to implement the functions required by the sampling comparison circuit. The ac power supply voltage sampling value U1 output by the ac power supply phase voltage sampling circuit of fig. 5 may be sent to the multi-interval voltage comparator circuit of fig. 6 for comparison, and a trigger gating control value is output; the ac power source voltage sampling value U2 output by the ac power source voltage sampling circuit of fig. 6 may be sent to the multi-interval voltage comparator circuit of fig. 5 for comparison, and a trigger gating control value is output.

FIG. 7 is a block diagram of an embodiment of an A-phase delay protection circuit, in which a delay detection module YC1 respectively performs signal delay on input signals Y11-Y1M including an A-phase M-bit trigger gate control value Y11-Y1M to obtain delayed signals Y21-Y2M, and Y21-Y2M therein form an A-phase delayed trigger gate control value P3A; the YC1 module simultaneously and respectively carries out edge detection on the input signals Y11-Y1m to obtain edge detection signals Y31-Y3 m; the triggerless area control signal generation module YC2 inputs the edge detection signals Y31-Y3M, and converts the edge variation in the M-bit trigger gate control value Y11-Y1M into the triggerless area control signal P4A for outputting. In the block diagram of the embodiment in fig. 7, when the input of the delay detection module YC1 is the a-phase trigger gating control value output by the a-phase compensation control circuit in fig. 5 sampling comparison circuit embodiment 1, m is equal to 7. In the block diagram of the embodiment in fig. 7, when the input of the delay detection module YC1 is the a-phase trigger strobe control value output by the a-phase compensation control circuit in fig. 6 sampling comparison circuit embodiment 2, m is equal to 10. The phase B and the phase C adopt the same delay protection circuit as the phase A.

Fig. 8 shows a delay detection circuit embodiment 1 for the a-phase input signal Y11 in the delay detection module. The resistor RY0, the capacitor CY0 and the driving gate FY0 realize signal delay of Y11, and a delayed signal Y21 of Y11 is obtained. The resistor RY1, the capacitor CY1, the diode DY1 and the inverter FY1 form a rising edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is output in the output signal YP1 of the inverter FY 1. The resistor RY2, the capacitor CY2, the diode DY2, the inverters FY2 and FY3 constitute a falling edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the falling edge of Y11 is output in the output signal YP2 of the inverter FY 3. The nand gate FY4 implements a nor (negative logic) function, in which a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY4 when a negative pulse is generated in the input signals YP1 and YP2, that is, a single pulse in the form of a positive pulse is output by the nand gate FY4 when the input signal Y11 changes. In fig. 8, the drive gate FY0, inverter FY1, inverter FY3 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; the drive gate FY0 may consist of 2 inverters with schmitt inputs.

Fig. 9 shows an embodiment 2 of the delay detection circuit for the a-phase input signal Y11 in the delay detection module. The inverter FY5, the resistor RY3 and the capacitor CY3 invert and delay the input signal Y11 to obtain a delayed inverted signal YP0 of Y11; the inverter FY6 inverts YP0 to obtain a delayed Y11 signal Y21. The signal input by the nand gate FY7 is a delayed inverted signal YP0 of Y11 and Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is generated in the output signal YP 1; the or gate FY8 receives the inverted signals YP0 of Y11 and Y11, and the output signal YP2 generates a single pulse in the form of a negative pulse corresponding to the falling edge of Y11. The nand gate FY9 implements a nor (negative logic) function, in which a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY9 when a negative pulse is generated in the input signals YP1 and YP2, that is, a single pulse in the form of a positive pulse is output by the nand gate FY9 when the input signal Y11 changes. In fig. 9, inverter FY6, nand gate FY7, or gate FY8 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; nand gate select 74HC132, CD4093, etc.; or gate select 74HC7032 or 2 inverters with schmitt inputs and 1 nand gate to implement the or gate function.

Fig. 10 is a delay detection circuit embodiment 3 for the a-phase input signal Y11 in the delay detection module, in which a rising edge detection circuit for the input signal Y11 is composed of the resistor RY1, the capacitor CY1, the diode DY1 and the inverter FY1, and a falling edge detection circuit for the input signal Y11 is composed of the resistor RY2, the capacitor CY2, the diode DY2, the inverter FY2 and the inverter FY3, and a circuit for outputting the edge detection signal Y31 by using the nand gate FY4 is the same as in embodiment 1 of fig. 8. In fig. 10, the signal delay of Y11 is realized by inverters FY11, FY12, FY13, and FY14, and a delayed signal Y21 of Y11 is obtained.

The delay detection circuit for the phase-A input signal Y11 can select any one of the embodiments 1-3 in FIG. 8, FIG. 9 and FIG. 10; generally, the same delay detection circuit is used for all signals in A, B, C three-phase trigger gating control value. For example, assuming that m is equal to 7, A, B, C three phases require 21 delay detection circuits; the 21 delay detection circuits may be all employed in embodiment 1 of fig. 8, or all employed in embodiment 2 of fig. 9, or all employed in embodiment 3 of fig. 10. The delay detection circuit may also adopt other circuits meeting the requirements to realize the functions thereof.

The function of the no-trigger area control signal generation module of each phase is to output a single pulse in the no-trigger area control signal of the phase when a single pulse related to an edge is generated in any one or more of the edge detection signals input for the trigger strobe control value of the phase. FIG. 11 is an embodiment of an A-phase no-trigger area control signal generating module, in which a corresponding function is realized by a circuit including m input NOR gates FY10, m pull-down resistors Rz1-Rzm, and m edge-detection-signal gate switches z1-zm, wherein m-bit edge detection signals Y31-Y3m of the A-phase are respectively connected to m input terminals of a NOR gate FY10 through the edge-detection-signal gate switches z1-zm, and the pull-down resistors RZ1-RZm are used for pulling down the corresponding input signal of the NOR gate FY10 to a low level when a certain z1-zm is opened; the nor gate FY10 outputs the no-trigger area control signal P4A as the a phase. In the embodiment of fig. 11, the single pulse that does not trigger the output of the zone control signal is a negative pulse, i.e., the low level of the zone control signal is not active; when the nor gate FY10 is replaced by an or gate, the single pulse that does not trigger the zone control signal output is a positive pulse. If the single pulse associated with an edge generated in the input edge detection signals Y31-Y3M is a negative pulse, the nor gate FY10 in fig. 11 should be changed to a nand gate or an and gate to implement an or logic function under negative logic.

The m-bit comparison output values output by each phase sampling comparison circuit are all sent to the m-bit input end of the phase delay protection circuit; the M edge detection signal gating switches z1-zm are used for connecting M bit trigger gating control values in M bit comparison output values to the input end of the NOR gate FY10, and when M is smaller than M, redundant input signals are not connected to the input end of the NOR gate FY 10; for example, when M equals 7 and M also equals 7, the edge detection signal gate switches z1-z7 are all turned on; when M is equal to 7, and M is equal to 3, the edge detection signal gating switch z1-z3 is turned on, z4-z7 is turned off, and the pull-down resistor RZ4-RZ7 pulls down the signal at the input end of the NOR gate FY10 behind the switch z4-z7 to low level, and at the moment, the non-trigger area control signal is generated by edge change in Y11-Y13. In embodiments 1 and 2 of the a-phase sampling comparison circuit, when M is smaller than M, other data in M-bit data other than the M-bit trigger strobe control value does not change, for example, when M is equal to 3 in embodiment 1 of the sampling comparison circuit, the remaining 4 bits output a constant low level, and no edge detection signal is generated; when M is equal to 5 in embodiment 2 of the sampling comparison circuit, the output of the remaining 5 bits is a constant high level, and no edge detection signal is generated; therefore, when M is smaller than M, even if all of the M-bit edge detection signals Y31-Y3M are connected to the input terminal of the nor gate FY10, the signals other than the M-bit trigger gate control value in the M-bit comparison output value do not cause a single pulse to be output in the no-trigger area control signal; therefore, when the sampling comparison circuit in embodiment 1 or embodiment 2 is used to output an m-bit comparison output value, the m pull-down resistors Rz1-Rz m and the m edge detection signal gate switches z1-zm in fig. 11 may be omitted, and the m-bit edge detection signals Y31-Y3m may be directly and entirely connected to the input terminal of the nor gate FY 10.

All gates in the delay protection circuit are powered by a single power supply + VCC 1. Fig. 12 is a diagram illustrating a part of relevant waveforms in the delay protection circuit. From the principle and requirements of the sampling comparison circuit, when the output A-phase trigger gating control value is normally changed, 2 bits are changed every time. In fig. 12, Y11 in the a-phase trigger strobe control value has a rising edge change and a falling edge change, respectively, and Y21 is the a-phase trigger strobe control value after Y11 delays by T1; in embodiment 1 of the delay detection circuit in fig. 8, T1 is determined by the magnitude of the product of the resistor RY0 and the capacitor CY0 (i.e., the magnitude of the time constant); in embodiment 2 of the delay detection circuit of fig. 9, T1 is determined by the product of the resistor RY3 and the capacitor CY 3; in the delay detection circuit embodiment 3 of fig. 10, T1 is determined by the gate delay time of the inverters FY11, FY12, FY13, and FY14 themselves. In fig. 12, the negative pulse width of the signal YP1 due to the rising edge of Y11 is T2; in the delay detection circuit embodiment 1 of fig. 8 and the delay detection circuit embodiment 3 of fig. 10, T2 is determined by the magnitude of the product of the resistor RY1 and the capacitor CY 1; in embodiment 2 of the delay detection circuit in fig. 9, T2 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 12, the negative pulse width generated by the falling edge of Y11 in the signal YP2 is T3; in the delay detection circuit embodiment 1 of fig. 8 and the delay detection circuit embodiment 3 of fig. 10, T3 is determined by the magnitude of the product of the resistor RY2 and the capacitor CY 2; in embodiment 2 of the delay detection circuit in fig. 9, T3 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 12, 2 positive pulses in the edge detection signal Y31 correspond to a negative pulse due to a rising edge of Y11 in the signal YP1 and a negative pulse due to a falling edge of Y11 in the signal YP2, respectively. When Y11 in the phase a trigger strobe control value of fig. 12 changes in rising edge, Y12 in the phase a trigger strobe control value changes in falling edge, and the corresponding edge detection signal Y32 generates a positive pulse correspondingly; when Y11 changes in the falling edge, Y12 in the a-phase trigger gate control value changes in the rising edge at the same time, and a positive pulse is generated in the corresponding edge detection signal Y32; during this period, the comparison output value signals including the trigger strobe control value signals other than Y11 and Y12 are unchanged, and the corresponding edge detection signals are all at low level, which is not shown in fig. 12. According to the logical or function of the non-trigger area control signal generation module, the width of the single pulse output by the non-trigger area control signal generation module is the same as the widest pulse width of the input pulses in the input edge detection signals, and the width difference is caused by the difference between the resistance and capacitance values of T2 and T3 determined in the different delay detection circuits. In fig. 12, the 1 st positive pulse in Y31 is wider than the 1 st positive pulse in Y32, the 2 nd positive pulse in Y31 is narrower than the 2 nd positive pulse in Y32, the 1 st negative pulse width in the no-trigger-region control signal P4A coincides with the 1 st positive pulse width in the edge-detection signal Y31, and the 2 nd negative pulse width in the no-trigger-region control signal P4A coincides with the 2 nd positive pulse width in the edge-detection signal Y32.

In the embodiment 1 of the delay detection circuit in the delay protection circuit of fig. 8, the delay time for the change of the trigger gating control value of the phase a to the leading edge of the single pulse of the corresponding control signal of the non-trigger area is the sum of the delay times of the gates FY1 and FY4 and FY10 in fig. 11, or the sum of the delay times of the gates FY3 and FY4 and FY10 in fig. 11; the selection range of the signal delay time T1 of the a-phase trigger gating control value determined by the product of the resistor RY0 and the capacitor CY0 is ms order of magnitude, obviously, is greater than the delay time of the a-phase trigger gating control value changing to the leading edge of the corresponding single pulse of the no-trigger area control signal, that is, the time of the delay change of the gradation coding value signal is later than the leading edge time of the single pulse output after the a-phase trigger gating control value is changed. Strictly speaking, T1 actually includes the sum of the delay time caused by resistor RY0 and capacitor CY0, and the delay time of gate FY 0. In embodiment 1 of fig. 8, when selecting parameters, the value of T2 and the value of T3 are both larger than the value of T1, so that the time when the gradation code value signal changes with delay meets the requirement that the time is earlier than the time of the trailing edge of the output single pulse after the a-phase trigger strobe control value changes.

In the embodiment 2 of the delay detection circuit in the delay protection circuit in fig. 9, the delay time for the change of the a-phase trigger gating control value to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY7 and FY9 and FY10 in fig. 11, or the sum of the delay times of the gates FY8 and FY9 and FY10 in fig. 11; t1 is a value of ms magnitude, and it is obvious that at this time, the signal delay time T1 of the a-phase trigger gate control value determined by the product of the resistor RY3 and the capacitor CY3 is longer than the delay time of the leading edge of the single pulse of the a-phase trigger gate control value when the a-phase trigger gate control value changes to the corresponding no-trigger-zone control signal, that is, the time of the delay change of the a-phase trigger gate control value signal is later than the leading edge of the single pulse output after the a-phase trigger gate control value changes. In the embodiment 2 of the delay detection circuit in fig. 9, both the time when the a-phase trigger gate control value signal changes in delay and the time when the trailing edge of the output single pulse after the a-phase trigger gate control value changes are affected by the change of the signal YP 0; the time when the delay of the A-phase trigger gating control value signal changes is the delay of the gate circuit FY6 after the signal YP0 changes; the trailing edge time of the single pulse output after the change of the A-phase trigger gate control value is the sum of the delay time of the signal YP0 after the change of the signal YP 7, the delay time of the signal YP 9 after the change of the signal YP 10 in the graph 11 and the delay time of the signal YP0 after the change of the signal YP 8, the delay time of the signal FY9 after the change of the signal YP0 in the graph 11 and the delay time of the signal FY10 in the graph 11; obviously, the time of the delayed change of the A-phase trigger gating control value signal is less than the time of the trailing edge of the single pulse output after the A-phase trigger gating control value is changed by 2 gate circuits, and the requirement that the time of the delayed change of the A-phase trigger gating control value signal is earlier than the time of the trailing edge of the single pulse output after the A-phase trigger gating control value is changed is met.

Fig. 13 is a trigger circuit embodiment of triggering the self-coupling compensation type three-phase main circuit unit of fig. 3 in the trigger unit, or triggering the triac SR1 in the a-phase main circuit of the self-coupling compensation type three-phase main circuit unit of fig. 4, and the trigger circuit embodiment is composed of an ac trigger optocoupler UG1, a resistor RG1, and a resistor RG2, and the trigger control signal P51 is active at a low level. The alternating current trigger optocoupler UG1 can be selected from phase-shifting bidirectional thyristor output optocouplers such as MOC3022, MOC3023, MOC3052 and MOC 3053. The power supply + VCCA is a controlled power supply of the A-phase trigger circuit controlled by the protection driving unit. The triggering circuits for triggering the triacs SR2-SR6 in the A-phase main circuit of the embodiment 1 of the auto-compensation three-phase main circuit unit of FIG. 3 or triggering the triacs SR2-SR8 in the A-phase main circuit of the embodiment 2 of the auto-compensation three-phase main circuit unit of FIG. 4 are controlled by an A-phase triggering control signal P5A, which is the same as the circuit structure for triggering the triacs SR1 in the A-phase main circuit. The trigger circuit structure for triggering all the bidirectional thyristors in the B-phase main circuit is the same as the circuit structure for triggering the SR1 in the A-phase main circuit, is controlled by a B-phase trigger control signal P5B, and the power supply is + VCCB and is a controlled power supply of the B-phase trigger circuit controlled by the protection driving unit. The trigger circuit structure for triggering all the bidirectional thyristors in the C-phase main circuit is the same as the circuit structure for triggering the bidirectional thyristor SR1 in the A-phase main circuit, is controlled by a C-phase trigger control signal P5C, and the power supply is + VCCC and is a controlled power supply of the C-phase trigger circuit controlled by the protection driving unit. The trigger pulses output by the alternating current trigger optocoupler UG1 in fig. 14 from G11 and G12 and the trigger pulses output by other alternating current trigger optocouplers in the trigger unit jointly form a trigger signal P6.

Fig. 14 is an embodiment 1 of an a-phase trigger strobe configuration circuit, which is used to implement a trigger strobe configuration when the trigger strobe control value is active high and M is equal to 7, i.e., M does not exceed 7, the trigger control signal is active low and N is equal to 6. In fig. 14, 42 diodes D11-D76, 42 configuration switches K11-K76, 7 trigger control row lines Y21-Y27, and 6 trigger drive column lines VK1-VK6 form a diode trigger configuration matrix, a resistor RS1-RS6 and a triode VS1-VS6 form a drive circuit of a-phase trigger control signals P51-P56, and a P51-P56 form an a-phase trigger control signal P5A to control 6 thyristors. At the crossing positions of 7 trigger control row lines Y21-Y27 and 6 trigger drive column lines VK1-VK6, configuration branches composed of diodes and configuration switches in series are arranged, the anode sides of the diodes of the configuration branches are connected to the trigger control row lines, and the cathode sides of the diodes of the configuration branches are connected to the trigger drive column lines.

The a-phase trigger gate configuration circuit embodiment 1 of fig. 14 is used for compensation control of an a-phase main circuit in the self-coupled compensated three-phase main circuit unit embodiment 1 of fig. 3; setting the fluctuation range of the phase voltage of the A-phase alternating current power supply to be 220V +/-10%, and requiring the phase voltage to be stabilized within the range of 220V +/-2% for output; at this time, the A-phase trigger gate control value is Y21-Y27 with 7 bits, and all of the 7 trigger control row lines Y21-Y27 in FIG. 14 are selected as trigger gate control row lines. Table 1 is a trigger strobe configuration table of the trigger strobe configuration circuit at this time, and lists the configuration states of the configuration switches in the diode trigger configuration matrix when the corresponding active trigger control signals are configured when the trigger strobe control values Y21-Y27 for 7 bits are respectively active. The trigger gating control values Y21-Y27 are respectively and effectively corresponding to the voltage class intervals 1-7, and the trigger gating configuration circuit controls the on-off state of the bidirectional thyristor in the phase a main circuit in the embodiment 1 of the self-coupling compensation type three-phase main circuit unit to perform corresponding voltage compensation through the trigger control signal according to the trigger gating control values.

In table 1, the listed configuration switches need to be configured in the on state, and the unlisted configuration switches need to be configured in the off state; a total of 14 configuration switches in table 1 need to be configured in the on state. When a certain trigger gating control row line is effective, the configuration switch between the trigger driving row lines of the bidirectional thyristor which needs to be conducted in the corresponding on-off combination state when the certain trigger gating control row line is effective is configured to be in a conducting state, and the configuration switch is connected through the diode, so that the trigger driving row line of the bidirectional thyristor which needs to be conducted is effective. For example, when the input voltage level of the phase a is the lowest voltage level 1, that is, Y21 is at a high level, K11 and K16 in the diode trigger configuration matrix are turned on to turn on diodes D11 and D16, trigger drive row lines VK1 and VK6 to be at a high level to control the triodes VS1 and VS6 to be turned on respectively to turn on P51 and P56 to effectively turn on the triacs SR1 and SR6, and the other diodes in the diode trigger configuration matrix are turned off to control the other triacs to be turned off, and output voltage U12+ U23 is used for forward compensation of the excitation coil voltage of TB 1; when the input voltage is in a voltage class 2, namely Y22 is effectively in a high level, K23 and K26 in the diode trigger configuration matrix are conducted to enable diodes D23 and D26 to be conducted, triodes VS3 and VS6 are respectively controlled to be conducted to enable P53 and P56 to effectively turn on bidirectional thyristors SR3 and SR6 when trigger drive row lines VK3 and VK6 are in a high level, other diodes in the diode trigger configuration matrix are cut off to control the other bidirectional thyristors to be turned off, and only output voltage U23 is used for forward compensation of excitation coil voltage of TB 1; when the input voltage is at a voltage level of 4, namely Y24 is effectively at a high level, K45 and K46 in the diode trigger configuration matrix are conducted to enable diodes D45 and D46 to be conducted, triodes VS5 and VS6 are respectively controlled to be conducted to enable P55 and P56 to effectively turn on bidirectional thyristors SR5 and SR6 when trigger driving row lines VK5 and VK6 are at a high level, and other diodes in the diode trigger configuration matrix are cut off to control other bidirectional thyristors to be turned off, so that 0-voltage compensation is realized; when the input voltage is at voltage level 5, namely Y25 is effectively at a high level, K52 and K53 in the diode trigger configuration matrix are conducted to enable diodes D52 and D53 to be conducted, triodes VS2 and VS3 are respectively controlled to be conducted to enable P52 and P53 to effectively turn on bidirectional thyristors SR2 and SR3 when trigger drive row lines VK2 and VK3 are at a high level, other diodes in the diode trigger configuration matrix are cut off to control the other bidirectional thyristors to be turned off, and the reverse output voltage U12 is only adopted to carry out reverse compensation on the excitation coil voltage of TB 1; and so on.

TABLE 1

The a-phase trigger gate configuration circuit embodiment 1 of fig. 14 is used for compensation control of an a-phase main circuit in the self-coupling compensation type three-phase main circuit unit embodiment 1 of fig. 3, the fluctuation range of a-phase alternating current power supply phase voltage is 220V ± 10%, and the a-phase alternating current power supply phase voltage is required to be stabilized within a range of 220V ± 4% for output; at this time, the A-phase trigger strobe control value is Y21-Y23 with 3 bits, and 3 trigger control row lines Y21-Y23 in FIG. 14 are selected as the trigger strobe control row lines. Table 2 is a trigger strobe configuration table of the trigger strobe configuration circuit at this time, which lists the configuration states of the configuration switches in the diode trigger configuration matrix when the corresponding active trigger control signals are configured when the trigger strobe control values Y21-Y23 for 3 bits are respectively active. The A-phase trigger strobe control values Y21-Y23 effectively correspond to voltage level intervals 1-3, respectively.

In table 2, the listed configuration switches need to be configured in the on state, and the unlisted configuration switches need to be configured in the off state; in table 2, a total of 6 configuration switches need to be configured in the on state. When the A-phase input voltage is in a voltage level 1, namely Y21 is effectively in a high level, K13 and K16 in a diode trigger configuration matrix are conducted, diodes D13 and D16 are conducted, trigger driving row lines VK3 and VK6 are in a high level and respectively control triodes VS3 and VS6 to be conducted, so that P53 and P56 are effectively turned on bidirectional thyristors SR3 and SR6, other diodes in the diode trigger configuration matrix are turned off, other bidirectional thyristors are controlled to be turned off, and forward compensation is performed by only using an output voltage U23 as an excitation coil voltage of TB 1; when the input voltage is in a voltage class 2, namely Y22 is effectively in a high level, K25 and K26 in the diode trigger configuration matrix are conducted to enable diodes D25 and D26 to be conducted, the trigger drive row lines VK5 and VK6 are in a high level and respectively control triodes VS5 and VS6 to be conducted to enable P55 and P56 to effectively turn on bidirectional thyristors SR5 and SR6, and other diodes in the diode trigger configuration matrix are turned off to control other bidirectional thyristors to be turned off, so that 0-voltage compensation is realized; when the input voltage is in a voltage class 3, namely Y23 is effectively in a high level, K34 and K35 in the diode trigger configuration matrix are conducted to enable diodes D34 and D35 to be conducted, triodes VS4 and VS5 are controlled to be conducted to enable P54 and P55 to effectively turn on bidirectional thyristors SR4 and SR5 respectively when trigger drive row lines VK4 and VK5 are in a high level, other diodes in the diode trigger configuration matrix are turned off to control the other bidirectional thyristors to be turned off, and the excitation coil voltage of TB1 is reversely compensated by only adopting a reverse output voltage U23.

TABLE 2

Fig. 15 shows an embodiment 2 of the a-phase trigger strobe configuration circuit, which is used to implement the trigger strobe configuration when the trigger strobe control value is active low and M is equal to 10, i.e. M does not exceed 10, and the trigger control signal is active low and 8, i.e. N is equal to 8. In fig. 15, 80 diodes D01-D98, 80 configuration switches K01-K98, 10 trigger control row lines Y21-Y210, and 8 trigger driving column lines VK1-VK8 form a diode trigger configuration matrix, and 8 trigger driving column lines VK1-VK8 in the diode trigger configuration matrix directly output low-level active a-phase trigger control signals P51-P58 to form P5A. At the crossing positions of 10 trigger control row lines Y21-Y210 and 8 trigger driving column lines VK1-VK8, configuration branches composed of diodes and configuration switches connected in series are arranged, the cathode sides of the diodes of the configuration branches are connected to the trigger control row lines, and the anode sides of the diodes of the configuration branches are connected to the trigger driving column lines. The main difference between the embodiment 2 of the trigger gating configuration circuit in fig. 15 and the embodiment 1 of the trigger gating configuration circuit in fig. 14 is that the trigger gating control value is active at low level, and the diode which is conducted by the active low level of the trigger gating control value is directly used as the driving source of the light emitting diode at the input end of the multiple ac trigger optocouplers without a trigger control signal driving circuit.

Using the a-phase trigger gate configuration circuit embodiment 2 of fig. 15 for compensation control of the a-phase main circuit in the self-coupled compensated three-phase main circuit unit embodiment 2 of fig. 4; setting the fluctuation range of the phase voltage of the A-phase alternating current power supply to be 220V + 10% to 220V-20%, and requiring the phase voltage to be stabilized within the range of 220V +/-2% for output; at this time, the A-phase trigger strobe control value is Y21-Y210 with 10 bits, and all of the 10 trigger control row lines Y21-Y210 in FIG. 15 are selected as trigger strobe control row lines. Table 3 is a trigger strobe configuration table of the trigger strobe configuration circuit at this time, which lists the configuration states of the configuration switches in the diode trigger configuration matrix when the corresponding active trigger control signals are configured when the trigger strobe control values Y21-Y210 for 10 bits are respectively active. The trigger gating control values Y21-Y210 effectively correspond to the voltage class intervals 1-10, respectively, and the trigger gating configuration circuit controls the on-off state of the triac in the a-phase main circuit in embodiment 2 of the self-coupling compensation type three-phase main circuit unit to perform corresponding voltage compensation according to the trigger gating control values through the trigger control signals.

In table 3, the listed configuration switches need to be configured in the on state, and the unlisted configuration switches need to be configured in the off state; a total of 20 configuration switches in table 3 need to be configured in the on state. When a certain trigger gating control row line is effective, the configuration switch between the trigger driving row lines of the bidirectional thyristor which needs to be conducted in the corresponding on-off combination state when the certain trigger gating control row line is effective is configured to be in a conducting state, and the configuration switch is connected through the diode, so that the trigger driving row line of the bidirectional thyristor which needs to be conducted is effective. For example, when the input voltage of the a-phase is at voltage level 7, that is, Y27 is at a low level, K77 and K78 in the diode trigger configuration matrix are turned on to turn on diodes D77 and D78, trigger drive row lines VK7 and VK8 to be at a low level to turn on bidirectional thyristors SR7 and SR8, and other diodes in the diode trigger configuration matrix are turned off to turn off other bidirectional thyristors, so that 0-voltage compensation is realized, that is, the excitation voltage of TB1 is 0; when the input voltage is at a voltage level of 8, namely Y28 is at a low level, K82 and K83 in the diode trigger configuration matrix are conducted to enable diodes D82 and D83 to be conducted, trigger driving row lines VK2 and VK3 to be at a low level to turn on bidirectional thyristors SR2 and SR3, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and reverse output voltage U12 is only adopted to carry out reverse compensation on excitation coil voltage of TB 1; when the input voltage is in a voltage class of 10, namely Y210 is effectively in a low level, K04 and K05 in the diode trigger configuration matrix are conducted, diodes D04 and D05 are conducted, row lines VK4 and VK5 are triggered and driven to be in a low level to turn on bidirectional thyristors SR4 and SR5, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and reverse output voltage U23 is only adopted to be used as excitation coil voltage of TB1 for reverse compensation; when the input voltage is at voltage level 6, namely Y26 is at low level effectively, K61 and K64 in the diode trigger configuration matrix are conducted, diodes D61 and D64 are conducted, row lines VK1 and VK4 are triggered and driven to be at low level to turn on bidirectional thyristors SR1 and SR4, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and only the output voltage U12 is used as the excitation coil voltage of TB1 to perform forward compensation; when the input voltage is in a voltage class of 4, namely Y24 is effectively in a low level, K43 and K46 in the diode trigger configuration matrix are conducted, diodes D43 and D46 are conducted, trigger driving row lines VK3 and VK6 to be in a low level to turn on bidirectional thyristors SR3 and SR6, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and forward compensation is carried out by only adopting an output voltage U23 as the excitation coil voltage of TB 1; when the input voltage is in a voltage class 1, namely Y21 is effectively in a low level, K11 and K18 in the diode trigger configuration matrix are conducted, diodes D11 and D18 are conducted, row lines VK1 and VK8 are triggered and driven to be in a low level to turn on bidirectional thyristors SR1 and R8, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and output voltage U12+ U23+ U34 is adopted to serve as excitation coil voltage of TB1 for forward compensation; and so on.

TABLE 3

Using the a-phase trigger gate configuration circuit embodiment 2 of fig. 15 for compensation control of the a-phase main circuit in the self-coupled compensated three-phase main circuit unit embodiment 2 of fig. 4; setting the fluctuation range of the phase voltage of the A-phase alternating current power supply to be 220V +/-15%, and requiring the phase voltage to be stabilized within the range of 220V +/-3.5% for output; at this time, the A-phase trigger gate control value is Y21-Y25 with 5 bits, and 5 trigger control row lines Y21-Y25 in FIG. 15 are selected as the trigger gate control row lines. Table 4 is a trigger strobe configuration table of the trigger strobe configuration circuit at this time, which lists the configuration states of the configuration switches in the diode trigger configuration matrix when the corresponding active trigger control signals are configured when the trigger strobe control values Y21-Y25 for 5 bits are respectively active. The trigger gating control values Y21-Y25 are respectively and effectively corresponding to the voltage class intervals 1-5, and the trigger gating configuration circuit controls the on-off state of the bidirectional thyristor in the a-phase main circuit in the embodiment 2 of the self-coupling compensation type three-phase main circuit unit to perform corresponding voltage compensation according to the trigger gating control values through trigger control signals.

In table 4, the listed configuration switches need to be configured in the on state, and the unlisted configuration switches need to be configured in the off state; a total of 10 configuration switches in table 4 need to be configured in the on state. For example, when the input voltage of the a phase is at voltage level 3, that is, Y23 is at a low level, K37 and K38 in the diode trigger configuration matrix are turned on to turn on diodes D37 and D38, trigger drive row lines VK7 and VK8 are at a low level to turn on bidirectional thyristors SR7 and SR8, and other diodes in the diode trigger configuration matrix are turned off to turn off other bidirectional thyristors, thereby implementing 0-voltage compensation; when the input voltage is in a voltage class 1, namely Y21 is effectively in a low level, K11 and K16 in the diode trigger configuration matrix are conducted, diodes D11 and D16 are conducted, the row lines VK1 and VK6 are triggered and driven to be in a low level to turn on bidirectional thyristors SR1 and SR6, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and the output voltage U12+ U23 is used as the excitation coil voltage of TB1 for forward compensation; when the input voltage is in a voltage class of 4, namely Y24 is effectively in a low level, K46 and K47 in the diode trigger configuration matrix are conducted, so that diodes D46 and D47 are conducted, row lines VK6 and VK7 are triggered and driven to be in a low level to turn on bidirectional thyristors SR6 and SR7, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and the reverse output voltage U34 is only used as the excitation coil voltage of TB1 for reverse compensation; and so on.

TABLE 4

The embodiment 2 of the a-phase trigger gating configuration circuit in fig. 15 is used for compensating and controlling the a-phase main circuit in the embodiment 2 of the self-coupling compensation type three-phase main circuit unit in fig. 4, and a low level in a trigger gating control value needs to directly drive the input end light emitting diodes of 2 ac trigger optocouplers to emit light; when the alternating current trigger optocoupler selects MOC3022, MOC3052 and the like, a driving current of 20mA is needed; when the alternating current trigger optocoupler selects MOC3023, MOC3053 and the like, 10mA of driving current is needed. The embodiment 2 of the trigger gating configuration circuit in fig. 15 may also be used to perform compensation control on the a-phase main circuit in the embodiment 1 of the self-coupling compensation type three-phase main circuit unit in fig. 3, and at this time, the low level in the trigger gating control value also needs to directly drive the input end light emitting diodes of the 2 ac trigger optocouplers to emit light.

Embodiment 1 of the a-phase trigger gate configuration circuit of fig. 14 can also be used to perform compensation control on the a-phase main circuit of embodiment 2 of the self-coupled compensated three-phase main circuit unit of fig. 4, in which case, the number of trigger control row lines and the number of trigger driving column lines need to be increased. When fig. 14 and fig. 15 are expanded, the diode trigger configuration matrix needs to be provided with a configuration branch consisting of a diode and a configuration switch in series at all intersections of the trigger control row line and the trigger drive column line.

The B-phase and C-phase trigger gating configuration circuits adopt the same trigger gating configuration circuit as the A-phase, and the configuration switches in the respective diode trigger configuration matrixes adopt the same configuration method and configuration state as the A-phase.

The error detection judging circuit has the function that when judging that only one of M bits of the trigger gating control value is valid, the output trigger gating control value judging signal is enabled, otherwise, the output trigger gating control value judging signal is disabled; that is, when more than one bit of the M bits of the trigger strobe control value is valid or no bit is valid, the output trigger strobe control value discrimination signal is invalidated.

Fig. 16 shows an a-phase error detection and determination circuit in embodiment 1, which inputs a-phase trigger strobe control values Y21-Y27, and determines a trigger strobe control value P3A with m being 7, i.e., 7 bits at most, which is active at high level; the output A-phase trigger gating control value judging signal P7A is effective in high level and ineffective in low level; namely, the output P7A is 1, which indicates that the A-phase trigger gating control value is valid; output P7A is 0 indicating that the a-phase trigger strobe control value is invalid. In fig. 16, FD3 is a ROM memory having a 7-bit address input and a 1-bit data output, 7-bit trigger strobe control values Y21-Y27 are connected to the 7-bit address inputs a0-a6 via strobe switches k1-k7, respectively, and a trigger strobe control value decision signal P7A is output from the data output terminal D0; pull-down resistors RX1-RX7 are used to pull down the corresponding ROM memory input signal to a low level when the gate switches are open. Table 5 is a logic truth table of the phase a error detection and determination circuit in embodiment 1, and is also a table of cell contents data of the ROM memory in fig. 16. The contents of the ROM memory storage unit in fig. 16 are written in accordance with the data of table 5. If the input a-phase trigger gate control value P3A is 7 bits, i.e., M is equal to 7, the gate switches k1-k7 in fig. 16 are all closed, and the 7-bit trigger gate control values Y21-Y27 are all actually input to the 7-bit address inputs a0-a6 of the ROM memory. In table 5, only one of the 7 bits Y21-Y27 of the trigger strobe control value is valid 1, the output a-phase trigger strobe control value decision signal P7A is made valid 1, otherwise the output a-phase trigger strobe control value decision signal P7A is made invalid 0, which satisfies the functional requirements of the error detection decision circuit.

TABLE 5

In fig. 16, if the input a-phase trigger gate control value P3A is 3 bits, i.e., M equals to 3, the gate switches k1-k3 in fig. 16 are closed, and k4-k7 are opened; the 3-bit trigger strobe control value Y21-Y23 is actually input to the 3-bit address input A0-A2 of the ROM memory, and the other 4-bit address input A3-A6 of the ROM memory is pulled down to 0 by a pull-down resistor; at this time, the input conditions of the 4 th to 7 th rows in table 5 cannot be generated, and only one of the 3 bits Y21 to Y23 of the a-phase trigger strobe control value is valid 1, the output a-phase trigger strobe control value determination signal P7A is made to be valid 1, otherwise the output a-phase trigger strobe control value determination signal P7A is made to be invalid 0, so as to satisfy the functional requirements of the error detection determination circuit.

In fig. 16, if the trigger strobe control value determination signal P7A to be output is active low and inactive high, all the contents of the last 1 column data in table 5 need to be changed from 0 to 1 and from 1 to 0.

Fig. 17 shows an a-phase error detection and determination circuit in embodiment 2, in which the input a-phase trigger strobe control value P3A is Y21-Y210, and is determined for a-phase trigger strobe control value P3A which is active at low level and m is 10, i.e., 10 bits at most; the output A-phase trigger gating control value judging signal P7A is effective in high level and ineffective in low level; namely, the output P7A is 1, which indicates that the A-phase trigger gating control value is valid; output P7A is 0 indicating that the a-phase trigger strobe control value is invalid. In fig. 17, FD4 is a ROM memory having a 10-bit address input and a 1-bit data output, 10-bit flip-flop strobe control values Y21-Y210 are connected to 10-bit address inputs a0-a9 via strobe switches j1-j10, respectively, and an a-phase flip-flop strobe control value decision signal P7A is output from a data output terminal D0; pull-up resistors RJ1-RJ10 are used to pull up the corresponding ROM memory input signal to a high level when the gating switches are open. Table 6 is a logical truth table of the error detection and discrimination circuit in embodiment 2, and is also a table of contents data of the ROM memory in fig. 17.

The contents of the ROM memory storage unit in fig. 17 are written in accordance with the data of table 6. If the input a-phase trigger strobe control value P3A is 10 bits, i.e., M equals 10, then the strobe switches j1-j10 in fig. 17 are all closed and the 10-bit trigger strobe control values Y21-Y210 are all actually input to the 10-bit address input a0-a9 of the ROM memory. In table 6, when only one of the 10 bits Y21-Y210 of the a-phase trigger strobe control value is valid 1, the output a-phase trigger strobe control value determination signal P7A is made to be valid 1, otherwise, the output a-phase trigger strobe control value determination signal P7A is made to be invalid 0, which satisfies the functional requirement of the error detection determination circuit.

TABLE 6

In FIG. 17, if the input trigger gate control value P3A is 5 bits, i.e., M equals to 5, then the gate switches k1-k5 in FIG. 17 are closed and k6-k10 are opened; the 5-bit trigger strobe control value Y21-Y25 is actually input to 9-bit address input A0-A4 of the ROM memory, and the other 5-bit address input A5-A9 of the ROM memory are pulled up to be 1 by a pull-up resistor; at this time, the input conditions of the rows 6 to 10 in table 6 cannot be generated, and only one of the 5 bits Y21 to Y25 of the a-phase trigger strobe control value is valid 0, the output a-phase trigger strobe control value determination signal P7A is made to be valid 1, otherwise the output a-phase trigger strobe control value determination signal P7A is made to be invalid 0, so as to meet the functional requirements of the error detection determination circuit.

In fig. 17, if the trigger strobe control value determination signal P7A to be output is active at low and inactive at high, all the contents of the data in the last 1 column in table 6 need to be changed from 0 to 1 and from 1 to 0.

In

embodiments

1 and 2 of the sampling comparison circuit, when M is smaller than M, except for the M-bit trigger strobe control value, the state of other comparison output values of M-M bits and the delayed state of the signals sent to the phase delay protection circuit by the sampling comparison circuit are the same as the state of an invalid bit in the M-bit trigger strobe control value, and the judgment on whether the M-bit trigger strobe control value of the phase is valid or not is not influenced; thus, at this time, the gate switches k1-k7 and the pull-down resistors RX1-RX7 in FIG. 16 may be eliminated, and the 7-bit comparison output values Y21-Y27 are directly connected to the 7-bit address inputs A0-A6 of the ROM memory; the gating switches j1-j10 and pull-up resistors RJ1-RJ10 in FIG. 17 may be eliminated, and the 10-bit comparison output values Y21-Y210 may be directly connected to the 10-bit address inputs A0-A9 of the ROM memory.

The logic function of the error detection and discrimination circuit can also be realized in other ways, for example, tables 5 and 6 are logic truth tables, and the function can be realized by combining with or not logic gate. The ROM memory in the error detection judging circuit or the logic gate is adopted to realize the function, and the single power supply + VCC1 is adopted to supply power.

The phase B and phase C error detection discrimination circuits adopt the same phase A error detection discrimination circuit. The function of the B-phase error detection judging circuit is to enable the output B-phase trigger gating control value judging signal P7B to be effective when judging that only one of M bits of the B-phase trigger gating control value P3B is effective, or to enable the output B-phase trigger gating control value judging signal P7B to be ineffective; the function of the C-phase error detection and determination circuit is to enable the output C-phase trigger strobe control value determination signal P7C when only one of the M bits of the C-phase trigger strobe control value P3C is determined to be valid, and to disable the output C-phase trigger strobe control value determination signal P7C otherwise.

Fig. 18 shows an embodiment of a protection driving unit, wherein the input a-phase, B-phase and B-phase trigger gate control value determination signals P7A, P7B and P7C are all set to be active at high level and inactive at low level; for example, a value of 1 in P7A indicates that the a-phase trigger strobe control value discrimination signal is active, and a value of 0 in P7A indicates that the a-phase trigger strobe control value discrimination signal is inactive. Setting the low level of input A-phase, B-phase and B-phase non-trigger area control signals P4A, P4B and P4C to be effective and the high level to be ineffective; for example, when P4A is 0, it indicates that there is fluctuation in the ac-phase-a phase current supply phase voltage, so that the a-phase trigger gating control value changes, and switching of the on-off state of the bidirectional thyristor in the a-phase thyristor switch group needs to be performed, so as to change the compensation mode; in the switching process, in order to avoid that 2 or more than 2 thyristors are simultaneously conducted in the thyristors at the same side due to the delayed turn-off factor of the bidirectional thyristors, and a power supply short circuit is caused, all the bidirectional thyristors in the phase a thyristor switch group are turned off in the effective period of the control signal of the non-trigger area, namely when the P4A of the embodiment is equal to 0.

In fig. 18, an and gate FY21, a transistor VT, a freewheeling diode VD, a resistor RK1, a relay coil KA, a relay coil KB, and a relay coil KC form a protection control circuit; the A-phase trigger circuit controlled power supply + VCCA control circuit consists of an AND gate FY22, a triode VK1, a triode VK2, a resistor RK2 and a resistor RK 3; the B-phase trigger circuit controlled power supply + VCCB control circuit is composed of an AND gate FY23, a triode VK3, a triode VK4, a resistor RK4 and a resistor RK 5; and the AND gate FY24, the triode VK5, the triode VK6, the resistor RK6 and the resistor RK7 form a C-phase trigger circuit controlled power supply + VCCC control circuit. The AND gates FY21, FY22, FY23 and FY24 are all powered by a single power supply + VCC 1; + VCC2 is the power supply for the relay coil and the source for the trigger circuit controlled power supply.

In fig. 18, when one of the input a-phase trigger gating control value determining signal P7A, B-phase trigger gating control value determining signal P7B, and C-phase trigger gating control value determining signal P7C is at a low level, that is, one of the a-phase trigger gating control value, B-phase trigger gating control value, and C-phase trigger gating control value is invalid, the output P7K of the and gate FY21 is at a low level, the control transistor VT is turned off, and the relay coil KA is de-energized, so that the self-coupled compensation three-phase main circuit unit embodiment 1 in fig. 3 or the relay normally open switch KA-1 in the self-coupled compensation three-phase main circuit unit embodiment 2 in fig. 4 is turned off, that is, the input-side supply voltage of the self-coupled transformer is controlled to be turned off, and the voltage between all taps of the self-coupled transformer is set to be 0, thereby protecting the thyristor; the normally closed relay switch KA-2 is closed, and the voltage applied to the excitation coil of TB1 is set to 0. And the triode VT is cut off, and simultaneously the relay coil KB and the relay coil KC are controlled to lose power, so that corresponding relay switches in the B-phase main circuit and the C-phase main circuit execute the same action as the relay switch of the A-phase main circuit, and the B-phase thyristor switch group and the C-phase thyristor switch group are protected. The output P7K of the AND gate FY21 is low level, meanwhile, the AND gates FY22, FY23 and FY24 output low level, the triodes VK1, VK2, VK3, VK4, VK5 and VK6 are all cut off, the controlled power supplies + VCCA, + VCCB and + VCCC are all power-off, and the A-phase trigger circuit, the B-phase trigger circuit and the C-phase trigger circuit in the trigger unit do not work because of no power supply, namely, trigger pulses for triggering the bidirectional thyristor are not all sent out. Therefore, as long as one phase of the three-phase trigger gating control value is invalid, the protection driving unit cuts off the power supply of the trigger unit no matter whether the input three-phase non-trigger area control signal is valid or not, stops sending out the trigger pulse of all the bidirectional thyristors, and simultaneously controls and disconnects the input side power supply voltage of the three-phase autotransformer, thereby realizing the protection of the three-phase thyristor switch group.

In fig. 18, when the input a-phase trigger gate control value determination signal P7A, B-phase trigger gate control value determination signal P7B, and C-phase trigger gate control value determination signal P7C are all at high level, that is, the a-phase trigger gate control value, B-phase trigger gate control value, and C-phase trigger gate control value are all valid, the output P7K of the and gate FY21 is at high level, the transistor VT is turned on, and the relay coil KA is controlled to be electrically coupled, so that the compensation type three-phase main circuit unit embodiment 1 in fig. 3, or the relay normally open switch KA-1 in the compensation type three-phase main circuit unit embodiment 2 in fig. 4 is turned on, the relay normally closed switch KA-2 is turned off, and the circuit is in the compensation working state. And the triode VT is conducted, and meanwhile, the relay coil KB and the relay coil KC are controlled to be electrified, so that corresponding relay switches in the B-phase main circuit and the C-phase main circuit execute the same action as the relay switch of the A-phase main circuit, and the B-phase thyristor switch group and the C-phase thyristor switch group are in a compensation working state.

In fig. 18, when all three-phase trigger gating control values are active and P7K is at a high level, when the a-phase non-trigger area control signal is active, that is, P4A is equal to 0, the and gate FY22 outputs a low level, the triodes VK1 and VK2 are turned off, the controlled power supply + VCCA loses power, the a-phase trigger circuit does not work, that is, the trigger pulse for triggering the bidirectional thyristors in the a-phase thyristor switch group is not sent out, all the bidirectional thyristors in the a-phase thyristor switch group are turned off, which indicates that at this time, the phase voltage of the a-phase ac power supply fluctuates, so that the a-phase trigger gating control value changes, and the on-off state of the bidirectional thyristors in the a-phase thyristor switch group needs to be. When the three-phase trigger gating control values are all effective and the P7K is at a high level, when the control signal of the A-phase non-trigger area is ineffective, namely P4A is equal to 1, the AND gate FY22 outputs a high level, the triodes VK1 and VK2 are both conducted, the controlled power supply + VCCA is electrified, the A-phase trigger circuit normally works, the A-phase trigger gating configuration circuit selects the corresponding A-phase trigger control signal to be effective according to the effective A-phase trigger gating control value corresponding to a certain voltage grade interval, so that the A-phase trigger circuit sends out trigger pulses to control the on-off state of the bidirectional thyristors in the A-phase thyristor switch group, and the A-phase main circuit is in a compensation working state corresponding to the voltage grade interval.

In fig. 18, when all three-phase trigger gating control values are active and P7K is at a high level, when a B-phase non-trigger zone control signal is active, that is, P4B is equal to 0, the and gate FY23 outputs a low level, the triodes VK3 and VK4 are turned off, the controlled power supply + VCCB loses power, the B-phase trigger circuit does not work, that is, a trigger pulse for triggering the bidirectional thyristors in the B-phase thyristor switch group is not sent out, all the bidirectional thyristors in the B-phase thyristor switch group are turned off, which indicates that at this time, a phase voltage of the B-phase ac power supply fluctuates, so that the B-phase trigger gating control value changes, and switching of the on-off states of the bidirectional thyristors in the B-phase thyristor switch group is. When the three-phase trigger gating control values are all effective and the P7K is at a high level, when the control signal of the B-phase non-trigger area is ineffective, namely P4B is equal to 1, the AND gate FY23 outputs a high level, the triodes VK3 and VK4 are both conducted, the controlled power supply + VCCB is electrified, the B-phase trigger circuit works normally, the B-phase trigger gating configuration circuit selects the corresponding B-phase trigger control signal to be effective according to the effective B-phase trigger gating control value corresponding to a certain voltage grade interval, so that the B-phase trigger circuit sends out trigger pulses to control the on-off state of the bidirectional thyristors in the B-phase thyristor switch group, and the B-phase main circuit is in a compensation working state corresponding to the voltage grade interval.

In fig. 18, when all three-phase trigger gating control values are active and P7K is at a high level, when a C-phase non-trigger zone control signal is active, that is, P4C is equal to 0, the and gate FY24 outputs a low level, the triodes VK5 and VK6 are turned off, the controlled power supply + VCCC loses power, the C-phase trigger circuit does not work, that is, a trigger pulse for triggering the bidirectional thyristors in the C-phase thyristor switch group is not sent out, all the bidirectional thyristors in the C-phase thyristor switch group are turned off, which indicates that at this time, the phase voltage of the C-phase ac power supply fluctuates, so that the C-phase trigger gating control value changes, and the on-off state of the bidirectional thyristors in the C-phase thyristor switch group needs to be. When the three-phase trigger gating control values are all effective and the P7K is at a high level, when the control signal of the C-phase non-trigger area is ineffective, namely P4C is equal to 1, the AND gate FY24 outputs a high level, the triodes VK5 and VK6 are both conducted, the controlled power supply + VCCC is powered on, the C-phase trigger circuit works normally, the C-phase trigger gating configuration circuit selects the corresponding C-phase trigger control signal to be effective according to the effective C-phase trigger gating control value corresponding to a certain voltage grade interval, so that the C-phase trigger circuit sends out trigger pulses to control the on-off state of the bidirectional thyristors in the C-phase thyristor switch group, and the C-phase main circuit is in a compensation working state corresponding to the voltage grade interval.

When one phase of trigger gating control value is invalid in the three-phase trigger gating control values, the protection driving unit sends a protection control signal to the three-phase main circuit to enable the three-phase thyristor switch group to be in a protection state, the three-phase alternating current voltage stabilizing device does not compensate input voltage, and the voltage output by the voltage stabilizer is the voltage of the input three-phase alternating current power supply. When the thyristor switch group is in a protection state, if the three-phase trigger gating control values are all restored to be effective signals, the protection driving unit automatically stops the protection state of the three-phase thyristor switch group, and the three-phase thyristor switch group is in a compensation working state again.

As can be known from the above embodiments and the working processes thereof, when the input is an effective trigger gating control value, the trigger gating configuration circuit of each phase ensures that thyristors at the same side in the thyristor switch group of the phase are not conducted at the same time, thereby realizing the interlocking control of the thyristors; when the trigger gating control value is invalid, the protection driving unit cuts off the power supply of the trigger unit rapidly, and on the basis of avoiding short circuit caused by error conduction of the bidirectional thyristor, the power supply voltage of the input side of all the autotransformers in three phases is cut off simultaneously, so that the three-phase thyristor switch group is in a protection state. When the three-phase thyristor switch group is in a protection state, if the three-phase error detection judging circuit judges that the three-phase trigger gating control values are all recovered to be effective signals, the protection state of the three-phase thyristor switch group can be automatically stopped and the three-phase thyristor switch group is enabled to be in a compensation working state again. The function effectively strengthens the protection force of the three-phase alternating-current voltage stabilizing device against the abnormity of the working process, so that the three-phase alternating-current voltage stabilizing device works more reliably.

Besides the technical features described in the specification, other techniques of the three-phase ac voltage stabilizer are conventional techniques which are known to those skilled in the art.

Claims

1. The utility model provides a three-phase exchanges voltage regulator device which characterized in that: the self-coupling compensation type three-phase main circuit unit comprises a self-coupling compensation type three-phase main circuit unit, a compensation control unit, a trigger unit and a protection driving unit;

each phase main circuit of the self-coupling compensation type three-phase main circuit unit comprises a compensation transformer, a self-coupling transformer, a thyristor switch group and a relay protection circuit;

the compensation control unit outputs a three-phase trigger control signal to the trigger unit; the trigger unit sends a trigger signal to the compensation type three-phase main circuit unit according to an input trigger control signal to control the on-off of the thyristors in the three-phase thyristor switch group; the compensation control unit simultaneously outputs a three-phase non-triggering area control signal and a three-phase triggering gating control value judging signal to the protection driving unit, the protection driving unit stops/starts protection of the three-phase thyristor switch group according to whether the input three-phase triggering gating control value judging signal is effective or not, and controls a power supply of the triggering unit according to whether the three-phase triggering gating control value judging signal is effective or not and whether the three-phase non-triggering area control signal is effective or not;

the compensation control unit consists of three compensation control circuits with the same structure; the compensation control circuit comprises a sampling comparison circuit, a delay protection circuit and a trigger gating configuration circuit; the sampling comparison circuit samples the voltage of the alternating current power supply phase voltage, outputs a trigger gating control value and sends the trigger gating control value to the delay protection circuit; the delayed trigger gating control value is sent to a trigger gating configuration circuit; the trigger gating configuration circuit outputs a trigger control signal;

each phase sampling comparison circuit comprises m-1 comparators, an upper limit threshold potentiometer and a lower limit threshold potentiometer; the upper limit threshold potentiometer and the lower limit threshold potentiometer are adjusted to adjust the voltage in the alternating current power supply phase voltage fluctuation interval range to M voltage level intervals, and M-bit trigger gating control values are output; m voltage grade intervals correspond to M trigger gating control values one by one; m is greater than or equal to 3, and M is less than or equal to M;

each phase voltage grade interval corresponds to a voltage compensation state one by one, and each voltage grade interval corresponds to a voltage compensation state; the different voltage compensation states are controlled by different on-off combination states of thyristors in the thyristor switch group; the trigger gating configuration circuit selects and enables a corresponding trigger control signal to be effective by the diode trigger configuration matrix according to the trigger gating control value, and controls the on-off combination state of the thyristors in the thyristor switch group;

the thyristor switch group in each phase has N thyristors; the diode trigger configuration matrix comprises m trigger control row lines and N trigger drive column lines; the N triggering driving column lines correspond to the N thyristors one by one, and the signal of one triggering driving column line effectively corresponds to the triggering control signal of one thyristor;

a configuration branch circuit formed by connecting a diode and a configuration switch in series is arranged at the crossing position of each trigger control row line and each trigger driving column line; when the trigger control row line signal is active at a low level, the cathode side of the diode of the configuration branch is connected to the trigger control row line, and the anode side of the diode of the configuration branch is connected to the trigger driving column line; when the trigger control row line signal is high level and effective, the anode side of the diode of the configuration branch is connected to the trigger control row line, and the cathode side of the diode is connected to the trigger drive column line; and N is an integer greater than or equal to 4.

2. The three-phase ac voltage stabilization device according to claim 1, characterized in that: the three compensation control circuits respectively carry out voltage sampling on the voltage of the three-phase alternating current power supply and output a three-phase trigger control signal, a three-phase non-trigger area control signal and a three-phase trigger gating control value judgment signal.

3. The three-phase ac voltage stabilizing apparatus according to claim 2, wherein: the compensation control circuit in each phase also comprises an error detection judging circuit; the delay protection circuit outputs a non-trigger area control signal and a delayed trigger gating control value; the delayed trigger gating control value is also sent to an error detection judging circuit; the error detection judging circuit judges whether the input trigger gating control value is effective or not and outputs a trigger gating control value judging signal.

4. A three-phase ac voltage stabilizing apparatus according to claim 3, wherein: the basis of judging whether the input trigger gating control value is effective or not by the error detection judging circuit in each phase is that the trigger gating control value is effective when only one bit is effective in M-bit binary values of the trigger gating control value; otherwise, the trigger gating control value is invalid.

5. The three-phase ac voltage stabilization device according to claim 4, wherein: the configuration method of the configuration switch in the configuration branch in each phase is that M of M trigger control row lines are selected as trigger gating control row lines; m triggering gating control row lines correspond to M bit triggering gating control values one by one, and one triggering gating control value correspondingly enables one triggering gating control row line to be effective; when each trigger gating control row line signal is effective, the trigger gating control row line signal corresponds to the on-off combination state of a thyristor in one thyristor switch group, the trigger driving row line signal of the trigger driving row line corresponding to the thyristor to be conducted in the on-off combination state is effective, in the configuration branches of the trigger gating control row line and the N trigger driving row lines, the configuration switches in the configuration branches between the trigger gating control row line and the trigger driving row line signal effective are configured to be in an on state, and the configuration switches in other configuration branches are configured to be in an off state.

6. A three-phase AC voltage stabilizing device according to any one of claims 1 to 5, wherein: the control signal for controlling the non-trigger area in each phase outputs a single pulse after the trigger gating control value is changed; the no-trigger area control signal is active during the output of a single pulse and inactive during the non-output of a single pulse.

7. The three-phase ac voltage stabilization device according to claim 6, wherein: in the delay protection circuit in each phase, the change time of the delayed trigger gating control value signal is later than the leading edge time of a single pulse in the non-trigger area control signal after the trigger gating control value is changed and is earlier than the trailing edge time of the single pulse in the non-trigger area control signal after the trigger gating control value is changed.