CN109358684B

CN109358684B - Compensation ac voltage stabilizer

Info

Publication number: CN109358684B
Application number: CN201811355989.2A
Authority: CN
Inventors: 王兵; 凌云; 杨兴果; 刘建华
Original assignee: Hunan University of Technology
Current assignee: Ma Genying
Priority date: 2018-11-15
Filing date: 2018-11-15
Publication date: 2020-09-04
Anticipated expiration: 2038-11-15
Also published as: CN109358684A

Abstract

A compensation type alternating current voltage stabilizer comprises a compensation type main circuit, a sampling comparison unit, a coding unit, a delay protection unit, an interlocking control unit, a trigger unit and an error detection control unit, wherein the compensation type main circuit is composed of a compensation transformer bank, a thyristor bridge and a relay protection switch. The coding unit codes the voltage grade comparison value output by the sampling comparison unit into a voltage grade coding value, the delay protection unit outputs the delayed voltage grade coding value and the control signal of the non-trigger area to the interlocking control unit, and the interlocking control unit outputs the trigger control signal to control the on-off of the thyristor in the thyristor bridge of the main circuit; when the interlocking control is realized, the error detection control unit also carries out open circuit protection on the thyristor bridge by judging whether a logic error occurs in the coding unit or the interlocking control unit, so that the protection strength of the compensation type alternating current voltage stabilizer for the abnormity of the working process is effectively enhanced, and the work of the compensation type alternating current voltage stabilizer is more stable and reliable.

Description

Compensation ac voltage stabilizer

Technical Field

The invention relates to the technical field of power supplies, in particular to a compensation type alternating current voltage stabilizer.

Background

The existing compensation type AC voltage stabilizer has the advantages of wide voltage stabilizing range, almost no distortion of waveform, high efficiency of the whole machine and strong load adaptability. The principle is that switching of different winding coils of a primary winding on a compensation transformer is automatically controlled according to the high-low condition of input voltage, bidirectional multi-gear voltage compensation is provided by utilizing the transformation ratio relation of a primary side working winding and a secondary winding or by adjusting the voltage applied to the primary winding, and therefore the purpose of voltage regulation and stabilization is achieved.

The existing compensation type alternating current voltage stabilizer has the following defects: when the motor is adopted to control the carbon brush to move to change the application of different voltages to the excitation coil of the compensation transformer, the carbon brush is easy to wear and often fails. Switching different winding coils of a primary winding on a compensation transformer by adopting an electronic switch switching mode, or when voltage applied to the primary winding is adjusted, the delayed turn-off of the electronic switch is easy to cause a power supply short-circuit fault; when the electronic switch is controlled to be switched by adopting a program mode of a singlechip, a PLC and the like, the problems of program runaway, dead halt and the like can also cause the failure of the voltage stabilizer or cause the short-circuit fault of a power supply due to the error of control logic.

Disclosure of Invention

In order to solve the problems of the existing compensation type alternating current voltage stabilizer, the invention provides a compensation type alternating current voltage stabilizer which comprises a compensation type main circuit, a sampling comparison unit, a coding unit, a delay protection unit, an interlocking control unit, a trigger unit and an error detection control unit.

The compensation type main circuit consists of a compensation transformer bank, a thyristor bridge and a relay protection switch; the on-off combination of the thyristors in the thyristor bridge controls the voltage and polarity combination of the excitation coil of each compensation transformer in the compensation transformer bank to realize different compensation working states. The sampling comparison unit samples the voltage of the alternating current power supply, outputs a voltage grade comparison value to the coding unit, and the coding unit outputs a voltage grade coding value; the delay protection unit inputs a voltage grade coding value and outputs a delayed voltage grade coding value and a non-trigger area control signal; the interlocking control unit inputs the delayed voltage grade code value and the control signal of the non-trigger area and outputs a trigger control signal; the trigger unit controls the on-off of a thyristor in a thyristor bridge of the main circuit according to an input trigger control signal; the error detection control unit judges whether the input trigger control signal is wrong or not to start or stop the open-circuit protection of the thyristor bridge. The voltage grade comparison value is an M-bit binary value; and M is greater than or equal to 1.

When the alternating-current power supply voltage fluctuation causes the voltage grade code value to change, so that the on-off combination state of the thyristors in the thyristor bridge needs to be changed, maintaining a non-trigger area time between 2 different on-off combination states of the thyristors in the thyristor bridge, and turning off all the thyristors in the thyristor bridge; maintaining the time of the non-trigger area is realized by a control signal of the non-trigger area, and controlling the control signal of the non-trigger area to output a single pulse after the voltage level code value is changed; the no-trigger area control signal is active during the output of a single pulse and inactive during the non-output of a single pulse. In the time delay protection unit, the delayed voltage level code value signal change time is later than the leading edge time of a single pulse output in the non-trigger area control signal after the voltage level code value is changed; in the time delay protection unit, the change time of the delayed voltage level code value signal is earlier than the back edge time of a single pulse output in the non-trigger area control signal after the voltage level code value is changed. Further, after the voltage level code value is changed, the width time of the single pulse in the non-trigger area control signal is selected from 10ms to 30 ms.

When the control signal of the non-trigger area input by the interlocking control unit is invalid and the input voltage level code value is an effective code value, outputting an effective trigger control signal corresponding to the effective code value to perform compensation control on the alternating-current power supply voltage; and when the control signal of the non-trigger area input by the interlocking control unit is invalid and the input voltage level code value is not a valid code value, outputting an invalid trigger control signal.

Dividing the voltage in the alternating current power supply voltage fluctuation interval range into M +1 voltage grade intervals for compensation control; controlling and selecting 0 or 1 or a plurality of compensation transformers to perform voltage compensation by the on-off combination state of the thyristors in the thyristor bridge, so as to realize the voltage compensation state corresponding to the voltage grade interval; the voltage level code values have M +1 effective code values which are in one-to-one correspondence with the M +1 voltage level intervals, and the corresponding effective trigger control signals have M +1 groups, so that the control of M +1 voltage compensation states is realized. Each voltage class interval of the alternating current power supply voltage corresponds to a voltage compensation state.

When the control signal of the non-trigger area input by the interlocking control unit is effective, the interlocking control unit outputs 1 group of effective trigger control signals for turning off all thyristors in the thyristor bridge, and the switching control between the voltage compensation states is carried out. The effective trigger control signals output by the interlocking control unit are M +2 groups in total, and comprise M +1 groups of effective trigger control signals corresponding to M +1 effective coding values and 1 group of effective trigger control signals for turning off all thyristors in the thyristor bridge.

The error detection control unit judges whether the input trigger control signal is wrong according to the principle that the trigger control signal is correct when the input trigger control signal is 1 group in the M +2 group effective trigger control signals, otherwise, the trigger control signal is wrong.

And when the error detection control unit judges that the input trigger control signal is wrong, the thyristor bridge is controlled to be in an open-circuit protection state by controlling to disconnect all upper bridge arms of the thyristor bridge to carry out open-circuit protection on the thyristor bridge or controlling to disconnect all lower bridge arms of the thyristor bridge to carry out open-circuit protection on the thyristor bridge. When the thyristor bridge is in an open-circuit protection state, the error detection control unit automatically stops the open-circuit protection state of the thyristor bridge when judging that the input trigger control signal is recovered to a correct signal.

When the error detection control unit judges that the input trigger control signal has no error, the control signal of the non-trigger area input by the interlocking control unit is invalid and the input voltage level code value is an effective code value, the compensation type alternating current voltage stabilizer is in1 of M +1 voltage compensation states. When the error detection control unit judges that the input trigger control signal has no error and the control signal of the non-trigger area input by the interlocking control unit is effective, the compensation type alternating current voltage stabilizer is in a switching state between different voltage compensation states.

The trigger unit converts the trigger control signal into a thyristor trigger signal to realize on-off control of a thyristor in a thyristor bridge of the compensation type main circuit. When the error detection control unit judges that the input trigger control signal is in error, the working power supply of the trigger unit is cut off, and the trigger unit stops sending out thyristor trigger pulses; when the error detection control unit judges that the input trigger control signal has no error, the working power supply of the trigger unit is switched on, and the trigger unit sends out corresponding thyristor trigger pulse according to the input trigger control signal to control the on-off of the thyristor in the thyristor bridge.

The thyristors in the thyristor bridge are bidirectional thyristors or thyristor alternating current switches formed by connecting 2 unidirectional thyristors in reverse parallel.

The delay protection unit consists of a delay detection module and a non-trigger area control signal generation module; the delay detection module comprises K identical delay detection circuits, each delay detection circuit delays an input signal to obtain a delayed output signal, and simultaneously performs edge detection on the input signal to output an edge detection signal; the K delay detection circuits respectively delay the K-bit voltage level code value to obtain a delayed K-bit voltage level code value, and perform edge detection on the K-bit voltage level code value to obtain K edge detection signals; the non-trigger area control signal generation module converts the input K edge detection signals into non-trigger area control signals and outputs the non-trigger area control signals.

Each of the K identical delay detection circuits comprises a resistor RY3, a capacitor CY3, an inverter FY5, an inverter FY6, a nand gate FY7, an or gate FY8, and a nand gate FY 9; the input end of the inverter FY5 is connected to the input signal end; one end of the resistor RY3 is connected to the output end of the inverter FY5, and the other end of the resistor RY3 is respectively connected to one end of the capacitor CY3, one input end of the NAND gate FY7, one input end of the OR gate FY8 and the input end of the inverter FY 6; the other end of the capacitor CY3 is connected to the ground, the other input end of the NAND gate FY7 is connected to the input signal end, and the other input end of the OR gate FY8 is connected to the input signal end; 2 input ends of the NAND gate FY9 are respectively connected to the output end of the NAND gate FY7 and the output end of the OR gate FY 8; the output end of the inverter FY6 is a delayed output signal end; the output end of the NAND gate FY9 is an edge detection signal output end.

Or, in the K identical delay detection circuits, each delay detection circuit includes a resistor RY0, a resistor RY1, a resistor RY2, a capacitor CY0, a capacitor CY1, a capacitor CY2, a diode DY1, a diode DY2, a driving gate FY0, an inverter FY1, an inverter FY2, an inverter FY3, and a nand gate FY 4; the resistor RY0 is connected between the input signal end and the input end of the driving gate FY0, the capacitor CY0 is connected between the input end of the driving gate FY0 and the ground end, and the output end of the driving gate FY0 is a delayed output signal end; the capacitor CY1 is connected between the input signal end and the input end of the inverter FY1, the resistor RY1 is connected between the input end of the inverter FY1 and the ground end, the cathode of the diode DY1 is connected to the input end of the inverter FY1, and the anode of the diode DY1 is connected to the ground end; the input of the inverter FY2 is connected to the input signal terminal; the capacitor CY2 is connected between the output end of the inverter FY2 and the input end of the inverter FY3, the resistor RY2 is connected between the input end of the inverter FY3 and the ground end, the cathode of the diode DY2 is connected to the input end of the inverter FY3, and the anode of the diode DY2 is connected to the ground end; 2 input ends of the NAND gate FY4 are respectively connected to the output end of the inverter FY1 and the output end of the inverter FY 3; the output of the nand gate FY4 is an edge detection signal output.

Or, in the K identical delay detection circuits, each delay detection circuit includes a resistor RY1, a resistor RY2, a capacitor CY1, a capacitor CY2, a diode DY1, a diode DY2, an inverter FY1, an inverter FY2, an inverter FY3, an inverter FY11, an inverter FY12, an inverter FY13, an inverter FY14, and a nand gate FY 4; the input end of the inverter FY11 is connected to an input signal end, the input end of the inverter FY12 is connected to the output end of the inverter FY11, the input end of the inverter FY13 is connected to the output end of the inverter FY12, the input end of the inverter FY14 is connected to the output end of the inverter FY13, and the output end of the inverter FY14 is a delayed output signal end; the capacitor CY1 is connected between the input signal end and the input end of the inverter FY1, the resistor RY1 is connected between the input end of the inverter FY1 and the ground end, the cathode of the diode DY1 is connected to the input end of the inverter FY1, and the anode of the diode DY1 is connected to the ground end; the input of the inverter FY2 is connected to the input signal terminal; the capacitor CY2 is connected between the output end of the inverter FY2 and the input end of the inverter FY3, the resistor RY2 is connected between the input end of the inverter FY3 and the ground end, the cathode of the diode DY2 is connected to the input end of the inverter FY3, and the anode of the diode DY2 is connected to the ground end; 2 input ends of the NAND gate FY4 are respectively connected to the output end of the inverter FY1 and the output end of the inverter FY 3; the output end of the NAND gate FY4 is an edge detection signal output end.

The no-trigger area control signal generation module is an OR gate FY10 with K input signal terminals; k input signal ends of the OR gate FY10 are respectively connected to edge detection signal output ends of the K delay detection circuits; the output of or gate FY10 outputs a no trigger area control signal.

The invention has the beneficial effects that: the compensation type alternating current voltage stabilizer adopting the compensation transformer bank and the thyristor bridge to perform voltage compensation guarantees that the upper thyristors and the lower thyristors of the same bridge arm cannot be conducted simultaneously, namely, the interlocking control of the upper thyristors and the lower thyristors of the same bridge arm is realized, and simultaneously, the logic errors of the possible coding units and the invalid coding values are output, and the conditions that the logic errors of the interlocking control units and the invalid trigger control signals are output stop sending the trigger pulses and perform open-circuit protection of the thyristor bridge, so that the protection strength of the compensation type alternating current voltage stabilizer against the abnormal working process is effectively enhanced; when the thyristor bridge is in the open-circuit protection state, if the compensation type alternating current voltage stabilizer enters the normal logic control state again, the open-circuit protection state of the thyristor bridge can be automatically stopped and the thyristor bridge is enabled to be in the compensation working state again; the on-off switching of the thyristor is controlled without adopting a program mode of a singlechip, a PLC and the like, so that the faults of the voltage stabilizer caused by the problems of program runaway, dead halt and the like are avoided. The compensation type alternating current voltage stabilizer has the advantages that the compensation type alternating current voltage stabilizer can work more stably and reliably.

Drawings

FIG. 1 is a block diagram of a system configuration of a compensated AC voltage regulator;

FIG. 2 shows an embodiment 1 of a compensated main circuit;

FIG. 3 illustrates an embodiment of a compensated main circuit 2;

FIG. 4 shows a sample comparison unit of example 1;

FIG. 5 shows a sample comparison unit of example 2;

FIG. 6 shows an embodiment of a coding unit, wherein FIG. 6(a) shows an embodiment 1 of a coding unit, and FIG. 6(b) shows an embodiment 2 of a coding unit;

FIG. 7 is a block diagram of an embodiment of a delay protection unit;

fig. 8 is a circuit embodiment 1 of a delay detection circuit for the voltage level code value signal Y10 in the delay detection module;

fig. 9 is a circuit embodiment 2 of the delay detection circuit for the voltage level code value signal Y10 in the delay detection module;

fig. 10 is a circuit embodiment 3 of the delay detection circuit for the voltage level code value signal Y10 in the delay detection module;

FIG. 11 is a block diagram of an embodiment of a no trigger area control signal generation module;

FIG. 12 is a diagram illustrating a partial correlation waveform in the delay protection unit;

fig. 13 is an embodiment of an interlock control unit, wherein fig. 13(a) is an interlock control unit embodiment 1, and fig. 13(b) is an interlock control unit embodiment 2;

FIG. 14 is an embodiment of a trigger circuit for triggering the triac SR1 in the trigger unit;

FIG. 15 is an error detection control unit embodiment.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

Fig. 1 is a block diagram of a system of a compensated ac voltage regulator, in which a sampling and comparing unit samples voltage of an ac power supply and outputs a voltage level comparison value P1 to an encoding unit, and the encoding unit outputs a voltage level encoding value P2; the delay protection unit inputs a voltage level code value P2 and outputs a delayed voltage level code value P3 and a non-trigger area control signal P4; the interlock control unit inputs the delayed voltage level code value P3 and the non-trigger area control signal P4 and outputs a trigger control signal P5; the trigger unit sends a trigger signal P6 to the compensation type main circuit according to an input trigger control signal P5 to control the on-off of a thyristor in a thyristor bridge; the error detection control unit determines whether the input trigger control signal P5 is an effective trigger control signal, and sends a protection control signal to the compensation type main circuit according to the determination result to perform open-circuit protection on the thyristor bridge.

Fig. 2 shows a compensation type main circuit embodiment 1, in which a compensation transformer bank is composed of compensation transformers TB1 and TB2, a thyristor bridge is composed of 6 bidirectional thyristors SR1-SR6, a fuse FU1, normally open switches KA-1, KA-2 and KA-3 of a relay, and normally closed switches KA-5 and KA-6 of the relay constitute a relay protection circuit.

In fig. 2, the compensation coils of the compensation transformers TB1 and TB2 are both connected in series to the phase line, the input end of the phase line is LA1, and the output end is LA 2. The voltage on the TB1, TB2 excitation coils is controlled by a thyristor bridge. The 1 thyristor bridge arm circuit comprises an upper thyristor and a lower thyristor, wherein the upper thyristor and the lower thyristor are 2 thyristors. One ends of the excitation coils TB1 and TB2 are connected in parallel and then connected to a thyristor bridge arm circuit formed by SR1 and SR2, and the other ends of the excitation coils TB1 and TB2 are respectively connected to a thyristor bridge arm circuit formed by SR3 and SR4, and SR5 and SR 6. If the compensation voltages of TB1 and TB2 are different, and no compensation method for mutual cancellation of the compensation voltages is considered, the compensation transformer bank has 6 voltage compensation states at most, namely, forward TB1, forward TB2, forward TB1+ TB2, reverse TB1, reverse TB2 and reverse TB1+ TB2, and the ac power supply voltage input by phase line input terminal LA1 can be divided into 7 voltage intervals for compensation control at most when a voltage compensation state of 0 is applied when the input voltage is within a normal range. In fig. 2, N is a zero line, and G11, G12 to G61, and G62 are trigger signal input ends of the triacs SR1 to SR6, respectively.

Fig. 3 shows a compensation type main circuit embodiment 2, in which a compensation transformer bank is composed of compensation transformers TB1, TB2, TB3, a thyristor bridge is composed of 8 bidirectional thyristors SR1-SR8, a fuse FU1, normally open switches KA-1, KA-2, KA-3, KA-4 of relays, and normally closed switches KA-4, KA-5, KA-6 of relays constitute a relay protection circuit.

In fig. 3, the compensation coils of the compensation transformers TB1, TB2, and TB3 are all connected in series to the phase line, where the input end of the phase line is LA1 and the output end is LA 2. The voltage on the TB1, TB2, TB3 excitation coils is controlled by a thyristor bridge. One ends of TB1, TB2 and TB3 excitation coils are connected in parallel and then connected to a thyristor bridge arm circuit formed by SR1 and SR2, and the other ends of TB1, TB2 and TB3 excitation coils are respectively connected to a thyristor bridge arm circuit formed by SR3 and SR4, SR5 and SR6, and SR7 and SR 8. If the compensation voltages of TB1, TB2, and TB3 are different, and no compensation mode in which the compensation voltages cancel each other is considered, the compensation transformer bank has 7 voltage compensation states in the forward direction, 7 voltage compensation states in the reverse direction, and 14 voltage compensation states in the reverse direction, and a0 voltage compensation state when the input voltage is within the normal range is applied, and the alternating-current power supply voltage input at the phase line input end LA1 can be divided into 15 voltage intervals at most for compensation control. In fig. 3, N is a zero line, and G11, G12 to G81, and G82 are trigger signal input terminals of the triacs SR1 to SR8, respectively.

Each of the triacs of fig. 2 and 3 may be replaced by 2 antiparallel triacs. In fig. 2 and 3, the relay normally open switch and the relay normally closed switch form a relay protection switch.

The sampling comparison unit obtains an alternating current power supply voltage sampling value by performing voltage sampling on alternating current power supply voltage through an alternating current power supply voltage sampling circuit, compares the alternating current power supply voltage sampling value through a comparison circuit composed of M comparators, and outputs a voltage grade comparison value composed of M binary digits.

Fig. 4 shows an embodiment 1 of a sampling comparator, and compensation control is performed on the embodiment 1 of the compensation type main circuit. In the ac power supply voltage sampling circuit shown in fig. 4, ac power supply voltages input from the phase line L1 and the zero line N are stepped down by the transformer TV, rectified by the rectifier bridge composed of the diodes DV1-DV4, filtered by the capacitor CV1, and divided by the resistors RV1 and RV2, so as to obtain an ac power supply voltage sampling value U1 in direct proportion to the effective value of the input ac power supply voltage.

In the comparison circuit of fig. 4, resistors RF1-RF7 form a voltage divider circuit, and 6 threshold voltages UF1-UF6 are obtained after voltage division of a power supply + VCC 1. The 6 comparators FA1-FA6 realize the comparison between the AC power supply voltage sampling value U1 and 6 threshold voltages UF1-UF6, the output voltage grade comparison value P1 is composed of the outputs J1-J6 of the 6 comparators FA1-FA6, and the voltage in the fluctuation range of the AC power supply voltage is divided into 7 voltage grade ranges. The operational amplifier FA0 forms a follower, and an alternating current power supply voltage sampling value U1 is driven by the follower FA0 and then is simultaneously sent to the non-inverting input end of the comparator FA1-FA 6; the 6 threshold voltages UF1-UF6 are respectively supplied to the inverting inputs of the comparators FA1-FA 6. In fig. 4, the power supply + VCC1 may be replaced by another precision power supply, and the voltage divider circuit divides the precision power supply to make the threshold voltage more accurate. The operational amplifier FA0 and the comparators FA1-FA6 are preferably rail-to-rail operational amplifiers powered by a single power supply + VCC1, such as LMV324, LMV358, AD8517, TLV2432, TLV2434, and the like.

The fluctuation range of the input alternating current power supply voltage is set as 220V +/-10%, and the input alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. By adopting the sampling comparison unit embodiment 1 in fig. 4, the voltage input between 242V and 198V can be divided into 7 voltage class intervals with the interval voltage size of 6.4V, wherein the voltage of 3 voltage class intervals is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of the 3 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 6.4V is not more than 220V +/-1.5 percent, and the requirement that the output is controlled within 220V +/-2 percent is met; the fluctuation interval of the alternating current power supply voltage corresponding to 7 voltage class intervals of 6.4V is 242.4V to 197.6V, and the actual fluctuation range is covered. The compensation is carried out by adopting the compensation type main circuit embodiment 1 in the figure 2, the compensation voltage of TB1 is low, and the compensation voltage of TB2 is high; the compensation voltage of the TB2 is 2 times of the compensation voltage of the TB1, and when the voltage on the exciting coil is 220V, the TB1 compensation voltage is 6.4V, and the TB2 compensation voltage is 12.8V. The selection of the threshold voltages UF1-UF6 is related to the ratio between the sampled values of the AC supply voltage U1 and the AC supply voltage; if the ratio between the ac power supply voltage sampling value U1 and the ac power supply voltage is 0.01, that is, the ac power supply voltage sampling value U1 is 1% of the effective value of the ac power supply voltage, when the ac power supply voltage is divided into 7 voltage class intervals with interval voltage of 6.4V, 6 threshold voltages UF1-UF6 are 2.36V, 2.296V, 2.232V, 2.168V, 2.104V, and 2.04V, respectively, and are 6 intermediate separation voltage values of the voltage sampling values corresponding to the ac power supply voltage values separating the 7 voltage class intervals; the sizes of the resistors RF1-RF7 can be calculated according to the sizes of the 6 threshold voltages UF1-UF6 and + VCC 1.

In fig. 4, the resistor R11, the resistor R12, and the comparator FA1 form a schmitt comparator, and the resistances of the resistor R11 and the resistor R12 are reasonably selected, so that the size of the hysteresis voltage interval can be controlled, and frequent switching of electronic switches in a thyristor bridge caused by fluctuation of the ac power supply voltage near the comparison critical point of the comparator is avoided. The resistor R21, the resistor R22 to the resistor R61 and the resistor R62 have the same functions and respectively form a Schmitt comparator with the comparator FA2 to the comparator FA 6. Since the compensation mode of the compensation type main circuit embodiment 1 automatically has the schmitt characteristic, the comparator FA1 to the comparator FA6 may not constitute a schmitt comparator, and in this case, the resistor R12 to the resistor R62 do not need to be used and connected, and the resistor R11 to the resistor R61 remain or are respectively connected in a short circuit.

Embodiment 1 of fig. 4 may be performed for the compensated main circuit embodiment 2, and in this case, it is necessary to divide the voltage in the ac power supply voltage fluctuation interval range into more voltage class intervals. For example, when the voltage of the ac power source voltage fluctuation interval range is divided into 15 voltage class intervals, the circuit of fig. 4 should be extended to 14 comparators, and compared with 14 threshold voltages of different sizes, the output voltage class comparison value P1 will be composed of 14 bits, e.g., J1-J14.

Fig. 5 shows an embodiment 2 of a sampling comparison unit, which is used for performing compensation control on the embodiment 2 of the compensation type main circuit. In fig. 5, FD1 is a true effective value detection device LTC1966, a transformer TV1, a capacitor CV2, and a capacitor CV3 constitute an ac power supply voltage sampling circuit, and the effective values of the ac power supply voltage input from a phase line L1 and a zero line N are measured to obtain a sampled ac power supply voltage U2. UIN1 and UIN2 of LTC1966 are alternating voltage differential input terminals, USS is a negative power input terminal capable of being grounded, UDD is a positive power input terminal, GND is a ground terminal, EN is a low-level effective enable control input terminal, UOUT is a voltage output terminal, and COM is an output voltage return terminal.

In fig. 5, FD2, resistor RD1, and resistor RD2 form a comparison circuit; the FD2 is a 10-stage comparison display driver LM3914, which contains an internal divider circuit with 10 1k Ω precision resistors connected in series, forming 10 comparison threshold voltages and connected to the positive input ends of the 10 comparators; pin 6 is the high end of the internal divider circuit and is connected to the internal standard power supply output VREF of pin 7 through a resistor RD 1; pin 4 is the low end of the internal voltage divider circuit and is connected to the ground through a resistor RD 2; pin 8 is the low end of the internal standard power supply and is connected to the ground; pin 2 is a negative power supply end and is connected to the ground; pin 3 is a positive power supply terminal and is connected to a power supply + VCC 1; pin 5 is a signal input end, is connected to an alternating current power supply voltage sampling value U2 and is internally connected to the negative input ends of 10 comparators; signals L1-L9 output by pins 10-18 are the output results of the comparator compared with the highest 9 comparison threshold voltages, wherein the comparison voltage of L1 is the highest, and is sequentially reduced, and the comparison voltage of L9 is the lowest; L1-L9 are all effective in low level, the priority of L1 is the highest, and L1-L9 form a voltage level comparison value P1; the 9-pin mode control terminal is connected to power supply + VCC1, enabling striped (continuous) output of L1 through L9. In fig. 5, the high side of the inner divider circuit can also be connected to other power supplies, such as power supply + VCC1, via resistor RD 1.

In fig. 5, 9 comparators out of 10 comparators in LM3914 are used to compare the input ac power supply voltage into 10 voltage class intervals. The input alternating current power supply voltage fluctuation range is set to be 220V + 10% to 220V-20%, and the output is required to be stabilized within the range of 220V +/-2%. By adopting the sampling comparison unit embodiment 2 of fig. 5, the voltage input between 242V and 176V is divided into 10 voltage class intervals with the interval voltage size of 7V, wherein the voltage of 3 voltage class intervals is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of the 6 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 7V is 220V +/-1.6%, and the requirement that the output is controlled within 220V +/-2% is met; the fluctuation interval of the alternating current power supply voltage corresponding to 10 voltage class intervals of 7V is 244.5V to 174.5V, and the actual fluctuation range is covered. The compensation is carried out by adopting the compensation type main circuit embodiment 2 in FIG. 3, the compensation voltage TB1 is the lowest, and the compensation voltage TB3 is the highest; the compensation voltage of the TB2 is 2 times of the compensation voltage of the TB1, the compensation voltage of the TB3 is 2 times of the compensation voltage of the TB2, and then when the voltage on the exciting coil is alternating current 220V, the TB1 compensation voltage is 7V, the TB2 compensation voltage is 14V, and the TB3 compensation voltage is 28V. The selection of the threshold voltage is related to the ratio between the sampled value of the ac supply voltage U2 and the ac supply voltage; if the ratio of the ac power supply voltage sampling value U2 to the ac power supply voltage is 0.005, that is, the ac power supply voltage sampling value U2 is 0.5% of the effective value of the ac power supply voltage, when the ac power supply voltage is divided into 10 voltage class sections with a voltage class of 7V, 9 threshold voltages are 1.1875V, 1.1525V, 1.1175V, 1.0825V, 1.0475V, 1.0125V, 0.9775V, 0.9425V, and 0.9075V, respectively, and are 9 intermediate divided voltage values of the voltage sampling values corresponding to the ac power supply voltage values divided into 10 voltage class sections; the voltage at the high end of the inner voltage divider circuit is connected to the positive input end of the highest comparator, so that the voltage at the 6 pin is 1.1875V. From the 9 threshold voltages and the magnitude of the internal standard power supply output VREF (1.2V or 1.25V), and the magnitude of the internal 10 precision resistors, the magnitudes of the resistors RD1, RD2 can be calculated. If the precision of voltage compensation is required to be improved or the fluctuation range of the input voltage is required to be larger, the sampling comparison unit in embodiment 2 of fig. 5 is required to divide the voltage class into more voltage class intervals, for example, when the voltage in the fluctuation range of the ac power supply voltage needs to be divided into 15 voltage class intervals, 2 LM3914 slices can be adopted for implementation, and the inner voltage divider circuits in the 2 LM3914 slices are connected in series to form 20 comparison threshold voltages, so as to form a 20-level comparison circuit; of which 14 stages of comparison outputs are selected, the output voltage level comparison value P1 will consist of 14 bits, e.g., L1-L14.

The embodiment 2 of the sampling comparison unit in fig. 5 can also perform compensation control on the compensated main circuit embodiment 1, and at this time, only the voltage within the fluctuation interval range of the input ac power voltage needs to be divided into intervals of no more than 7 voltage classes, that is, the comparison output of no more than 6 classes is selected.

In

embodiments

1 and 2 of the sampling comparison unit in fig. 4 and 5, when the input ac power voltage is higher than the range of the maximum voltage class interval, the output voltage class comparison value is equal to the voltage class comparison value of the maximum voltage class interval and is compensated accordingly; when the input alternating current power supply voltage is lower than the range of the minimum voltage grade interval, the output voltage grade comparison value is equal to the voltage grade comparison value of the minimum voltage grade interval and corresponding compensation is carried out.

In addition to the sampling comparison unit embodiment of fig. 4 or 5, when compensation control is performed on the compensation type main circuit embodiment 1 or embodiment 2, another ac power supply voltage sampling circuit and comparison circuit may be selected to implement a desired function. The ac power voltage sampling value U1 output by the ac power voltage sampling circuit of fig. 4 can be sent to the comparison circuit of fig. 5 for comparison, and output a voltage level comparison value; the sampled value U2 of the ac power voltage output by the ac power voltage sampling circuit of fig. 5 can be sent to the comparison circuit of fig. 4 for comparison, and the comparison value of the voltage level is output.

Fig. 6 shows an embodiment of an encoding unit, wherein fig. 6(a) shows an embodiment 1 of an encoding unit, the input of which is a 6-bit voltage level comparison value output by the sampling comparison unit embodiment 1, FD3 selects the integrated encoder 74HC148, the strobe input EI is connected to 0 (low level), 74HC148 is in an encoding active state, and table 1 shows a corresponding function table.

TABLE 1

As can be seen from FIG. 4, when the AC power voltage is in the highest interval, J1-J6 all output high level; when the alternating current power supply voltage is in a second-highest interval, J1 outputs low level, and J2-J6 all output high level; when the alternating current power supply voltage is in the lowest interval, the J1-J6 all output low levels, the comparison value output by the J6 is valid, and the priority of J6 is the highest in coding, and is sequentially reduced to J1 and J1 which are the lowest in priority. Table 1 encodes the voltage level comparison value P1 consisting of J1-J6 corresponding to 7 voltage levels of the ac power supply voltage in the sampling comparison unit embodiment 1 to obtain a voltage level encoded value P2, where P2 consists of Y12, Y11, and Y10; the interval of the alternating current power supply voltage represented by 1 in the 7 voltage levels is the lowest, and is increased in sequence, and the interval of the alternating current power supply voltage represented by 7 is the highest. In Table 1, the values of the 7Y 12, Y11, and Y10 corresponding to the voltage levels 1-7 are valid code values of the voltage level code values.

Fig. 6(b) shows an encoding unit embodiment 2 with the input being the 9-bit voltage level comparison value of the sampling comparison unit embodiment 2, with FD4 selecting the integrated encoder 74HC 147. As can be seen from fig. 5 and the function of LM3914, when the ac power voltage is in the highest range, L1-L9 all output low levels, and the comparison value output by L1 should be valid; when the alternating current power supply voltage is in a second-highest interval, L1 outputs a high level, L2-L9 all output a low level, and the comparison value output by L2 is valid; when the alternating current power supply voltage is in the lowest interval, L1-L9 all output high level; during encoding, the priority of L1 is highest, and is reduced to the priority of L9 and the priority of L9 is lowest. Table 2 shows that the voltage level comparison value P1 composed of L1-L9 corresponding to 10 voltage levels of the ac power voltage in the sampling comparison unit embodiment 2 is encoded to obtain a voltage level code value P2, where P2 is composed of Y13, Y12, Y11, and Y10; the interval of the alternating current power supply voltage represented by 1 in the 10 voltage levels is the lowest, and is increased in sequence, and the interval of the alternating current power supply voltage represented by 10 is the highest. In Table 2, the values of the 10Y 13, Y12, Y11, Y10 corresponding to the voltage levels 1-10 are valid code values of the voltage level code values.

TABLE 2

When the compensation accuracy needs to be improved, more stages of comparison are carried out on the input alternating current power supply voltage, and the number of bits of the voltage level comparison value P1 is increased, the corresponding input number of the encoder is increased, at this time, 2 or more 74HC148, 2 or more 74HC147, a ROM (read only memory) or a gate circuit is adopted to directly form a multi-input encoder circuit, and the function of the encoding unit is realized.

Fig. 7 is a block diagram of an embodiment of a delay protection unit, wherein a delay detection module YC1 respectively delays input voltage level code values Y12, Y11, and Y10 to obtain delayed voltage level code values Y22, Y21, and Y20, and Y22, Y21, and Y20 form P3; the YC1 module simultaneously and respectively carries out edge detection on Y12, Y11 and Y10 to obtain edge detection signals Y32, Y31 and Y30; the no-trigger area control signal generation module YC2 converts the input edge detection signals Y32, Y31, Y30 into the no-trigger area control signal P4 and outputs it. In the block diagram of the embodiment of fig. 7, the voltage level code values input by the delay time detection module YC1 are only 3 bits, such as Y12, Y11, Y10, etc., and K is equal to 3; if K is equal to 4, the voltage level code value input by the delay detection module YC1 is composed of a 4-bit binary value, for example, when Y13, Y12, Y11, and Y10 are included, the voltage level code value after the signal delay is performed to obtain the delay also has 4 bits such as Y23, Y22, Y21, and Y20, the edge detection signal obtained by performing edge detection on Y13, Y12, Y11, and Y10 also has 4 bits such as Y33, Y32, Y31, and Y30, and the edge detection signal input by the non-trigger area control signal generation module YC2 also has 4 bits such as Y33, Y32, Y31, and Y30.

Fig. 8 is a circuit embodiment 1 of the delay detection circuit for the voltage level code value signal Y10 in the delay detection module. The resistor RY0, the capacitor CY0 and the driving gate FY0 realize signal delay of Y10, and a delayed signal Y20 of Y10 is obtained. The resistor RY1, the capacitor CY1, the diode DY1 and the inverter FY1 form a rising edge detection circuit for the input signal Y10, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y10 is output in the output signal YP1 of the inverter FY 1. The resistor RY2, the capacitor CY2, the diode DY2, the inverters FY2 and FY3 constitute a falling edge detection circuit for the input signal Y10, and a single pulse in the form of a negative pulse corresponding to the falling edge of Y10 is output in the output signal YP2 of the inverter FY 3. The nand gate FY4 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y30 output by the nand gate FY4, that is, when the input signal Y10 changes, the nand gate FY4 outputs a single pulse in the form of a positive pulse. In fig. 8, the drive gate FY0, inverter FY1, inverter FY3 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; the drive gate FY0 may consist of 2 inverters with schmitt inputs.

Fig. 9 is a circuit embodiment 2 of the delay detection circuit for the voltage level code value signal Y10 in the delay detection module. The inverter FY5, the resistor RY3 and the capacitor CY3 invert and delay the input signal Y10 to obtain a delayed inverted signal YP0 of Y10; the inverter FY6 inverts YP0 to obtain a delayed Y10 signal Y20. The signal input by the nand gate FY7 is a delayed inverted signal YP0 of Y10 and Y10, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y10 is generated in the output signal YP 1; the or gate FY8 receives the inverted signals YP0 of Y10 and Y10, and the output signal YP2 generates a single pulse in the form of a negative pulse corresponding to the falling edge of Y10. The nand gate FY9 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y30 output by the nand gate FY9, that is, when the input signal Y10 changes, the nand gate FY9 outputs a single pulse in the form of a positive pulse. In fig. 9, inverter FY6, nand gate FY7, or gate FY8 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; nand gate select 74HC132, CD4093, etc.; or gate select 74HC7032 or 2 inverters with schmitt inputs and 1 nand gate to implement the or gate function.

Fig. 10 is a delay detection circuit embodiment 3 of the delay detection module for the voltage level encoded value signal Y10, in which a rising edge detection circuit for the input signal Y10 is composed of the resistor RY1, the capacitor CY1, the diode DY1 and the inverter FY1, and a falling edge detection circuit for the input signal Y10 is composed of the resistor RY2, the capacitor CY2, the diode DY2, the inverter FY2 and the inverter FY3, and a circuit for outputting the edge detection signal Y30 by using the nand gate FY4 is the same as in embodiment 1 of fig. 8. In fig. 10, the signal delay of Y10 is realized by inverters FY11, FY12, FY13, and FY14, and a delayed signal Y20 of Y10 is obtained.

The embodiments 1-3 of fig. 8, 9 and 10 are all delay detection circuits for the signal Y10 in the voltage level code value, and the delay detection circuits for the other signals in the voltage level code value, for example, the delay detection circuits for the input signals Y12 and Y11, and the delay detection circuit for the Y13 in the 4-bit voltage level code value, and the circuit structure and function of the delay detection circuit for the input signal Y10 in the corresponding embodiments are the same. The delay detection circuit may also adopt other circuits meeting the requirements to realize the functions thereof.

The function of the no-trigger area control signal generation module is to output a single pulse in the no-trigger area control signal when any one or more of the input edge detection signals generate a single pulse related to an edge. Fig. 11 shows an embodiment of the no-trigger area control signal generation module, where the or gate FY10 implements the corresponding function, and the input signals of the or gate FY10 are edge detection signals Y32, Y31, and Y30, and the output signal is a no-trigger area control signal P4. In the embodiment of fig. 11, the single pulse not triggering the output of the zone control signal is a positive pulse, i.e. the high level of the zone control signal is not activated; when the or gate FY10 is replaced by a nor gate, the single pulse that does not trigger the output of the zone control signal is a negative pulse, and the low level of the zone control signal is active. If the single pulse related to the edge generated in the input edge detection signals Y32, Y31, and Y30 is negative, the or gate in fig. 11 should be changed to a nand gate or an and gate to implement an or logic function under negative logic. If the input edge detection signal has 4 bits, the or gate in fig. 11, or other gates for implementing the function of the no-trigger area control signal generation module, such as nor gate, nand gate, and gate, is also a corresponding 4-input gate circuit.

Fig. 12 is a schematic diagram of a partial correlation waveform in the delay protection unit. In fig. 12, Y10 among the voltage level code values undergoes a rising edge change and a falling edge change, respectively, and Y20 is the voltage level code value of Y10 delayed by T1 time; in embodiment 1 of the delay detection circuit in fig. 8, T1 is determined by the magnitude of the product of the resistor RY0 and the capacitor CY0 (i.e., the magnitude of the time constant); in embodiment 2 of the delay detection circuit of fig. 9, T1 is determined by the product of the resistor RY3 and the capacitor CY 3; in the delay detection circuit embodiment 3 of fig. 10, T1 is determined by the gate delay time of the inverters FY11, FY12, FY13, and FY14 themselves. In fig. 12, the negative pulse width of the signal YP1 due to the rising edge of Y10 is T2; in the delay detection circuit embodiment 1 of fig. 8 and the delay detection circuit embodiment 3 of fig. 10, T2 is determined by the magnitude of the product of the resistor RY1 and the capacitor CY 1; in embodiment 2 of the delay detection circuit in fig. 9, T2 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 12, the negative pulse width generated by the falling edge of Y10 in the signal YP2 is T3; in the delay detection circuit embodiment 1 of fig. 8 and the delay detection circuit embodiment 3 of fig. 10, T3 is determined by the magnitude of the product of the resistor RY2 and the capacitor CY 2; in embodiment 2 of the delay detection circuit in fig. 9, T3 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 12, 2 positive pulses in the edge detection signal Y30 correspond to a negative pulse due to a rising edge of Y10 in the signal YP1 and a negative pulse due to a falling edge of Y10 in the signal YP2, respectively. When the rising edge of Y10 in the voltage level code of fig. 12 changes, Y11 and Y12 in the voltage level code do not change, and the corresponding edge detection signals Y31 and Y32 do not generate positive pulses; when Y10 changes at the falling edge, Y11 and Y12 in the voltage level code value change at the same time, positive pulses related to changes in Y11 and Y12 are generated in the corresponding edge detection signals Y31 and Y32, respectively. According to the logic function of the non-trigger area control signal generation module, the width of the single pulse output by the non-trigger area control signal generation module is the same as the widest pulse width of the input pulses which jointly generate the single pulse in the input edge detection signals. In FIG. 12, the 1 st positive pulse in the non-trigger area control signal P4 is generated by the 1 st negative pulse in the edge detection signal Y30, and the widths of the two pulses are identical; the 2 nd positive pulse in the no-trigger-zone control signal P4 is generated by the influence of the 2 nd negative pulse in the edge detection signal Y30 and the negative pulses in the edge detection signals Y31 and Y32, and has the same width as the widest negative pulse among the 3 negative pulses generating the positive pulse; as can be seen from fig. 12, the negative pulse width in Y32 is widest, and the 2 nd positive pulse width in P4 is the same as the negative pulse width in Y32. The width difference is caused by the difference between the resistance and capacitance values of T2 and T3 determined in different delay detection circuits.

In the embodiment 1 of the delay detection circuit in the delay protection unit of fig. 8, the delay time for the voltage level code value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY1 and FY4 and FY10 in fig. 11, or the sum of the delay times of the gates FY3 and FY4 and FY10 in fig. 11; the selection range of the signal delay time T1 of the voltage level code value determined by the product of the resistor RY0 and the capacitor CY0 is ms order of magnitude, obviously, is greater than the delay time of the voltage level code value changing to the leading edge of the single pulse of the corresponding non-trigger area control signal, that is, the time of the delay change of the level code value signal is later than the leading edge time of the single pulse output after the voltage level code value changes. Strictly speaking, T1 actually includes the sum of the delay time caused by resistor RY0 and capacitor CY0, and the delay time of gate FY 0. In embodiment 1 of fig. 8, when selecting the parameters, the value of T2 and the value of T3 are both made to be greater than the value of T1, so that the timing at which the gradation code value signal changes with a delay meets the requirement that the timing of the trailing edge of the output single pulse be earlier than the timing at which the voltage gradation code value changes.

In the embodiment 2 of the delay detection circuit in the delay protection unit of fig. 9, the delay time for the voltage level code value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY7 and FY9 and FY10 in fig. 11, or the sum of the delay times of the gates FY8 and FY9 and FY10 in fig. 11; t1 is a value of ms magnitude, and it is obvious that the signal delay time T1 of the voltage level code value determined by the product of the resistor RY3 and the capacitor CY3 is longer than the delay time of the voltage level code value changing to the leading edge of the corresponding single pulse of the no-trigger-zone control signal, i.e. the time of the delay change of the voltage level code value signal is later than the time of the leading edge of the single pulse output after the voltage level code value changes. In the embodiment 2 of the delay detection circuit in fig. 9, both the time when the voltage level code value signal changes in delay and the time when the trailing edge of the output single pulse after the voltage level code value changes are affected by the change of the signal YP 0; the time when the voltage level code value signal delay changes is the delay of the gate circuit FY6 after the signal YP0 changes; the trailing edge time of the single pulse output after the voltage level code value is changed is the sum of the delay time of the gate circuits FY7 and FY9 after the signal YP0 is changed and FY10 in FIG. 11, or the sum of the delay time of the gate circuits FY8 and FY9 after the signal YP0 is changed and FY10 in FIG. 11; obviously, the time of the delay change of the voltage level code value signal is less than the time of the trailing edge of the output single pulse after the voltage level code value is changed by 2 gate circuits, and the requirement that the time of the delay change of the voltage level code value signal is earlier than the time of the trailing edge of the output single pulse after the voltage level code value is changed is met.

Fig. 13 shows an embodiment of an interlock control unit, and fig. 13(a) shows an interlock control unit embodiment 1 in which YR1 is a ROM memory. In the embodiment 1 of the compensation type main circuit in fig. 2, the compensation voltage of TB1 is low, and the compensation voltage of TB2 is high; and the compensation voltage of TB2 is 2 times the compensation voltage of TB 1. Table 3 is a logic truth table of the interlock control unit embodiment 1 for performing logic control on the voltage level code value output by the coding unit embodiment 1 and delayed by the delay protection unit in fig. 6 (a); the fluctuation range of the alternating current power supply voltage is 220V +/-10%, and the alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. When the logic function of the interlocking control unit is realized by adopting a ROM, P4 and Y22-Y20 are respectively connected to the address input ends A3-A0 of the ROM in a delayed manner, the data outputs D0-D5 of the ROM are the logic outputs of the interlocking control unit, and 6 output signals P51-P56 form a trigger control signal P5. In table 3, when the trigger zone disable signal is not asserted, P4 is equal to 0, and the voltage level code value is a value corresponding to the voltage level 1-7, the interlock control unit controls the compensated main circuit embodiment 1 to perform the corresponding voltage compensation; for example, when the input voltage is the lowest voltage level 1, the outputs of the P51, the P54 and the P56 are controlled to be 0 to turn on the bidirectional thyristors SR1, SR4 and SR6, and the outputs of the P52, the P53 and the P55 are controlled to be 1 to turn off the bidirectional thyristors SR2, SR3 and SR5, so that both TB1 and TB2 are subjected to forward compensation; when the input voltage is in a voltage level 2, controlling the outputs of P51, P53 and P56 to be 0 to turn on the bidirectional thyristors SR1, SR3 and SR6, controlling the outputs of P52, P54 and P55 to be 1 to turn off the bidirectional thyristors SR2, SR4 and SR5, and only enabling TB2 to carry out forward compensation; when the input voltage is at a voltage level of 4, controlling the outputs of P51, P53 and P55 to be 0 to turn on the bidirectional thyristors SR1, SR3 and SR5, and controlling the outputs of P52, P54 and P56 to be 1 to turn off the bidirectional thyristors SR2, SR4 and SR6, so as to realize 0 voltage compensation, namely, both TB1 and TB2 are not compensated; when the input voltage is in a voltage level of 5, controlling the outputs of P52, P53 and P56 to be 0 to turn on the bidirectional thyristors SR2, SR3 and SR6, controlling the outputs of P51, P54 and P55 to be 1 to turn off the bidirectional thyristors SR1, SR4 and SR5, and only enabling TB1 to carry out reverse compensation; and so on. When P4 is equal to 1, it indicates that there is fluctuation in AC power voltage, and the voltage level code value changes, and it needs to switch the electronic switch to change the compensation mode. In the switching process of the electronic switch, in order to avoid the short circuit of the power supply caused by the factor of delayed turn-off of the electronic switch when the upper and lower bridge arms in the thyristor bridge are switched, all the bidirectional thyristors in the thyristor bridge are turned off during the period when the trigger zone control signal is not active, i.e. when P4 in the embodiment is equal to 1, and the interlocking control unit controls all the P51-P56 to output 1.

TABLE 3

In table 3, when the non-trigger area control signal is invalid (P4 is equal to 0), the valid code values of the 7 voltage level code values P3 correspond to 7 sets of valid trigger control signals, and accordingly, the control of 7 voltage compensation states is realized; when the P2 is changed to make P4 active (P4 equals 1), 1 group of active trigger control signals are corresponded, and the interlock control unit outputs 8 groups of active trigger control signals in total. When the P4 is invalid (P4 is equal to 0) and the voltage level code value P3 input by the interlock control unit is an invalid code value, the interlock control unit correspondingly outputs 1 group of invalid trigger control signals; the voltage level code value P2 and the delayed voltage level code value P3 of embodiment 1 of the coding unit of FIG. 6(a) have 7 valid code values, and only 1 possible invalid code value is 000. In Table 3, the 1 specific set of disable trigger control signals causes the P51 output to be 0 and the P52-P56 outputs to be 1; the specific invalid trigger control signal does not actually control the thyristor, and only makes the excitation coils of TB1 and TB2 connected with a zero line N and the excitation voltage 0 without performing voltage compensation even if the trigger control function of the thyristor is performed; the 1 specific inactive trigger control signal may also select other trigger combinations that are not voltage compensated, for example, such that the P53 output is 0 and the other outputs are 1.

In table 3, the trigger control signal output by the interlock control unit triggers the triac to be active at a low level when it is turned on. If the trigger control signal output by the interlocking control unit requires that the high level is effective when the trigger bidirectional thyristor is conducted, 1 in the output signal of the logic truth table in the table 3 needs to be changed into 0, and 0 needs to be changed into 1; when the function is realized by a ROM memory, the contents of the memory cell are inverted according to table 3.

Fig. 13(b) shows an interlock control unit embodiment 2 in which YR2 is a ROM memory. In the compensated main circuit embodiment 2 of fig. 3, the TB1 compensation voltage is the lowest, and the TB3 compensation voltage is the highest; and the compensation voltage of TB2 is 2 times of the compensation voltage of TB1, and the compensation voltage of TB3 is 2 times of the compensation voltage of TB 2. Table 4 is a logic truth table when the interlock control unit performs logic control on the voltage level code value output by the coding unit embodiment 2 and delayed by the delay protection unit in fig. 6 (b); the fluctuation range of the alternating current power supply voltage is 220V + 10% to 220V-20%, and the alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. In embodiment 2 of the interlock control unit shown in fig. 13(b), i.e. when the ROM memory YR2 is used to realize its logic function, the inputs P4 and Y23-Y20 are connected to the address terminals a4-a0 of the ROM memory, the data outputs D0-D7 of the ROM memory are the logic outputs of the interlock control unit, and 8 output signals P51-P58 constitute the trigger control signal P5. In table 4, when the trigger zone disable signal is not asserted, P4 is equal to 0, and the voltage level code value is a value corresponding to the voltage level 1-10, the interlock control unit controls the compensated main circuit embodiment 2 to perform the corresponding voltage compensation; for example, when the input voltage is at voltage level 7, the outputs of the P51, P53, P55 and P57 are controlled to be 0 to turn on the triacs SR1, SR3, SR5 and SR7, and the outputs of the P52, P54, P56 and P58 are controlled to be 1 to turn off the triacs SR2, SR4, SR6 and SR8, so that 0 voltage compensation is realized, that is, none of the TB1, TB2 and TB3 is compensated; when the input voltage is at a voltage level of 8, controlling the outputs of P52, P53, P56 and P58 to be 0 to turn on the bidirectional thyristors SR2, SR3, SR6 and SR8, and controlling the outputs of P51, P54, P55 and P57 to be 1 to turn off the bidirectional thyristors SR1, SR4, SR5 and SR7, so that TB1 is reversely compensated; when the input voltage is in a voltage level 9, controlling the outputs of P52, P54, P55 and P58 to be 0 to turn on the bidirectional thyristors SR2, SR4, SR5 and SR8, and controlling the outputs of P51, P53, P56 and P57 to be 1 to turn off the bidirectional thyristors SR1, SR3, SR6 and SR7, so that TB2 is reversely compensated; when the input voltage is in a voltage level of 10, controlling the outputs of P52, P53, P55 and P58 to be 0 to turn on the bidirectional thyristors SR2, SR3, SR5 and SR8, and controlling the outputs of P51, P54, P56 and P57 to be 1 to turn off the bidirectional thyristors SR1, SR4, SR6 and SR7, so that TB1 and TB2 perform reverse compensation at the same time; when the input voltage is in a voltage level 6, controlling the outputs of P51, P54, P55 and P57 to be 0 to turn on the bidirectional thyristors SR1, SR4, SR5 and SR7, and controlling the outputs of P52, P53, P56 and P58 to be 1 to turn off the bidirectional thyristors SR2, SR3, SR6 and SR8 so as to enable TB1 to carry out forward compensation; when the input voltage is in a voltage level 4, controlling the outputs of P51, P54, P56 and P57 to be 0 to turn on the bidirectional thyristors SR1, SR4, SR6 and SR7, and controlling the outputs of P52, P53, P55 and P58 to be 1 to turn off the bidirectional thyristors SR2, SR3, SR5 and SR8, so that TB1 and TB2 perform forward compensation at the same time; when the input voltage is in a voltage class 3, controlling the outputs of P51, P53, P55 and P58 to be 0 to turn on the bidirectional thyristors SR1, SR3, SR5 and SR8, and controlling the outputs of P52, P54, P56 and P57 to be 1 to turn off the bidirectional thyristors SR2, SR4, SR6 and SR7 so as to enable TB3 to carry out forward compensation; when the input voltage is in a voltage level 1, controlling the outputs of P51, P53, P56 and P58 to be 0 to turn on the bidirectional thyristors SR1, SR3, SR6 and SR8, and controlling the outputs of P52, P54, P55 and P57 to be 1 to turn off the bidirectional thyristors SR2, SR4, SR5 and SR7, so that TB2 and TB3 perform forward compensation at the same time; and so on. When the control signal of the non-trigger area is effective, when the P4 is equal to 1, the fluctuation of the alternating current power supply voltage is shown, the voltage level code value is changed, the electronic switch is required to be switched, the compensation mode is changed, all the bidirectional thyristors in the thyristor bridge are switched off at the moment, and the interlocking control unit controls the P51-P58 to output 1 completely.

TABLE 4

In table 4, when the non-trigger area control signal is invalid (P4 is equal to 0), the valid code values of the 10 voltage level code values P3 correspond to 10 sets of valid trigger control signals, and accordingly, the control of 10 voltage compensation states is realized; when the change in P2 makes P4 active (P4 equal to 1), there are 1 active set of trigger control signals, and the interlock control unit has 11 active set of trigger control signals. When the P4 is invalid (P4 is equal to 0) and the voltage level code value P3 input by the interlock control unit is an invalid code value, the interlock control unit corresponds to 1 group of specific invalid trigger control signals; FIG. 6(b) shows that the encoding unit of embodiment 2 has 10 valid encoding values P2 and the delayed P3, and may output 6 invalid encoding values; when outputting 6 invalid code values, the interlocking control unit outputs 1 same group of specific invalid trigger control signals; in Table 4, the 1 group of invalid toggle control signals makes the P51 output 0 and the P52-P58 outputs 1; the specific invalid trigger control signal does not actually control the thyristor, and only makes the excitation coils of TB1, TB2 and TB3 connected with a zero line N and the excitation voltage 0 even if the trigger control function of the thyristor is performed, and does not perform voltage compensation; the 1 specific inactive trigger control signal may also select other trigger combinations that are not voltage compensated, for example, such that the P53 output is 0 and the other outputs are 1.

In table 4, the trigger control signal output by the interlock control unit triggers the triac to be active at a low level when it is turned on. If the trigger control signal output by the interlock control unit requires that the high level is effective when the trigger bidirectional thyristor is conducted, 1 in the output signal of the logic truth table in table 4 needs to be changed into 0, and 0 needs to be changed into 1; when the function is realized by a ROM memory, the contents of the memory cell are inverted according to table 4. The combinational logic functions in table 3 or the truth table of table 4 can be implemented by other means besides ROM memory.

Fig. 14 shows an embodiment of a trigger circuit for triggering the triac SR1 in the trigger unit, which is composed of an ac trigger optocoupler UG1, a resistor RG1, and a resistor RG2, and the trigger control signal P51 is active at low level. The alternating current trigger optocoupler UG1 can be selected from phase-shifting bidirectional thyristor output optocouplers such as MOC3021, MOC3022, MOC3023, MOC3051, MOC3052 and MOC 3053. Power supply + VCCK is the controlled power supply controlled by the error detection control unit. The circuit structure of the trigger circuit for triggering the triacs SR2-SR6 in the compensated main circuit embodiment 1 in FIG. 2 or the triacs SR2-SR8 in the compensated main circuit embodiment 2 in FIG. 3 is the same as that of the triac SR 1. The trigger pulses output by the alternating current trigger optocoupler UG1 in fig. 14 from G11 and G12 and the trigger pulses output by other alternating current trigger optocouplers in the trigger unit jointly form a trigger signal P6.

FIG. 15 is an embodiment of an error detection control unit, wherein YR3 is a ROM memory, and the ROM memory constitutes a determination module for determining whether the input trigger control signal P5 is a valid trigger control signal; the triode VT, the triode VK1, the triode VK2, the relay coil KA, the freewheeling diode VD, the resistor RK1, the resistor RK2 and the resistor RK3 form a protection control circuit. + VCC2 is the power supply for the relay coil and the source for the trigger unit controlled power supply.

The error detection control unit in the embodiment of fig. 15 is used to determine the trigger control signal sent by the interlock control unit in the embodiment 1 in fig. 13(a), and table 5 is a logic truth table for determining whether the trigger control signal sent by the interlock control unit in the embodiment 1 is a valid trigger control signal.

When the trigger control signal sent by the interlock control unit embodiment 1 is 1 of 8 effective trigger control signals listed in the front 8 rows in table 5, the trigger control determination signal output by the determination module is effective, that is, P7 is 1, which indicates that the trigger control signal is an effective trigger control signal, the triodes VK1 and VK2 are turned on, the controlled power supply + VCCK is powered on, and the trigger unit normally operates and sends a corresponding trigger pulse according to the trigger control signal. The P7 is 1, and simultaneously controls the conduction of the triode VT, the relay coil KA is electrified, so that the normally open switches KA-1, KA-2 and KA-3 of the relay in the embodiment 1 of the compensation type main circuit in fig. 2 are closed, the normally closed switches KA-5 and KA-6 of the relay are opened, and the thyristor bridge is in a compensation working state. When the trigger control signal sent by the interlock control unit embodiment 1 is other signals, and is not any 1 of the 8 groups of valid trigger control signals listed in the front 8 rows in table 5, the trigger control determination signal output by the determination module is invalid, i.e., P7 is 0, the triodes VK1 and VK2 are turned off, the controlled power supply + VCCK is powered off, and the trigger unit does not work, i.e., does not send the trigger pulse for triggering the thyristor. P7 is 0, and simultaneously the triode VT is controlled to be cut off, and the relay coil KA loses power, so that normally open switches KA-1, KA-2 and KA-3 of the relay in the embodiment 1 of the compensation type main circuit in the figure 2 are disconnected, and the open circuit protection of a thyristor bridge is realized; normally closed switches KA-5 and KA-6 of the relay are controlled to be closed, so that the voltage applied to excitation coils TB1 and TB2 is 0. When the input of the interlocking control unit embodiment 1 is an invalid code value and outputs an invalid trigger control signal, as can be seen from table 5, the output of the discrimination module is also 0, so as to realize open-circuit protection of the thyristor bridge; therefore, no matter an invalid code value is output due to the fact that a coding error fault occurs in the coding unit, or an invalid trigger control signal is output due to the fact that a control error occurs in the interlocking control unit, the error detection control unit starts to carry out open-circuit protection on the thyristor bridge. When the logic truth table in table 5 is implemented by using a ROM memory, the address input of the ROM memory needs 6 bits, i.e., a0-a5 in table 5, and is correspondingly connected with input signals P51-P56; the data output of the ROM memory requires 1 bit, d0 in table 5, corresponding to the control signal P7 of the connection output.

TABLE 5

When the error detection control unit needs to determine the trigger control signal sent by the interlock control unit in embodiment 2 in fig. 13(b), table 6 is a logic truth table for determining whether the trigger control signal sent by the interlock control unit in embodiment 2 is a valid trigger control signal. When the trigger control signal sent by the interlock control unit embodiment 2 is 1 of the 11 effective trigger control signals listed in the front 11 rows in table 6, the trigger control determination signal output by the determination module is effective, that is, P7 is 1, which indicates that the trigger control signal is an effective trigger control signal, the triodes VK1 and VK2 are turned on, the controlled power supply + VCCK is powered on, and the trigger unit normally operates and sends a corresponding trigger pulse according to the trigger control signal. P7 is 1, and controls normally open switches KA-1, KA-2, KA-3 and KA-4 of the relay in embodiment 2 of the compensation type main circuit of the 3 to be closed, and normally closed switches KA-5, KA-6 and KA-7 of the relay to be opened, so that the thyristor bridge is in a compensation working state. When the trigger control signal sent by the interlock control unit embodiment 2 is other signals, and is not any 1 of the 11 groups of valid trigger control signals listed in the front 11 rows in table 6, the trigger control determination signal output by the determination module is invalid, i.e., P7 is 0, the triodes VK1 and VK2 are turned off, the controlled power supply + VCCK is powered off, and the trigger unit does not operate, i.e., does not send out trigger pulses for triggering the thyristor. P7 is 0, and normally open switches KA-1, KA-2, KA-3 and KA-4 of the relay in embodiment 2 of the compensation type main circuit of the 3 are controlled to be disconnected, so that open-circuit protection of a thyristor bridge is realized; the normally closed switches KA-5, KA-6 and KA-7 of the relays are controlled to be closed, so that the voltage applied to the excitation coils TB1, TB2 and TB3 is 0. When the input of the interlocking control unit embodiment 2 is an invalid code value and outputs an invalid trigger control signal, as can be seen from table 6, the output of the discrimination module is 0, so as to realize open-circuit protection of the thyristor bridge; similarly, no matter whether an invalid code value is output due to the coding unit having a coding error fault or an invalid trigger control signal is output due to the interlocking control unit having a control error, the error detection control unit starts to perform open-circuit protection on the thyristor bridge. When the logic truth table of table 6 is implemented by ROM memory, for example, the embodiment of fig. 15 is used to implement the function of error detection control unit, the address input of ROM memory YR3 in fig. 15 needs to be expanded to 8 bits, i.e., the address input needs a0-a7, corresponding to the connection input signals P51-P58; the data output of the ROM memory requires 1 bit, d0 in table 6, corresponding to the control signal P7 of the connection output.

TABLE 6

The combinational logic functions in table 5 or the truth table of table 6 can be implemented by other means besides ROM memory.

When the error detection control unit judges that the input trigger control signal is not an effective trigger control signal, the error detection control unit sends a protection control signal to the compensation type main circuit, so that the thyristor bridge is in an open circuit protection state, the compensation type alternating current voltage stabilizer does not compensate the input voltage, and the voltage output by the voltage stabilizer is the input alternating current power supply voltage. When the thyristor bridge is in the open-circuit protection state, if the error detection control unit judges that the input trigger control signal is recovered to be the effective trigger control signal, the error detection control unit automatically stops the open-circuit protection state of the thyristor bridge, and the thyristor bridge is in the compensation working state again.

As can be seen from the above embodiments and the working process thereof, as long as the error detection control unit determines that the input trigger control signal is not an effective trigger control signal, that is, the trigger control signal is invalid, the thyristor bridge is started and is in an open-circuit protection state while the trigger pulse for triggering the thyristor is not sent out; when the interlock control unit outputs the invalid trigger control signal, the error detection control unit starts the thyristor bridge to be in an open-circuit protection state; when the thyristor bridge is in the open-circuit protection state, if the error detection control unit judges that the compensation type alternating current voltage stabilizer enters the normal logic control state again, namely the error detection control unit judges that the input trigger control signal is recovered to be the effective trigger control signal, the open-circuit protection state of the thyristor bridge can be automatically stopped and the thyristor bridge is enabled to be in the compensation working state again. The function effectively strengthens the protection force of the compensation type alternating current voltage stabilizer against the abnormity of the working process, so that the compensation type alternating current voltage stabilizer is more reliable in working.

In the above embodiments, all of the ROM memory, logic gates, and logic function integrated circuits are powered by a single power supply + VCC 1. In addition to the technical features described in the specification, other techniques of the compensated ac voltage regulator are conventional techniques known to those skilled in the art.

Claims

1. A kind of compensation type alternating current voltage stabilizer, characterized by:

the device comprises a compensation type main circuit, a sampling comparison unit, a coding unit, a delay protection unit, an interlocking control unit, a trigger unit and an error detection control unit;

the compensation type main circuit comprises a compensation transformer bank, a thyristor bridge and a relay protection switch;

the sampling comparison unit samples the voltage of the alternating current power supply, outputs a voltage grade comparison value to the coding unit, and the coding unit outputs a voltage grade coding value; the delay protection unit inputs a voltage grade coding value and outputs a delayed voltage grade coding value and a non-trigger area control signal; the interlocking control unit inputs the delayed voltage grade code value and the control signal of the non-trigger area and outputs a trigger control signal; the trigger unit controls the on-off of a thyristor in a thyristor bridge of the main circuit according to an input trigger control signal;

controlling the control signal of the non-trigger area to output a single pulse after the voltage level code value is changed; the control signal of the non-trigger area is effective in the period of outputting the single pulse and is ineffective in the period of not outputting the single pulse;

in the time delay protection unit, the delayed voltage level code value signal change time is later than the leading edge time of a single pulse in the non-trigger area control signal after the voltage level code value is changed and is earlier than the trailing edge time of the single pulse in the non-trigger area control signal after the voltage level code value is changed;

when the control signal of the non-trigger area input by the interlocking control unit is invalid and the input voltage level code value is an effective code value, outputting an effective trigger control signal corresponding to the effective code value to perform compensation control on the alternating-current power supply voltage; when the control signal of the non-trigger area input by the interlocking control unit is invalid and the input voltage level code value is not a valid code value, outputting an invalid trigger control signal;

the voltage level code value output by the code unit is sharedMThe number of +1 valid code values,corresponding active trigger control signals are commonM+1 group, carry outMControl of +1 voltage compensation states; the above-mentionedMGreater than or equal to 1;

when the control signal of the non-trigger area input by the interlocking control unit is effective, the interlocking control unit outputs 1 group of effective trigger control signals to carry out switching control between voltage compensation states; the effective trigger control signal output by the interlock control unit is sharedM+2 groups;

when switching control between voltage compensation states is carried out, the interlocking control unit outputs effective trigger control signals for turning off all thyristors in the thyristor bridge;

the error detection control unit determines whether the input trigger control signal is erroneous according to the input trigger control signalMWhen the group +2 effectively triggers the group 1 in the control signals, the triggering control signals are correct, otherwise, the triggering control signals are wrong;

when the error detection control unit judges that the input trigger control signal is in error, the thyristor bridge is controlled to be in an open-circuit protection state;

the specific method for controlling the thyristor bridge to be in the open-circuit protection state is to control to disconnect all upper bridge arms of the thyristor bridge to perform open-circuit protection on the thyristor bridge, or to control to disconnect all lower bridge arms of the thyristor bridge to perform open-circuit protection on the thyristor bridge.

2. The compensated ac voltage regulator of claim 1, wherein: when the thyristor bridge is in an open-circuit protection state, the error detection control unit automatically stops the open-circuit protection state of the thyristor bridge when judging that the input trigger control signal is recovered to a correct signal.

3. The compensated ac voltage regulator of claim 1, wherein: the delay protection unit consists of a delay detection module and a non-trigger area control signal generation module; the delay detection module comprisesKEach delay detection circuit delays an input signal to obtain a delayed output signal, and simultaneously performs edge detection on the input signal to output an edge detection signal;Kpersonal extensionTime detection circuit pairKDelaying the bit voltage level code value to obtain delayedKBit voltage level code value, andKcarrying out edge detection on the bit voltage grade coding value to obtainKAn edge detection signal; input to the zone-not-triggered control signal generating moduleKThe edge detection signal is converted into a control signal of the non-trigger area and output.

4. The compensated ac voltage regulator of claim 3, wherein:Kin the same delay detection circuits, each delay detection circuit comprises a resistor RY3, a capacitor CY3, an inverter FY5, an inverter FY6, a NAND gate FY7, an OR gate FY8 and a NAND gate FY 9; the input end of the inverter FY5 is connected to the input signal end; one end of the resistor RY3 is connected to the output end of the inverter FY5, and the other end of the resistor RY3 is respectively connected to one end of the capacitor CY3, one input end of the NAND gate FY7, one input end of the OR gate FY8 and the input end of the inverter FY 6; the other end of the capacitor CY3 is connected to the ground, the other input end of the NAND gate FY7 is connected to the input signal end, and the other input end of the OR gate FY8 is connected to the input signal end; 2 input ends of the NAND gate FY9 are respectively connected to the output end of the NAND gate FY7 and the output end of the OR gate FY 8; the output end of the inverter FY6 is a delayed output signal end; the output end of the NAND gate FY9 is an edge detection signal output end.

5. The compensated ac voltage regulator of claim 3, wherein: the non-trigger area control signal generation module is provided withKAn or gate FY10 of the input signal terminal; of OR gate FY10KInput signal terminals are respectively connected toKAn edge detection signal output terminal in the delay detection circuit; the output of or gate FY10 outputs a no trigger area control signal.