CN109254610B

CN109254610B - Single-phase AC voltage stabilizer

Info

Publication number: CN109254610B
Application number: CN201811355996.2A
Authority: CN
Inventors: 肖会芹; 凌云; 王兵; 袁川来; 曾红兵
Original assignee: Hunan University of Technology
Current assignee: Ma Genying
Priority date: 2018-11-15
Filing date: 2018-11-15
Publication date: 2020-09-29
Anticipated expiration: 2038-11-15
Also published as: CN109254610A

Abstract

A single-phase alternating current voltage stabilizer comprises a compensation type main circuit, an analog-digital conversion coding unit, a delay protection unit, an interlocking control unit, a trigger unit and an error detection control unit, wherein the compensation type main circuit consists of a compensation transformer bank, a thyristor bridge and a relay protection switch; when the interlocking control is realized, the error detection control unit also performs open circuit protection on the thyristor bridge by judging whether the analog-digital conversion coding unit or the interlocking control unit has a logic error or not, so that the protection strength of the single-phase alternating current voltage stabilizer against the abnormity of the working process is effectively enhanced, and the single-phase alternating current voltage stabilizer can work more stably and reliably.

Description

Single-phase AC voltage stabilizer

Technical Field

The invention relates to the technical field of power supplies, in particular to a single-phase alternating current voltage stabilizer.

Background

The existing compensation type AC voltage stabilizer has the advantages of wide voltage stabilizing range, almost no distortion of waveform, high efficiency of the whole machine and strong load adaptability. The principle is that switching of different winding coils of a primary winding on a compensation transformer is automatically controlled according to the high-low condition of input voltage, bidirectional multi-gear voltage compensation is provided by utilizing the transformation ratio relation of a primary side working winding and a secondary winding or by adjusting the voltage applied to the primary winding, and therefore the purpose of voltage regulation and stabilization is achieved.

The existing compensation type alternating current voltage stabilizer has the following defects: when the motor is adopted to control the carbon brush to move to change the application of different voltages to the excitation coil of the compensation transformer, the carbon brush is easy to wear and often fails. Switching different winding coils of a primary winding on a compensation transformer by adopting an electronic switch switching mode, or when voltage applied to the primary winding is adjusted, the delayed turn-off of the electronic switch is easy to cause a power supply short-circuit fault; when the electronic switch is controlled to be switched by adopting a program mode of a singlechip, a PLC and the like, the problems of program runaway, dead halt and the like can also cause the failure of the voltage stabilizer or cause the short-circuit fault of a power supply due to the error of control logic.

Disclosure of Invention

In order to solve the problems of the existing compensation type alternating current voltage stabilizer, the invention provides a compensation type single-phase alternating current voltage stabilizer which comprises a compensation type main circuit, an analog-digital conversion coding unit, a time delay protection unit, an interlocking control unit, a trigger unit and an error detection control unit.

The compensation type main circuit consists of a compensation transformer bank, a thyristor bridge and a relay protection switch; the on-off combination of the thyristors in the thyristor bridge controls the voltage and polarity combination of the excitation coil of each compensation transformer in the compensation transformer bank to realize different compensation working states, namely voltage compensation states. The analog-to-digital conversion coding unit is used for sampling the voltage of the alternating current power supply, dividing the voltage in the fluctuation interval range of the alternating current power supply into voltage grade intervals after analog-to-digital conversion and converting the voltage into a voltage grade coding value for output; the delay protection unit inputs a voltage grade coding value and outputs a delayed voltage grade coding value and a non-trigger area control signal; the interlocking control unit inputs the delayed voltage grade code value and the control signal of the non-trigger area and outputs a trigger control signal; the trigger unit controls the on-off of a thyristor in a thyristor bridge of the main circuit according to an input trigger control signal; the error detection control unit starts or stops the open-circuit protection of the thyristor bridge according to whether the input trigger control signal is wrong or not. The voltage level comparison value and the voltage level encoding value are both binary values.

When the alternating-current power supply voltage fluctuation causes the voltage grade code value to change, so that the on-off combination state of the thyristors in the thyristor bridge needs to be changed, maintaining a non-trigger area time between 2 different on-off combination states of the thyristors in the thyristor bridge, and turning off all the thyristors in the thyristor bridge; maintaining a no-trigger zone time is accomplished by a no-trigger zone control signal. Controlling the control signal of the non-trigger area to output a single pulse after the voltage level code value is changed; the no-trigger area control signal is active during the output of a single pulse and inactive during the non-output of a single pulse. In the time delay protection unit, the delayed voltage level code value signal change time is later than the leading edge time of a single pulse output in the non-trigger area control signal after the voltage level code value is changed; in the time delay protection unit, the change time of the delayed voltage level code value signal is earlier than the back edge time of a single pulse output in the non-trigger area control signal after the voltage level code value is changed. Further, after the voltage level code value is changed, the width time of the single pulse in the non-trigger area control signal is selected from 10ms to 30 ms.

Dividing the voltage in the alternating current power supply voltage fluctuation interval range into M voltage grade intervals for compensation control; controlling and selecting 0 or 1 or a plurality of compensation transformers to perform voltage compensation by the on-off combination state of the thyristors in the thyristor bridge, so as to realize the voltage compensation state corresponding to the voltage grade interval; each voltage class interval of the alternating current power supply voltage corresponds to a voltage compensation state. The voltage level code values have M effective code values, and the M voltage level intervals correspond to the M effective code values one by one. The effective trigger control signals output by the interlocking control unit are M +1 groups in total; m groups in the effective M +1 groups of trigger control signals are used for realizing compensation control of M voltage compensation states of the alternating-current power supply voltage, and 1 group is used for turning off all thyristors in the thyristor bridge. M is an integer of 2 or more.

When the control signal of the non-trigger area is effective, the interlocking control unit outputs an effective trigger control signal for turning off all thyristors in all thyristor bridges; when the control signal of the non-trigger area is invalid, the interlocking control unit outputs an effective trigger control signal corresponding to the voltage grade code value, and compensation control of the alternating current power supply voltage is realized.

When the control signal of the non-trigger area input by the interlocking control unit is effective, the interlocking control unit outputs 1 group of effective trigger control signals for turning off all thyristors in the thyristor bridge; when the control signal of the non-trigger area input by the interlocking control unit is invalid and the input voltage level code value is 1 of the M effective code values, 1 group of the M groups of trigger control signals is correspondingly output for realizing the compensation control of the alternating current power supply voltage. When the control signal of the non-trigger area input by the interlocking control unit is invalid and the input voltage level code value is an invalid code value, 1 group of specific invalid trigger control signals are output.

The basis of the error detection control unit for judging whether the input trigger control signal is wrong is as follows: when the input trigger control signal is 1 group in the M +1 group effective trigger control signals, the trigger control signal is correct, otherwise, the trigger control signal is wrong.

And when the error detection control unit judges that the input trigger control signal is wrong, the thyristor bridge is controlled to be in an open-circuit protection state by controlling to disconnect all upper bridge arms of the thyristor bridge to carry out open-circuit protection on the thyristor bridge or controlling to disconnect all lower bridge arms of the thyristor bridge to carry out open-circuit protection on the thyristor bridge. The thyristor bridge is in an open-circuit protection state, and the error detection control unit automatically stops the open-circuit protection state of the thyristor bridge when judging that the input trigger control signal is recovered to a correct signal.

The trigger unit converts the trigger control signal into a thyristor trigger signal to realize on-off control of a thyristor in a thyristor bridge of the compensation type main circuit. When the error detection control unit judges that the input trigger control signal is in error, the working power supply of the trigger unit is cut off, and the trigger unit stops sending out thyristor trigger pulses; when the error detection control unit judges that the input trigger control signal has no error, the working power supply of the trigger unit is switched on, and the trigger unit sends out corresponding thyristor trigger pulse according to the input trigger control signal to control the on-off of the thyristor in the thyristor bridge.

The thyristors in the thyristor bridge are bidirectional thyristors or thyristor alternating current switches formed by connecting 2 unidirectional thyristors in reverse parallel.

The delay protection unit consists of a delay detection module and a non-trigger area control signal generation module; the delay detection module comprises K identical delay detection circuits, each delay detection circuit delays an input signal to obtain a delayed output signal, and simultaneously performs edge detection on the input signal to output an edge detection signal; the K delay detection circuits respectively delay the K-bit voltage level code value to obtain a delayed K-bit voltage level code value, and perform edge detection on the K-bit voltage level code value to obtain K edge detection signals; the non-trigger area control signal generation module converts the input K edge detection signals into non-trigger area control signals and outputs the non-trigger area control signals.

Each of the K identical delay detection circuits comprises a resistor RY3, a capacitor CY3, an inverter FY5, an inverter FY6, a NAND gate FY7, an OR gate FY8 and a NAND gate FY 9; the input end of the inverter FY5 is connected to the input signal end; one end of the resistor RY3 is connected to the output end of the inverter FY5, and the other end of the resistor RY3 is respectively connected to one end of the capacitor CY3, one input end of the NAND gate FY7, one input end of the OR gate FY8 and the input end of the inverter FY 6; the other end of the capacitor CY3 is connected to the ground, the other input end of the NAND gate FY7 is connected to the input signal end, and the other input end of the OR gate FY8 is connected to the input signal end; 2 input ends of the NAND gate FY9 are respectively connected to the output end of the NAND gate FY7 and the output end of the OR gate FY 8; the output end of the inverter FY6 is a delayed output signal end; the output end of the NAND gate FY9 is an edge detection signal output end.

Or, in the K identical delay detection circuits, each delay detection circuit includes a resistor RY0, a resistor RY1, a resistor RY2, a capacitor CY0, a capacitor CY1, a capacitor CY2, a diode DY1, a diode DY2, a driving gate FY0, an inverter FY1, an inverter FY2, an inverter FY3, and a nand gate FY 4; the resistor RY0 is connected between the input signal end and the input end of the driving gate FY0, the capacitor CY0 is connected between the input end of the driving gate FY0 and the ground end, and the output end of the driving gate FY0 is a delayed output signal end; the capacitor CY1 is connected between the input signal end and the input end of the inverter FY1, the resistor RY1 is connected between the input end of the inverter FY1 and the ground end, the cathode of the diode DY1 is connected to the input end of the inverter FY1, and the anode of the diode DY1 is connected to the ground end; the input of the inverter FY2 is connected to the input signal terminal; the capacitor CY2 is connected between the output end of the inverter FY2 and the input end of the inverter FY3, the resistor RY2 is connected between the input end of the inverter FY3 and the ground end, the cathode of the diode DY2 is connected to the input end of the inverter FY3, and the anode of the diode DY2 is connected to the ground end; 2 input ends of the NAND gate FY4 are respectively connected to the output end of the inverter FY1 and the output end of the inverter FY 3; the output of the nand gate FY4 is an edge detection signal output.

Or, in the K identical delay detection circuits, each delay detection circuit includes a resistor RY1, a resistor RY2, a capacitor CY1, a capacitor CY2, a diode DY1, a diode DY2, an inverter FY1, an inverter FY2, an inverter FY3, an inverter FY11, an inverter FY12, an inverter FY13, an inverter FY14, and a nand gate FY 4; the input end of the inverter FY11 is connected to an input signal end, the input end of the inverter FY12 is connected to the output end of the inverter FY11, the input end of the inverter FY13 is connected to the output end of the inverter FY12, the input end of the inverter FY14 is connected to the output end of the inverter FY13, and the output end of the inverter FY14 is a delayed output signal end; the capacitor CY1 is connected between the input signal end and the input end of the inverter FY1, the resistor RY1 is connected between the input end of the inverter FY1 and the ground end, the cathode of the diode DY1 is connected to the input end of the inverter FY1, and the anode of the diode DY1 is connected to the ground end; the input of the inverter FY2 is connected to the input signal terminal; the capacitor CY2 is connected between the output end of the inverter FY2 and the input end of the inverter FY3, the resistor RY2 is connected between the input end of the inverter FY3 and the ground end, the cathode of the diode DY2 is connected to the input end of the inverter FY3, and the anode of the diode DY2 is connected to the ground end; 2 input ends of the NAND gate FY4 are respectively connected to the output end of the inverter FY1 and the output end of the inverter FY 3; the output end of the NAND gate FY4 is an edge detection signal output end.

The no-trigger area control signal generation module is an OR gate FY10 with K input signal terminals; k input signal ends of the OR gate FY10 are respectively connected to edge detection signal output ends of the K delay detection circuits; the output of or gate FY10 outputs a no trigger area control signal.

The invention has the beneficial effects that: the single-phase alternating current voltage stabilizer adopting the compensation transformer bank and the thyristor bridge to perform voltage compensation ensures that upper and lower bridge arm thyristors of the same full-bridge circuit cannot be conducted simultaneously, namely, the interlocking control of the upper and lower bridge arm thyristors of the same full-bridge circuit is realized, and simultaneously, logic errors and invalid code values are output to a possibly-occurring coding unit, and under the condition that the logic errors and invalid trigger control signals are output by the interlocking control unit, the trigger pulse is stopped being sent out and the thyristor bridge is subjected to open-circuit protection, so that the protection strength of the single-phase alternating current voltage stabilizer against the abnormity of the working process is effectively enhanced, the fault of the control circuit is prevented from being further expanded into a main circuit short-circuit fault, the damage of the voltage stabilizer is reduced, and the cost; when the thyristor bridge is in the open-circuit protection state, if the single-phase alternating-current voltage stabilizer enters the normal logic control state again, the open-circuit protection state of the thyristor bridge can be automatically stopped and the thyristor bridge is enabled to be in the compensation working state again; the on-off switching of the thyristor is controlled without adopting a program mode of a singlechip, a PLC and the like, so that the faults of the voltage stabilizer caused by the problems of program runaway, dead halt and the like are avoided. The single-phase alternating current voltage stabilizer has the advantages that the single-phase alternating current voltage stabilizer can work more stably and reliably.

Drawings

FIG. 1 is a block diagram of a system configuration of a single-phase AC voltage regulator;

FIG. 2 shows an embodiment 1 of a compensated main circuit;

FIG. 3 illustrates an embodiment of a compensated main circuit 2;

FIG. 4 shows an embodiment 1 of an ADC encoding unit;

FIG. 5 shows an embodiment 2 of an ADC encoding unit;

FIG. 6 is a block diagram of an embodiment of a delay protection unit;

fig. 7 is a circuit embodiment 1 of the delay detection module for detecting the delay of the voltage level code value signal Y11;

fig. 8 is a circuit embodiment 2 of the delay detection module for detecting the delay of the voltage level code value signal Y11;

fig. 9 is a circuit embodiment 3 of the delay detection circuit of the delay detection module for the voltage level code value signal Y11;

FIG. 10 is a block diagram of an embodiment of a no trigger area control signal generation module;

FIG. 11 is a diagram illustrating a partial correlation waveform in the delay protection unit;

fig. 12 is an embodiment of an interlock control unit, wherein fig. 12(a) is an interlock control unit embodiment 1, and fig. 12(b) is an interlock control unit embodiment 2;

FIG. 13 is an embodiment of a trigger circuit for triggering the triac SR1 in the trigger unit;

FIG. 14 is an error detection control unit embodiment.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

Fig. 1 is a system block diagram of a single-phase ac voltage regulator, in which an analog-to-digital conversion coding unit samples the voltage of an ac power supply and outputs a voltage level code value P2 after analog-to-digital conversion; the delay protection unit inputs a voltage level code value P2 and outputs a delayed voltage level code value P3 and a non-trigger area control signal P4; the interlock control unit inputs the delayed voltage level code value P3 and the non-trigger area control signal P4 and outputs a trigger control signal P5; the trigger unit sends a trigger signal P6 to the compensation type main circuit according to an input trigger control signal P5 to control the on-off of a thyristor in a thyristor bridge; the error detection control unit determines whether the input trigger control signal P5 is an effective trigger control signal, and sends a protection control signal to the compensation type main circuit according to the determination result to perform open-circuit protection on the thyristor bridge.

Fig. 2 shows a compensation type main circuit embodiment 1, in which a compensation transformer bank is composed of compensation transformers TB1 and TB2, a thyristor bridge is composed of 6 bidirectional thyristors SR1-SR6, a fuse FU1, normally open switches KA-1, KA-2 and KA-3 of a relay, and normally closed switches KA-5 and KA-6 of the relay constitute a relay protection circuit.

In fig. 2, the compensation coils of the compensation transformers TB1 and TB2 are both connected in series to the phase line, the input end of the phase line is LA1, and the output end is LA 2. The voltage on the TB1, TB2 excitation coils is controlled by a thyristor bridge. The 1 thyristor full-bridge circuit comprises an upper thyristor bridge arm and a lower thyristor bridge arm. In fig. 2, one ends of TB1 and TB2 excitation coils are connected in parallel and then connected to a thyristor full-bridge circuit composed of SR1 and SR2, and the other ends of TB1 and TB2 excitation coils are connected to a thyristor full-bridge circuit composed of SR3 and SR4, and SR5 and SR6, respectively. If the compensation voltages of TB1 and TB2 are different, and no compensation method for mutual cancellation of the compensation voltages is considered, the compensation transformer bank has 6 voltage compensation states at most, namely, forward TB1, forward TB2, forward TB1+ TB2, reverse TB1, reverse TB2 and reverse TB1+ TB2, and the ac power supply voltage input by phase line input terminal LA1 can be divided into 7 voltage intervals for compensation control at most when a voltage compensation state of 0 is applied when the input voltage is within a normal range. In fig. 2, N is a zero line, and G11, G12 to G61, and G62 are trigger signal input ends of the triacs SR1 to SR6, respectively.

Fig. 3 shows a compensation type main circuit embodiment 2, in which a compensation transformer bank is composed of compensation transformers TB1, TB2, TB3, a thyristor bridge is composed of 8 bidirectional thyristors SR1-SR8, a fuse FU1, normally open switches KA-1, KA-2, KA-3, KA-4 of relays, and normally closed switches KA-4, KA-5, KA-6 of relays constitute a relay protection circuit.

In fig. 3, the compensation coils of the compensation transformers TB1, TB2, and TB3 are all connected in series to the phase line, where the input end of the phase line is LA1 and the output end is LA 2. The voltages of the excitation coils of TB1, TB2 and TB3 are controlled by a thyristor bridge, one ends of the excitation coils of TB1, TB2 and TB3 are connected in parallel and then connected to a thyristor full-bridge circuit consisting of SR1 and SR2, and the other ends of the excitation coils of TB1, TB2 and TB3 are respectively connected to a thyristor full-bridge circuit consisting of SR3 and SR4, SR5 and SR6, and SR7 and SR 8. If the compensation voltages of TB1, TB2, and TB3 are different, and no compensation mode in which the compensation voltages cancel each other is considered, the compensation transformer bank has 7 voltage compensation states in the forward direction, 7 voltage compensation states in the reverse direction, and 14 voltage compensation states in the reverse direction, and a0 voltage compensation state when the input voltage is within the normal range is applied, and the alternating-current power supply voltage input at the phase line input end LA1 can be divided into 15 voltage intervals at most for compensation control. In fig. 3, N is a zero line, and G11, G12 to G81, and G82 are trigger signal input terminals of the triacs SR1 to SR8, respectively.

Each of the triacs of fig. 2 and 3 may be replaced by 2 antiparallel triacs. In fig. 2 and 3, the relay normally open switch and the relay normally closed switch form a relay protection switch.

The analog-to-digital conversion coding unit samples the voltage of the alternating current power supply, and outputs a voltage grade coding value formed by binary after analog-to-digital conversion of the voltage in the fluctuation range of the alternating current power supply voltage.

Fig. 4 shows an analog-to-digital conversion coding unit embodiment 1. In fig. 4, FD1 is a true effective value detection device LTC1966, and the LTC1966, a transformer TV1, a capacitor CV1, a capacitor CV2, a resistor RV1, and a resistor RV2 form an effective value detection circuit, and measures the effective values of the ac power supply voltages input from a phase line L1 and a zero line N to obtain a sampled ac power supply voltage value U1. UIN1 and UIN2 of LTC1966 are alternating voltage differential input terminals, USS is a negative power input terminal capable of being grounded, UDD is a positive power input terminal, GND is a ground terminal, EN is a low-level effective enable control input terminal, UOUT is a voltage output terminal, and COM is an output voltage return terminal.

In fig. 4, FD2 is a double-integration a/D converter ICL7109, which is used to divide the voltage of the ac power supply voltage fluctuation interval into voltage level intervals and convert the voltage level intervals into binary voltage level code values for output. In fig. 4, the RUN/hold terminal RUN, the low byte enable terminal LBEN, and the TEST terminal TEST of the ICL7109 are connected to the high level, the chip select terminal CE/LOAD, the MODE terminal MODE, the high byte enable terminal HBEN, and the oscillator select terminal OSC SEL are connected to the low level, and they operate in the continuous (i.e., automatic repeat) conversion MODE and the high byte direct output MODE; the crystal oscillator XT1 is connected to the oscillator input terminal OSC IN and the oscillator output terminal OSC OUT of ICL 7109; one end of an integrating capacitor C11, one end of an integrating resistor R11 and one end of an automatic zero-setting capacitor C12 are connected to form an integrating circuit, and the other end of the integrating capacitor C11, one end of an integrating resistor R11 and one end of an automatic zero-setting capacitor C12 are respectively connected to an integrating capacitor end INT, a buffer output end BUF and an automatic zero-setting capacitor end AZ of the ICL; a differential input high-side IN HOL of ICL7109 inputs the AC power supply voltage sampled value U1, and a differential input low-side IN LO is connected to a reference voltage output terminal REF OUT; the resistor RF1 and the resistor RF2 divide the reference voltage to obtain a reference voltage Uref on the resistor RF2, and the Uref is input to a reference voltage positive input end REF IN + and a reference voltage negative input end REF IN-; the reference capacitor C13 is connected to a reference capacitor positive input terminal REF CAP + and a reference capacitor negative input terminal REF CAP-; v + of ICL7109 is a positive power supply end connected to a power supply + VCC; v-of ICL7109 is a negative power supply end connected to power supply VCC; the GND of ICL7109 is the digital ground and COMMON is the analog ground, both connected to the COMMON ground GND.

Assuming that the fluctuation range of the input alternating current power supply voltage is 220V ± 10%, the compensation type main circuit embodiment 1 is required to be adopted to stabilize the input alternating current power supply voltage within the range of 220V ± 2% for output, and the fluctuation range of the alternating current power supply voltage is 242V to 198V, at this time, the analog-to-digital conversion coding unit embodiment 1 of fig. 4 is adopted, the voltage input between 242V and 198V can be divided into 7 voltage class intervals with the interval voltage size of 6.4V, wherein the voltage of 3 voltage class intervals is higher than the required output voltage range, and the voltage reduction compensation is required; the voltage of the 3 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 6.4V is not more than 220V +/-1.5 percent, and the requirement that the output is controlled within 220V +/-2 percent is met; the fluctuation interval of the alternating current power supply voltage corresponding to 7 voltage class intervals of 6.4V is 242.4V to 197.6V, and the actual fluctuation range is covered. The compensation is carried out by adopting the compensation type main circuit embodiment 1 in the figure 2, the compensation voltage of TB1 is low, and the compensation voltage of TB2 is high; the compensation voltage of the TB2 is 2 times of the compensation voltage of the TB1, and when the voltage on the exciting coil is 220V, the TB1 compensation voltage is 6.4V, and the TB2 compensation voltage is 12.8V. IN fig. 4, ICL7109 a/D converts the differential voltage between the differential input high side IN HOL and the differential input low side IN LO; the actual alternating-current power supply voltage fluctuation interval corresponding to 7 voltage class intervals of 6.4V is 242.4V to 197.6V, and the actual fluctuation range is covered; the reference voltage Ucp output from the reference voltage output terminal REF OUT, input to the differential input low-side IN LO should correspond to the lower theoretical value 197.6V of the fluctuation range of the ac power supply voltage; therefore, the transformation ratio of the transformer TV1 and the voltage division ratio of the resistor RV1 and the resistor RV2 are determined, and the sampled value U1 of the ac power supply voltage should be equal to the reference voltage Ucp output by the reference voltage output terminal REF OUT when the ac power supply voltage is a theoretical value of 197.6V at the lower limit. In fig. 4, the voltage level code value P2 output by the analog-to-digital conversion coding unit is composed of data Y14, Y13, Y12, Y11 output from the top 4 bits B12, B11, B10, B9 of ICL 7109; the 7 voltage level code values of Y14, Y13, Y12 and Y11 corresponding to 7 voltage level intervals from low to high are 0000, 0001, 0010, 0011, 0100, 0101 and 0110 respectively, and the method is realized by adjusting the size of the reference voltage Uref. The method for adjusting the size of the reference voltage Uref is as follows: when the voltage of the alternating current power supply fluctuates up and down at a demarcation voltage 236V of the highest 2 voltage class intervals, setting (namely adjusting) the voltage division ratio of the resistor RF1 and the resistor RF2 to enable the numerical values of Y14, Y13, Y12 and Y11 to fluctuate between 0110 and 0101; the second method for adjusting the size of the reference voltage Uref is as follows: let Ux be the voltage variation range of the differential input high-side IN HOL and the differential input low-side IN LO when the AC power supply voltage fluctuates IN the theoretical range of 197.6V to 242.4V, there are

The variation range of Ux corresponds to 7 minimum code values of B12, B11, B10 and B9; let the input-change full-scale input voltage range of 10 BCD code values corresponding to B12, B11, B10 and B9 be Um, have

The reference voltage of ICL7109 is 1/2 of full scale input voltage, there is

Therefore, in this case, it is only necessary to adjust the voltage division ratio between the resistors RF1 and RF2 so that Uref is equal to the calculated value of equation (1).

Assuming that the fluctuation range of the input alternating current power supply voltage is 220V + 10% to 220V-20%, the compensation type main circuit embodiment 2 is required to be adopted to stabilize the input alternating current power supply voltage within the range of 220V ± 2% for output, and the fluctuation range of the alternating current power supply voltage is 242V to 176V, at this time, the analog-to-digital conversion coding unit embodiment 1 of fig. 4 is adopted, the voltage input between 242V and 176V can be divided into 10 voltage class intervals with the interval voltage size of 7V, wherein the voltage of 3 voltage class intervals is higher than the required output voltage range, and the voltage reduction compensation is required; the voltage of the 6 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 7V is 220V +/-1.6%, and the requirement that the output is controlled within 220V +/-2% is met; the fluctuation interval of the alternating current power supply voltage corresponding to 10 voltage class intervals of 7V is 244.5V to 174.5V, and the actual fluctuation range is covered. The compensation is carried out by adopting the compensation type main circuit embodiment 2 in FIG. 3, the compensation voltage TB1 is the lowest, and the compensation voltage TB3 is the highest; the compensation voltage of the TB2 is 2 times of the compensation voltage of the TB1, the compensation voltage of the TB3 is 2 times of the compensation voltage of the TB2, and then when the voltage on the exciting coil is alternating current 220V, the TB1 compensation voltage is 7V, the TB2 compensation voltage is 14V, and the TB3 compensation voltage is 28V. At this time, the actual alternating-current power supply voltage fluctuation interval corresponding to 10 voltage class intervals of 7V is 244.5V to 174.5V, and the actual fluctuation range is covered; the reference voltage Ucp output from the reference voltage output terminal REF OUT, input to the differential input low-side IN LO should correspond to the lower theoretical value 174.5V of the ac supply voltage fluctuation interval range; therefore, the transformation ratio of the transformer TV1 and the voltage division ratio of the resistor RV1 and the resistor RV2 are determined, and when the ac power supply voltage is 174.5V, the sampled value U1 of the ac power supply voltage should be equal to the reference voltage Ucp output by the reference voltage output terminal REF OUT. In fig. 4, the voltage level code value P2 output by the analog-to-digital conversion coding unit is composed of data Y14, Y13, Y12, and Y11 output from the top 4 bits B12, B11, B10, and B9 of ICL7109, and 10 voltage level code values corresponding to voltage level intervals of 10 voltage levels from low to high, Y14, Y13, Y12, and Y11, respectively, are 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, and 1001, and is implemented by adjusting the size of the reference voltage Uref. The method for adjusting the size of the reference voltage Uref is as follows: when the alternating current power supply voltage fluctuates up and down at the boundary of the two highest voltage class intervals (namely 237.5V of the alternating current power supply voltage), setting (namely adjusting) the voltage division ratio of the resistor RF1 and the resistor RF2 to enable the numerical values of Y14, Y13, Y12 and Y11 to fluctuate between 1000 and 1001; the second method for adjusting the size of the reference voltage Uref is as follows: uy is the voltage variation range of the differential input high-side IN HOL and the differential input low-side IN LO when the AC power supply voltage fluctuates IN the theoretical range of 174.5V to 244.5V, and there is a voltage variation range

The variation range of Uy corresponds to 10 code values of B12, B11, B10 and B9 output BCD codes, and the change range of Uy is full-scale input and has

Therefore, in this case, it is only necessary to adjust the voltage division ratio between the resistor RF1 and the resistor RF2 so that Uref is equal to the calculated value of equation (2).

In fig. 4, other peripheral component parameters of LTC1966 and ICL7109 can be determined by reading the corresponding device data sheet. Other detection circuits can be used for realizing the sampled value U1 of the AC power supply voltage, other devices can be used for ICL7109, for example, binary codes output by the double-integration A/D converters MAX139, MAX140, ICL7107 and the like are used for replacing ICL7109, and MAX139, MAX140, ICL7107 and the like are 7-segment codes, and the functions of the binary codes are the same as BCD codes output by ICL 7109.

Fig. 5 shows an embodiment 2 of the analog-to-digital conversion coding unit, in which ac power voltages input from a phase line L1 and a neutral line N are stepped down by a transformer TV2, rectified by a rectifier bridge composed of diodes DV1-DV4, filtered by a capacitor CV3, divided by a resistor RV3 and a resistor RV4, and an ac power voltage sampling value U2 in a direct proportional relationship with an effective value of the input ac power voltage is obtained; the resistor RV5 and the voltage regulator tube WV1 form a low-limit threshold voltage circuit, and the voltage on the voltage regulator tube WV1 is a low-limit threshold voltage U2cp corresponding to the low limit value of the alternating-current power supply voltage fluctuation range. The sampled ac supply voltage U2 may also be fed to the differential input high side IN HOL of ICL7109 IN fig. 4, and converted by ICL7109 into a binary voltage level code and output.

In fig. 5, FD3 is a double-integration a/D converter MC14433 for dividing the voltage range of the ac power supply voltage fluctuation interval into voltage level intervals and converting the voltage level intervals into binary voltage level code values for output. In fig. 5, the end-of-conversion output terminal EOC of the MC14433 is connected to the conversion result output control terminal DU, so that it operates in the automatic repeat conversion state; the integrating resistor R14 and the integrating capacitor C14 are connected to the external integral element ends R1, R1/C1 and C1 of the MC 14433; the oscillation resistor R15 is connected to the clock external element terminals CP0 and CP1 of the MC 14433; the compensation capacitor C15 is connected to the external compensation capacitor ends C01 and C02 of the MC 14433; the resistor RF3 and the resistor RF4 divide the voltage of the power supply + VCC, a reference voltage Uref1 is obtained on the resistor RF4, and Uref1 is input to a reference voltage input end VREF; VDD is a positive power supply end of the MC14433 and is connected to a power supply + VCC; VSS is the digital ground and VAG is the analog ground, both connected to common ground.

In FIG. 5, FD4 is a 4-way D latch CD4042, with the 4-bit data input terminals D0-D3 of CD4042 connected to the 4-bit data output terminals Q0-Q3 of MC 14433; the trigger clock input CP of the CD4042 is connected to the hundred-bit strobe signal output DS2 of the MC 14433; the clock polarity control terminal POL of CD4042 is connected to high, the positive power terminal VDD is connected to the power supply + VCC, and the digital ground terminal VSS is connected to the common ground. The CD4042 latches hundred-bit BCD data time-divisionally output after the MC14433 finishes conversion, and the voltage level code value P2 output by the analog-to-digital conversion coding unit consists of data Y14, Y13, Y12 and Y11 output from output ends Q3, Q2, Q1 and Q0 of the CD 4042. CD4042 may be replaced with other latches.

Assuming that the fluctuation range of the input alternating current power supply voltage is 220V ± 10%, the compensation type main circuit embodiment 1 is required to be adopted to stabilize the input alternating current power supply voltage within the range of 220V ± 2% for output, and the fluctuation range of the alternating current power supply voltage is 242V to 198V, at this time, the analog-to-digital conversion coding unit embodiment 2 of fig. 5 is adopted, the voltage input between 242V and 198V can be divided into 7 voltage class intervals with the interval voltage size of 6.4V, wherein the voltage of 3 voltage class intervals is higher than the required output voltage range, and the voltage reduction compensation is required; the voltage of the 3 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out.

In FIG. 5, the input VX of the measured voltage of MC14433 is connected to the output of the sampled value of the AC supply voltage U2, and the low-threshold voltage U2cp is connected to the common ground GND, therefore, MC14433 converts the voltage difference between the sampled value of the AC supply voltage U2 and the low-threshold voltage U2 cp; the actual alternating-current power supply voltage fluctuation interval corresponding to 7 voltage class intervals of 6.4V is 242.4V to 197.6V, and the low-limit threshold voltage U2cp corresponds to a low-limit theoretical value of the alternating-current power supply voltage fluctuation interval range of 197.6V; therefore, when the conversion ratio of the transformer TV2 and the voltage division ratio of the resistor RV3 and the resistor RV4 are lower limit theoretical values of 197.6V, the sampled value U2 of the ac power supply voltage should be equal to the lower limit threshold voltage U2 cp. In fig. 5, the voltage level code value P2 output by the analog-to-digital conversion coding unit is composed of data Y14, Y13, Y12, Y11 output from MC14433 hundreds bits; since it is required to divide the voltage input between 242.4V and 197.6V into 7 voltage class intervals with a class voltage size of 6.4V, and 7 voltage class code values of Y14, Y13, Y12 and Y11, which correspond to the 7 voltage class intervals from low to high one by one, are 0000, 0001, 0010, 0011, 0100, 0101 and 0110, respectively, it is implemented by adjusting the size of the reference voltage U2ref input to the MC 14433. The method for adjusting the size of the reference voltage U2ref is as follows: when the voltage of the alternating current power supply fluctuates up and down at a demarcation voltage 236V of the highest 2 voltage class intervals, the reference voltage is reduced from the maximum value, and the voltage division ratio of the resistor RF3 and the resistor RF4 is adjusted to enable the numerical values of Y14, Y13, Y12 and Y11 to fluctuate between 0110 and 0101; the second method for adjusting the magnitude of the reference voltage U2ref is as follows: let Ux be the voltage variation range of the alternating current power supply voltage when the voltage fluctuates in the theoretical range of 197.6V to 242.4V, and

because the measurement output of the MC14433 is 3-bit half BCD data, corresponding to full-scale input, the thousand bits plus hundred bits have 20 BCD coding values, and the variation range of Ux corresponds to 7 minimum coding values; let the input voltage range of input variation full scale corresponding to 20 BCD code values be Uz, have

The reference voltage of MC14433 is equal to the full-scale input voltage, has

Therefore, at this time, it is only necessary to adjust the voltage division ratio between the resistor RF3 and the resistor RF4 so that U2ref is equal to the calculated value of equation (3).

Assuming that the fluctuation range of the input ac power voltage is 220V + 10% to 220V-20%, it is required to adopt the compensation type main circuit embodiment 2 to stabilize it in the range of 220V ± 2% for output, and the fluctuation range of the ac power voltage is 242V to 176V, at this time, the analog-to-digital conversion coding unit embodiment 2 of fig. 5 is adopted, the voltage input between 242V and 176V can be divided into 10 voltage class intervals with the interval voltage size of 7V, wherein the voltage of 3 voltage class intervals is higher than the required output voltage range, and the voltage reduction compensation is required; the voltage of the 6 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The actual alternating-current power supply voltage fluctuation interval corresponding to 10 voltage class intervals of 7V is 244.5V to 174.5V, and the lower limit threshold voltage U2cp corresponds to the lower limit theoretical value 174.5V of the alternating-current power supply voltage fluctuation interval range; therefore, when the conversion ratio of the transformer TV2 and the voltage division ratio of the resistor RV3 and the resistor RV4 are lower limit theoretical values 174.5V, the sampled value U2 of the ac power supply voltage should be equal to the lower limit threshold voltage U2 cp. In fig. 5, the voltage level code value P2 output by the adc coding unit is composed of data Y14, Y13, Y12, and Y11 output from MC14433 hundreds, and 10 voltage level code values, which are respectively 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, and 1001 corresponding to 10 voltage level intervals from low to high in voltage level, of Y14, Y13, Y12, and Y11 are respectively implemented by adjusting the size of the reference voltage U2 ref. The method for adjusting the size of the reference voltage U2ref is as follows: when the alternating current power supply voltage fluctuates up and down at the boundary of two highest voltage level intervals (namely 237.5V of the alternating current power supply voltage), the reference voltage is reduced from the maximum value, and the voltage division ratio of the resistor RF3 and the resistor RF4 is adjusted to enable the numerical values of Y14, Y13, Y12 and Y11 to fluctuate between 1000 and 1001; the second method for adjusting the magnitude of the reference voltage U2ref is as follows: when Uy is the voltage variation range of the alternating current power supply voltage when the alternating current power supply voltage fluctuates in the theoretical range of 174.5V to 244.5V, the voltage variation range includes

The variation range of Uy corresponds to 10 minimum encoding values in 20 BCD encoding values of MC14433 kbits plus hundred bits; let the input voltage range of full scale of input change corresponding to 20 BCD code values at this time be Uz, have

The reference voltage of MC14433 is equal to the full-scale input voltage, has

Therefore, at this time, it is only necessary to adjust the voltage division ratio between the resistor RF3 and the resistor RF4 so that U2ref is equal to the calculated value of equation (4).

In fig. 5, other peripheral component parameters of MC14433 can be determined by reading the corresponding device data manual. The ac supply voltage sample value U2 may also be implemented using other detection circuits, such as various true valid value detection chips. The difference between the sampled ac supply voltage U2 and the corresponding low threshold voltage may also be obtained by other methods, such as subtracting the corresponding low threshold voltage value from the sampled ac supply voltage U2 using an analog voltage subtractor circuit.

In the above embodiments, when the compensation type main circuit embodiment 1 is used for voltage compensation, and the analog-to-digital conversion coding unit embodiment 1 in fig. 4 or the analog-to-digital conversion coding unit embodiment 2 in fig. 5 is used to divide the voltage input between 242V and 198V into 7 voltage level intervals with the interval voltage size of 6.4V, Y14 is constantly equal to 0 in the voltage level code values composed of Y14, Y13, Y12 and Y11, so that the actual voltage level code value at this time can also be considered to be composed of 3 bits, i.e., Y13, Y12 and Y11, and the 7 voltage level code values corresponding to the voltage level intervals from low to high 7, i.e., Y13, Y12 and Y11, are 000, 001, 010, 011, 100, 101 and 110, respectively.

Fig. 6 is a block diagram of an embodiment of a delay protection unit, wherein a delay detection module YC1 respectively delays input voltage level code values Y14, Y13, Y12, and Y11 to obtain delayed voltage level code values Y24, Y23, Y22, and Y21, and Y23, Y24, Y22, and Y21 form P3; the YC1 module simultaneously and respectively carries out edge detection on Y14, Y13, Y12 and Y11 to obtain edge detection signals Y34, Y33, Y32 and Y31; the no-trigger area control signal generation module YC2 converts the input edge detection signals Y34, Y33, Y32, Y31 into the no-trigger area control signal P4 for output. In the block diagram of the embodiment of fig. 6, the voltage level code values input by the delay detection module YC1 have 4 bits, such as Y14, Y13, Y12, Y11, etc., and K is equal to 4; if K is equal to 3, the voltage level code value inputted by the delay detection module YC1 is composed of 3 bits binary value, for example, when Y13, Y12 and Y11 are included, the voltage level code value after signal delay is performed to obtain delay is only 3 bits such as Y23, Y22 and Y21, the edge detection signal obtained by edge detection on Y13, Y12 and Y11 is only 3 bits such as Y33, Y32 and Y31, and the edge detection signal inputted by the non-trigger area control signal generation module YC2 is only 3 bits such as Y33, Y32 and Y31.

Fig. 7 is a circuit embodiment 1 of the delay detection module for detecting the delay of the voltage level code value signal Y11. The resistor RY0, the capacitor CY0 and the driving gate FY0 realize signal delay of Y11, and a delayed signal Y21 of Y11 is obtained. The resistor RY1, the capacitor CY1, the diode DY1 and the inverter FY1 form a rising edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is output in the output signal YP1 of the inverter FY 1. The resistor RY2, the capacitor CY2, the diode DY2, the inverters FY2 and FY3 constitute a falling edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the falling edge of Y11 is output in the output signal YP2 of the inverter FY 3. The nand gate FY4 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY4, that is, when the input signal Y11 changes, the nand gate FY4 outputs a single pulse in the form of a positive pulse. In fig. 7, the drive gate FY0, inverter FY1, inverter FY3 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; the drive gate FY0 may consist of 2 inverters with schmitt inputs.

Fig. 8 is a circuit embodiment 2 of the delay detection module for detecting the delay of the voltage level code value signal Y11. The inverter FY5, the resistor RY3 and the capacitor CY3 invert and delay the input signal Y11 to obtain a delayed inverted signal YP0 of Y11; the inverter FY6 inverts YP0 to obtain a delayed Y11 signal Y21. The signal input by the nand gate FY7 is a delayed inverted signal YP0 of Y11 and Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is generated in the output signal YP 1; the or gate FY8 receives the inverted signals YP0 of Y11 and Y11, and the output signal YP2 generates a single pulse in the form of a negative pulse corresponding to the falling edge of Y11. The nand gate FY9 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY9, that is, when the input signal Y11 changes, the nand gate FY9 outputs a single pulse in the form of a positive pulse. In fig. 8, inverter FY6, nand gate FY7, or gate FY8 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; nand gate select 74HC132, CD4093, etc.; or gate select 74HC7032 or 2 inverters with schmitt inputs and 1 nand gate to implement the or gate function.

Fig. 9 is a delay detection circuit embodiment 3 of the delay detection module for the voltage level encoded value signal Y11, in which a rising edge detection circuit for the input signal Y11 is composed of a resistor RY1, a capacitor CY1, a diode DY1 and an inverter FY1, and a falling edge detection circuit for the input signal Y11 is composed of a resistor RY2, a capacitor CY2, a diode DY2, an inverter FY2 and an inverter FY3, and a circuit for outputting the edge detection signal Y31 by using the nand gate FY4 is the same as in embodiment 1 of fig. 7. In fig. 9, the signal delay of Y11 is realized by inverters FY11, FY12, FY13, and FY14, and a delayed signal Y21 of Y11 is obtained.

The embodiments 1-3 of fig. 7, 8 and 9 are all delay detection circuits for the signal Y11 in the voltage level code value, and the delay detection circuits for the other signals in the voltage level code value, for example, the delay detection circuits for the input signals Y13 and Y12, and the delay detection circuit for the Y14 in the 4-bit voltage level code value, have the same circuit structure and function as the circuit for performing delay detection for the input signal Y11 in the corresponding embodiments. The delay detection circuit may also adopt other circuits meeting the requirements to realize the functions thereof.

The function of the no-trigger area control signal generation module is to output a single pulse in the no-trigger area control signal when any one or more of the input edge detection signals generate a single pulse related to an edge. Fig. 10 shows an embodiment of the no-trigger area control signal generation module, where the or gate FY10 implements the corresponding function, and the input signals of the or gate FY10 are edge detection signals Y34, Y33, Y32, and Y31, and the output signal is a no-trigger area control signal P4. In the embodiment of fig. 10, the single pulse not triggering the output of the zone control signal is a positive pulse, i.e. the high level of the zone control signal is not activated; when the or gate FY10 is replaced by a nor gate, the single pulse that does not trigger the output of the zone control signal is a negative pulse, and the low level of the zone control signal is active. If the single pulse associated with an edge generated in the input edge detection signals Y34, Y33, Y32 and Y31 is a negative pulse, the or gate in fig. 10 should be changed to a nand gate or an and gate to implement a negative logic or logic function. If the input edge detection signal has only 3 bits, for example, only the edge detection signals Y33, Y32, and Y31, the or gate in fig. 10, or other gates for implementing the function of the trigger zone free control signal generation module, such as nor gate, nand gate, and gate, etc., is also a 3-input gate circuit accordingly.

Fig. 11 is a schematic diagram of a partial correlation waveform in the delay protection unit. In fig. 11, Y11 among the voltage level code values undergoes a rising edge change and a falling edge change, respectively, and Y21 is the voltage level code value of Y11 delayed by T1 time; in embodiment 1 of the delay detection circuit in fig. 7, T1 is determined by the magnitude of the product of the resistor RY0 and the capacitor CY0 (i.e., the magnitude of the time constant); in embodiment 2 of the delay detection circuit in fig. 8, T1 is determined by the product of the resistor RY3 and the capacitor CY 3; in the embodiment 3 of the delay detection circuit in fig. 9, T1 is determined by the gate delay time of the inverters FY11, FY12, FY13 and FY 14. In fig. 11, the negative pulse width of the signal YP1 due to the rising edge of Y11 is T2; in the delay detection circuit embodiment 1 of fig. 7 and the delay detection circuit embodiment 3 of fig. 9, T2 is determined by the magnitude of the product of the resistor RY1 and the capacitor CY 1; in embodiment 2 of the delay detection circuit in fig. 8, T2 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 11, the negative pulse width generated by the falling edge of Y11 in the signal YP2 is T3; in the delay detection circuit embodiment 1 of fig. 7 and the delay detection circuit embodiment 3 of fig. 9, T3 is determined by the magnitude of the product of the resistor RY2 and the capacitor CY 2; in embodiment 2 of the delay detection circuit in fig. 8, T3 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 11, 2 positive pulses in the edge detection signal Y31 correspond to a negative pulse due to a rising edge of Y11 in the signal YP1 and a negative pulse due to a falling edge of Y11 in the signal YP2, respectively. When Y11 in the voltage level code value of fig. 11 is changed in rising edge, Y12, Y13 and Y14 in the voltage level code value are not changed, and the corresponding edge detection signals Y32, Y33 and Y34 do not generate positive pulses; when Y11 is changed by a falling edge, Y12 in the voltage level code value is changed at the same time, Y13 and Y14 are not changed, and a positive pulse related to Y12 change is generated in the corresponding edge detection signal Y32; since Y33 and Y34 remain at the low level, they are not shown in fig. 11. According to the logic function of the non-trigger area control signal generation module, the width of the single pulse output by the non-trigger area control signal generation module is the same as the widest pulse width of the input pulses which jointly generate the single pulse in the input edge detection signals. In FIG. 11, the 1 st positive pulse in the non-trigger area control signal P4 is generated by the 1 st negative pulse in the edge detection signal Y31, and the widths of the two pulses are the same; the 2 nd positive pulse in the no-trigger-zone control signal P4 is generated by the influence of the 2 nd negative pulse in the edge detection signal Y31 and the negative pulse in the edge detection signal Y32, and has the same width as the negative pulse with the widest width among the 2 negative pulses generating the positive pulse; as can be seen from fig. 11, the negative pulse width in Y32 is wide, and the 2 nd positive pulse width in P4 is the same as the negative pulse width in Y23. The width difference is caused by the difference between the resistance and capacitance values of T2 and T3 determined in different delay detection circuits.

In the embodiment 1 of the delay detection circuit in the delay protection unit of fig. 7, the delay time for the voltage level code value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY1 and FY4 and FY10 in fig. 10, or the sum of the delay times of the gates FY3 and FY4 and FY10 in fig. 10; the selection range of the signal delay time T1 of the voltage level code value determined by the product of the resistor RY0 and the capacitor CY0 is ms order of magnitude, obviously, is greater than the delay time of the voltage level code value changing to the leading edge of the single pulse of the corresponding non-trigger area control signal, that is, the time of the delay change of the level code value signal is later than the leading edge time of the single pulse output after the voltage level code value changes. Strictly speaking, T1 actually includes the sum of the delay time caused by resistor RY0 and capacitor CY0, and the delay time of gate FY 0. In embodiment 1 of fig. 7, when selecting the parameters, the value of T2 and the value of T3 are both made to be greater than the value of T1, so that the timing at which the gradation code value signal changes with a delay meets the requirement that the timing of the trailing edge of the output single pulse be earlier than the timing at which the voltage gradation code value changes.

In the embodiment 2 of the delay detection circuit in the delay protection unit of fig. 8, the delay time for the voltage level code value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY7 and FY9 and FY10 in fig. 10, or the sum of the delay times of the gates FY8 and FY9 and FY10 in fig. 10; t1 is a value of ms magnitude, and it is obvious that the signal delay time T1 of the voltage level code value determined by the product of the resistor RY3 and the capacitor CY3 is longer than the delay time of the voltage level code value changing to the leading edge of the corresponding single pulse of the no-trigger-zone control signal, i.e. the time of the delay change of the voltage level code value signal is later than the time of the leading edge of the single pulse output after the voltage level code value changes. In the embodiment 2 of the delay detection circuit in fig. 8, both the time when the voltage level code value signal changes in delay and the time when the trailing edge of the output single pulse after the voltage level code value changes are affected by the change of the signal YP 0; the time when the voltage level code value signal delay changes is the delay of the gate circuit FY6 after the signal YP0 changes; the trailing edge time of the single pulse output after the voltage level code value is changed is the sum of the delay time of the gate circuits FY7 and FY9 after the signal YP0 is changed and FY10 in FIG. 10, or the sum of the delay time of the gate circuits FY8 and FY9 after the signal YP0 is changed and FY10 in FIG. 10; obviously, the time of the delay change of the voltage level code value signal is less than the time of the trailing edge of the output single pulse after the voltage level code value is changed by 2 gate circuits, and the requirement that the time of the delay change of the voltage level code value signal is earlier than the time of the trailing edge of the output single pulse after the voltage level code value is changed is met.

Fig. 12 shows an example of an interlock control unit, and fig. 12(a) shows an interlock control unit example 1 in which YR1 is a ROM memory. In the embodiment 1 of the compensation type main circuit in fig. 2, the compensation voltage of TB1 is low, and the compensation voltage of TB2 is high; and the compensation voltage of TB2 is 2 times the compensation voltage of TB 1. Table 1 is a logic truth table for performing compensation control by using the compensation main circuit embodiment 1 of fig. 2, and dividing the power supply voltage into 7 voltage level intervals by using the adc embodiment 1 of fig. 4 or the adc embodiment 2 of fig. 5, and performing logic control when 7 voltage level code values are formed by Y13, Y12, and Y11, or by delayed Y23, Y22, and Y21; the fluctuation range of the alternating current power supply voltage is 220V +/-10%, and the alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. When the logic function of the interlocking control unit is realized by adopting a ROM, P4 and Y23-Y21 are respectively connected to the address input ends A3-A0 of the ROM in sequence, the data outputs D0-D5 of the ROM are the logic outputs of the interlocking control unit, and 6 output signals P51-P56 form a trigger control signal P5. In table 1, when the trigger zone control signal is not valid, P4 is equal to 0, and the voltage level code value is a value corresponding to the voltage level 1-7, the interlock control unit controls the compensated main circuit embodiment 1 to perform corresponding voltage compensation; for example, when the input voltage is the lowest voltage level 1, the outputs of the P51, the P54 and the P56 are controlled to be 0 to turn on the bidirectional thyristors SR1, SR4 and SR6, and the outputs of the P52, the P53 and the P55 are controlled to be 1 to turn off the bidirectional thyristors SR2, SR3 and SR5, so that both TB1 and TB2 are subjected to forward compensation; when the input voltage is in a voltage level 2, controlling the outputs of P51, P53 and P56 to be 0 to turn on the bidirectional thyristors SR1, SR3 and SR6, controlling the outputs of P52, P54 and P55 to be 1 to turn off the bidirectional thyristors SR2, SR4 and SR5, and only enabling TB2 to carry out forward compensation; when the input voltage is at a voltage level of 4, controlling the outputs of P51, P53 and P55 to be 0 to turn on the bidirectional thyristors SR1, SR3 and SR5, and controlling the outputs of P52, P54 and P56 to be 1 to turn off the bidirectional thyristors SR2, SR4 and SR6, so as to realize 0 voltage compensation, namely, both TB1 and TB2 are not compensated; when the input voltage is in a voltage level of 5, controlling the outputs of P52, P53 and P56 to be 0 to turn on the bidirectional thyristors SR2, SR3 and SR6, controlling the outputs of P51, P54 and P55 to be 1 to turn off the bidirectional thyristors SR1, SR4 and SR5, and only enabling TB1 to carry out reverse compensation; and so on. When P4 is equal to 1, it indicates that there is fluctuation in AC power voltage, and the voltage level code value changes, and it needs to switch the electronic switch to change the compensation mode. In the switching process of the electronic switch, in order to avoid the short circuit of the power supply caused by the factor of delayed turn-off of the electronic switch when the upper and lower bridge arms in the thyristor bridge are switched, all the bidirectional thyristors in the thyristor bridge are turned off during the period when the trigger zone control signal is not active, i.e. when P4 in the embodiment is equal to 1, and the interlocking control unit controls all the P51-P56 to output 1.

TABLE 1

In Table 1, M is equal to 7. When the control signal of the non-trigger area is invalid (P4 is equal to 0), the valid code values of 7 voltage level code values P3 correspond to 7 groups of valid trigger control signals, and accordingly control of 7 voltage compensation states is realized; when the P2 is changed to make P4 active (P4 equals 1), 1 group of active trigger control signals are corresponded, and the interlock control unit outputs 8 groups of active trigger control signals in total. When P4 is invalid (P4 is equal to 0) and the voltage level code value P3 inputted by the interlock control unit is an invalid code value, the interlock control unit corresponds to 1 specific group of invalid trigger control signals. With the analog-to-digital conversion coding unit embodiment 1 in fig. 4 or the analog-to-digital conversion coding unit embodiment 2 in fig. 5, the power supply voltage is divided into 7 voltage level intervals, valid code values of 7 voltage level code values are output by Y13, Y12, and Y11, and only 1 invalid code value may be output by Y13, Y12, Y11 or Y23, Y22, and Y21, which is 111. In Table 1, the 1 specific set of disable trigger control signals causes the P51 output to be 0 and the P52-P56 outputs to be 1; the specific invalid trigger control signal does not actually control the thyristor, and only makes the excitation coils of TB1 and TB2 connected with a zero line N and the excitation voltage 0 without performing voltage compensation even if the trigger control function of the thyristor is performed; the 1 specific inactive trigger control signal may also select other trigger combinations that are not voltage compensated, for example, such that the P53 output is 0 and the other outputs are 1.

In table 1, the trigger control signal output by the interlock control unit triggers the triac to be active at a low level when it is turned on. If the trigger control signal output by the interlocking control unit requires that the high level is effective when the trigger bidirectional thyristor is conducted, 1 in the output signal of the logic truth table in the table 1 needs to be changed into 0, and 0 needs to be changed into 1; when the function is realized by a ROM, the content of the memory cell is inverted according to Table 1.

Fig. 12(b) shows an interlock control unit embodiment 2 in which YR2 is a ROM memory. In the compensated main circuit embodiment 2 of fig. 3, the TB1 compensation voltage is the lowest, and the TB3 compensation voltage is the highest; and the compensation voltage of TB2 is 2 times of the compensation voltage of TB1, and the compensation voltage of TB3 is 2 times of the compensation voltage of TB 2. Table 2 is a logic truth table for performing compensation control by using the compensation main circuit embodiment 2 of fig. 3, and dividing the power supply voltage into 10 voltage level intervals by using the adc embodiment 1 of fig. 4 or the adc embodiment 2 of fig. 5, and performing logic control when 10 voltage level code values are formed by Y14, Y13, Y12, and Y11, or by delayed Y24, Y23, Y22, and Y21; the fluctuation range of the alternating current power supply voltage is 220V + 10% to 220V-20%, and the alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. When the ROM YR2 is adopted to realize the logic function, inputs P4 and Y24-Y21 are respectively connected to address terminals A4-A0 of the ROM in sequence, data outputs D0-D7 of the ROM are the logic outputs of the interlocking control unit, and 8 output signals P51-P58 form a trigger control signal P5. In table 2, when the trigger zone control signal is not valid, P4 is equal to 0, and the voltage level code value is a value corresponding to the voltage level 1-10, the interlock control unit controls the compensated main circuit embodiment 2 to perform the corresponding voltage compensation; for example, when the input voltage is at voltage level 7, the outputs of the P51, P53, P55 and P57 are controlled to be 0 to turn on the triacs SR1, SR3, SR5 and SR7, and the outputs of the P52, P54, P56 and P58 are controlled to be 1 to turn off the triacs SR2, SR4, SR6 and SR8, so that 0 voltage compensation is realized, that is, none of the TB1, TB2 and TB3 is compensated; when the input voltage is at a voltage level of 8, controlling the outputs of P52, P53, P56 and P58 to be 0 to turn on the bidirectional thyristors SR2, SR3, SR6 and SR8, and controlling the outputs of P51, P54, P55 and P57 to be 1 to turn off the bidirectional thyristors SR1, SR4, SR5 and SR7, so that TB1 is reversely compensated; when the input voltage is in a voltage level 9, controlling the outputs of P52, P54, P55 and P58 to be 0 to turn on the bidirectional thyristors SR2, SR4, SR5 and SR8, and controlling the outputs of P51, P53, P56 and P57 to be 1 to turn off the bidirectional thyristors SR1, SR3, SR6 and SR7, so that TB2 is reversely compensated; when the input voltage is in a voltage level of 10, controlling the outputs of P52, P53, P55 and P58 to be 0 to turn on the bidirectional thyristors SR2, SR3, SR5 and SR8, and controlling the outputs of P51, P54, P56 and P57 to be 1 to turn off the bidirectional thyristors SR1, SR4, SR6 and SR7, so that TB1 and TB2 perform reverse compensation at the same time; when the input voltage is in a voltage level 6, controlling the outputs of P51, P54, P55 and P57 to be 0 to turn on the bidirectional thyristors SR1, SR4, SR5 and SR7, and controlling the outputs of P52, P53, P56 and P58 to be 1 to turn off the bidirectional thyristors SR2, SR3, SR6 and SR8 so as to enable TB1 to carry out forward compensation; when the input voltage is in a voltage level 4, controlling the outputs of P51, P54, P56 and P57 to be 0 to turn on the bidirectional thyristors SR1, SR4, SR6 and SR7, and controlling the outputs of P52, P53, P55 and P58 to be 1 to turn off the bidirectional thyristors SR2, SR3, SR5 and SR8, so that TB1 and TB2 perform forward compensation at the same time; when the input voltage is in a voltage class 3, controlling the outputs of P51, P53, P55 and P58 to be 0 to turn on the bidirectional thyristors SR1, SR3, SR5 and SR8, and controlling the outputs of P52, P54, P56 and P57 to be 1 to turn off the bidirectional thyristors SR2, SR4, SR6 and SR7 so as to enable TB3 to carry out forward compensation; when the input voltage is in a voltage level 1, controlling the outputs of P51, P53, P56 and P58 to be 0 to turn on the bidirectional thyristors SR1, SR3, SR6 and SR8, and controlling the outputs of P52, P54, P55 and P57 to be 1 to turn off the bidirectional thyristors SR2, SR4, SR5 and SR7, so that TB2 and TB3 perform forward compensation at the same time; and so on. When the control signal of the non-trigger area is effective, when the P4 is equal to 1, the fluctuation of the alternating current power supply voltage is shown, the voltage level code value is changed, the electronic switch is required to be switched, the compensation mode is changed, all the bidirectional thyristors in the thyristor bridge are switched off at the moment, and the interlocking control unit controls the P51-P58 to output 1 completely.

TABLE 2

In Table 2, M is equal to 10. When the control signal of the non-trigger area is invalid (P4 is equal to 0), the valid code values of 10 voltage level code values P3 correspond to 10 groups of valid trigger control signals, and accordingly control of 10 voltage compensation states is realized; when the change in P2 makes P4 active (P4 equal to 1), there are 1 active set of trigger control signals, and the interlock control unit has 11 active set of trigger control signals. When the P4 is invalid (P4 is equal to 0) and the voltage level code value P3 input by the interlock control unit is an invalid code value, the interlock control unit corresponds to 1 group of specific invalid trigger control signals; with the analog-to-digital conversion coding unit embodiment 1 of fig. 4 or the analog-to-digital conversion coding unit embodiment 2 of fig. 5, the power supply voltage is divided into 10 voltage level intervals, the voltage level code values composed of Y14, Y13, Y12, and Y11 output valid code values of 10 voltage level code values in total, and the 4-bit voltage level code values Y14, Y13, Y12, and Y11, or Y24, Y23, Y22, and Y21 may also have outputs of 6 invalid code values, all of which enable the interlock control unit to output the same 1 set of invalid trigger control signals; in table 2, the 1 group of specific invalid trigger control signals make the P51 output 0, the P52-P58 output 1, the excitation coils of TB1, TB2 and TB3 connected to the zero line N and the excitation voltage 0, and no voltage compensation is performed; the 1 specific inactive trigger control signal may also select other trigger combinations that are not voltage compensated, for example, such that the P53 output is 0 and the other outputs are 1.

In table 2, the trigger control signal output by the interlock control unit triggers the triac to be active at a low level when it is turned on. If the trigger control signal output by the interlock control unit requires that the high level is effective when the trigger bidirectional thyristor is conducted, 1 in the output signal of the logic truth table in the table 2 needs to be changed into 0, and 0 needs to be changed into 1; when the function is realized by a ROM memory, the contents of the memory cells are inverted according to table 2.

The combinational logic functions in table 1 or the truth table of table 2 can be implemented by other means besides ROM memory.

Fig. 13 shows an embodiment of a trigger circuit for triggering the triac SR1 in the trigger unit, which is composed of an ac trigger optocoupler UG1, a resistor RG1, and a resistor RG2, and the trigger control signal P51 is active at low level. The alternating current trigger optocoupler UG1 can be selected from phase-shifting bidirectional thyristor output optocouplers such as MOC3021, MOC3022, MOC3023, MOC3051, MOC3052 and MOC 3053. Power supply + VCCK is the controlled power supply controlled by the error detection control unit. The circuit structure of the trigger circuit for triggering the triacs SR2-SR6 in the compensated main circuit embodiment 1 in FIG. 2 or the triacs SR2-SR8 in the compensated main circuit embodiment 2 in FIG. 3 is the same as that of the triac SR 1. The trigger pulses output by the alternating current trigger optocoupler UG1 in fig. 13 from G11 and G12 and the trigger pulses output by other alternating current trigger optocouplers in the trigger unit jointly form a trigger signal P6.

FIG. 14 shows an embodiment of an error detection control unit, wherein YR3 is a ROM memory, and the ROM memory constitutes a determination module for determining whether the input trigger control signal P5 is a valid trigger control signal; the triode VT, the triode VK1, the triode VK2, the relay coil KA, the freewheeling diode VD, the resistor RK1, the resistor RK2 and the resistor RK3 form a protection control circuit. + VCC2 is the power supply for the relay coil and the source for the trigger unit controlled power supply.

The error detection control unit in the embodiment of fig. 14 is used to determine the trigger control signal sent by the interlock control unit in the embodiment 1 in fig. 12(a), and table 3 is a logic truth table for determining whether the trigger control signal sent by the interlock control unit in the embodiment 1 is a valid trigger control signal.

When the trigger control signal sent by the interlock control unit embodiment 1 is 1 of 8 effective trigger control signals listed in the front 8 rows in table 3, the trigger control determination signal output by the determination module is effective, that is, P7 is 1, which indicates that the trigger control signal is an effective trigger control signal, the triodes VK1 and VK2 are turned on, the controlled power supply + VCCK is powered on, and the trigger unit normally operates and sends a corresponding trigger pulse according to the trigger control signal. The P7 is 1, and simultaneously controls the conduction of the triode VT, the relay coil KA is electrified, so that the normally open switches KA-1, KA-2 and KA-3 of the relay in the embodiment 1 of the compensation type main circuit in fig. 2 are closed, the normally closed switches KA-5 and KA-6 of the relay are opened, and the thyristor bridge is in a compensation working state. When the trigger control signal sent by the interlock control unit embodiment 1 is other signals, and is not any 1 of the 8 groups of valid trigger control signals listed in the front 8 rows in table 3, the trigger control determination signal output by the determination module is invalid, i.e., P7 is 0, the triodes VK1 and VK2 are turned off, the controlled power supply + VCCK is powered off, and the trigger unit does not work, i.e., does not send the trigger pulse for triggering the thyristor. P7 is 0, and simultaneously the triode VT is controlled to be cut off, and the relay coil KA loses power, so that normally open switches KA-1, KA-2 and KA-3 of the relay in the embodiment 1 of the compensation type main circuit in the figure 2 are disconnected, and the open circuit protection of a thyristor bridge is realized; normally closed switches KA-5 and KA-6 of the relay are controlled to be closed, so that the voltage applied to excitation coils TB1 and TB2 is 0. When the input of the interlocking control unit embodiment 1 is an invalid code value and outputs an invalid trigger control signal, as can be seen from table 3, the output of the discrimination module is also 0, so as to realize open-circuit protection of the thyristor bridge; therefore, no matter an invalid code value is output due to the fact that the analog-to-digital conversion coding unit has a coding error fault, or an invalid trigger control signal is output due to the fact that the interlocking control unit has a control error, the error detection control unit starts to carry out open-circuit protection on the thyristor bridge. When the logic truth table in table 3 is implemented by using a ROM memory, the address input of the ROM memory needs 6 bits, i.e., a0-a5 in table 3, and is correspondingly connected with input signals P51-P56; the data output of the ROM memory requires 1 bit, d0 in table 3, corresponding to the control signal P7 of the connection output.

TABLE 3

When the error detection control unit needs to determine the trigger control signal sent by the interlock control unit in embodiment 2 in fig. 12(b), table 4 is a logic truth table for determining whether the trigger control signal sent by the interlock control unit in embodiment 2 is a valid trigger control signal.

When the trigger control signal sent by the interlock control unit embodiment 2 is 1 of the 11 effective trigger control signals listed in the front 11 rows in table 4, the trigger control determination signal output by the determination module is effective, that is, P7 is 1, which indicates that the trigger control signal is an effective trigger control signal, the triodes VK1 and VK2 are turned on, the controlled power supply + VCCK is powered on, and the trigger unit normally operates and sends a corresponding trigger pulse according to the trigger control signal. P7 is 1, and controls normally open switches KA-1, KA-2, KA-3 and KA-4 of the relay in embodiment 2 of the compensation type main circuit of the 3 to be closed, and normally closed switches KA-5, KA-6 and KA-7 of the relay to be opened, so that the thyristor bridge is in a compensation working state. When the trigger control signal sent by the interlock control unit embodiment 2 is other signals, and is not any 1 of the 11 groups of valid trigger control signals listed in the front 11 rows in table 4, the trigger control determination signal output by the determination module is invalid, i.e., P7 is 0, the triodes VK1 and VK2 are turned off, the controlled power supply + VCCK is powered off, and the trigger unit does not operate, i.e., does not send the trigger pulse for triggering the thyristor. P7 is 0, and normally open switches KA-1, KA-2, KA-3 and KA-4 of the relay in embodiment 2 of the compensation type main circuit of the 3 are controlled to be disconnected, so that open-circuit protection of a thyristor bridge is realized; the normally closed switches KA-5, KA-6 and KA-7 of the relays are controlled to be closed, so that the voltage applied to the excitation coils TB1, TB2 and TB3 is 0. When the input of the interlocking control unit embodiment 2 is an invalid code value and outputs an invalid trigger control signal, as can be seen from table 4, the output of the discrimination module is 0, so as to realize open-circuit protection of the thyristor bridge; similarly, no matter the analog-to-digital conversion coding unit outputs an invalid coding value due to a coding error fault or the interlocking control unit outputs an invalid trigger control signal due to a control error, the error detection control unit starts to perform open-circuit protection on the thyristor bridge.

TABLE 4

When the logic truth table of table 4 is implemented by ROM memory, for example, the embodiment of fig. 14 is used to implement the function of error detection control unit, the address input of ROM memory YR3 in fig. 14 needs to be expanded to 8 bits, i.e., the address input needs a0-a7, corresponding to the connection input signals P51-P58; the data output of the ROM memory requires 1 bit, d0 in table 4, corresponding to the control signal P7 of the connection output. When the error detection control unit judges that the input trigger control signal is not an effective trigger control signal, the error detection control unit sends a protection control signal to the compensation type main circuit, so that the thyristor bridge is in an open circuit protection state, the single-phase alternating current voltage stabilizer does not compensate the input voltage, and the voltage output by the voltage stabilizer is the input alternating current power supply voltage. When the thyristor bridge is in the open-circuit protection state, if the error detection control unit judges that the input trigger control signal is recovered to be the effective trigger control signal, the error detection control unit automatically stops the open-circuit protection state of the thyristor bridge, and the thyristor bridge is in the compensation working state again.

The combinational logic functions in table 3 or the truth table of table 4 can be implemented by other means besides ROM memory.

As can be seen from the above embodiments and the working process thereof, as long as the error detection control unit determines that the input trigger control signal is not an effective trigger control signal, that is, the trigger control signal is invalid, the thyristor bridge is started and is in an open-circuit protection state while the trigger pulse for triggering the thyristor is not sent out; when the interlocking control unit outputs the invalid trigger control signal, the error detection control unit starts the interlocking control unit and enables the thyristor bridge to be in an open-circuit protection state; when the thyristor bridge is in the open-circuit protection state, if the error detection control unit judges that the single-phase alternating-current voltage stabilizer enters the normal logic control state again, namely the error detection control unit judges that the input trigger control signal is recovered to be the effective trigger control signal, the open-circuit protection state of the thyristor bridge can be automatically stopped and the thyristor bridge is enabled to be in the compensation working state again. The function effectively strengthens the protection force of the single-phase alternating current voltage stabilizer against the abnormity of the working process, so that the single-phase alternating current voltage stabilizer is more reliable to work.

In the above embodiments, all ROM memories, logic gates and logic function integrated circuits are powered by a positive single power supply + VCC. Other techniques for single-phase ac regulators are conventional in the art, except for the features described in the specification.

Claims

1. A single-phase ac regulator, comprising:

the device comprises a compensation type main circuit, an analog-to-digital conversion coding unit, a delay protection unit, an interlocking control unit, a trigger unit and an error detection control unit;

the compensation type main circuit comprises a compensation transformer bank, a thyristor bridge and a relay protection switch; the analog-to-digital conversion coding unit samples the voltage of the alternating current power supply and outputs a voltage grade coding value after analog-to-digital conversion; the delay protection unit inputs a voltage grade coding value and outputs a delayed voltage grade coding value and a non-trigger area control signal; the interlocking control unit inputs the delayed voltage grade code value and the control signal of the non-trigger area and outputs a trigger control signal; the trigger unit controls the on-off of a thyristor in a thyristor bridge of the main circuit according to an input trigger control signal; the error detection control unit starts/stops the open-circuit protection of the thyristor bridge according to whether the input trigger control signal is wrong or not;

controlling the control signal of the non-trigger area to output a single pulse after the voltage level code value is changed; the control signal of the non-trigger area is effective in the period of outputting the single pulse and is ineffective in the period of not outputting the single pulse;

in the time delay protection unit, the delayed voltage level code value signal change time is later than the leading edge time of a single pulse in the non-trigger area control signal after the voltage level code value is changed and is earlier than the trailing edge time of the single pulse in the non-trigger area control signal after the voltage level code value is changed;

the voltage level code values are M effective code values, and the effective trigger control signals output by the interlocking control unit are M +1 groups; m is greater than or equal to 2;

m groups in the effective M +1 groups of trigger control signals are used for realizing compensation control of alternating current power supply voltage, and 1 group is used for turning off all thyristors in a thyristor bridge;

when the control signal of the non-trigger area is effective, the interlocking control unit outputs an effective trigger control signal for turning off all thyristors in all thyristor bridges; when the control signal of the non-trigger area is invalid, the interlocking control unit outputs an effective trigger control signal corresponding to the voltage grade code value to realize the compensation control of the alternating current power supply voltage;

when the control signal of the non-trigger area input by the interlocking control unit is effective, the interlocking control unit outputs 1 group of effective trigger control signals for turning off all thyristors in the thyristor bridge; when the control signal of the non-trigger area input by the interlocking control unit is invalid and the input voltage level code value is 1 of the M effective code values, correspondingly outputting 1 group of the M groups of effective trigger control signals for realizing the compensation control of the alternating current power supply voltage; when the control signal of the non-trigger area input by the interlocking control unit is invalid and the input voltage level code value is an invalid code value, outputting 1 group of invalid trigger control signals;

the error detection control unit judges whether the input trigger control signal is wrong according to the condition that the trigger control signal is correct when the input trigger control signal is 1 group in the M +1 group effective trigger control signals, or else, the trigger control signal is wrong;

when the error detection control unit judges that the input trigger control signal is wrong, the thyristor bridge is controlled to be in an open-circuit protection state.

2. The single-phase ac voltage regulator according to claim 1, wherein: when the thyristor bridge is in an open-circuit protection state, the error detection control unit automatically stops the open-circuit protection state of the thyristor bridge when judging that the input trigger control signal is recovered to a correct signal.

3. The single-phase ac voltage regulator according to claim 1, wherein: the delay protection unit consists of a delay detection module and a non-trigger area control signal generation module; the delay detection module comprises K identical delay detection circuits, each delay detection circuit delays an input signal to obtain a delayed output signal, and simultaneously performs edge detection on the input signal to output an edge detection signal; the K delay detection circuits respectively delay the K-bit voltage level code value to obtain a delayed K-bit voltage level code value, and perform edge detection on the K-bit voltage level code value to obtain K edge detection signals; the non-trigger area control signal generation module converts the input K edge detection signals into non-trigger area control signals and outputs the non-trigger area control signals.

4. The single-phase ac voltage regulator according to claim 3, wherein: each of the K identical delay detection circuits comprises a resistor RY3, a capacitor CY3, an inverter FY5, an inverter FY6, a nand gate FY7, an or gate FY8, and a nand gate FY 9; the input end of the inverter FY5 is connected to the input signal end; one end of the resistor RY3 is connected to the output end of the inverter FY5, and the other end of the resistor RY3 is respectively connected to one end of the capacitor CY3, one input end of the NAND gate FY7, one input end of the OR gate FY8 and the input end of the inverter FY 6; the other end of the capacitor CY3 is connected to the ground, the other input end of the NAND gate FY7 is connected to the input signal end, and the other input end of the OR gate FY8 is connected to the input signal end; 2 input ends of the NAND gate FY9 are respectively connected to the output end of the NAND gate FY7 and the output end of the OR gate FY 8; the output end of the inverter FY6 is a delayed output signal end; the output end of the NAND gate FY9 is an edge detection signal output end.

5. The single-phase ac voltage regulator according to claim 3, wherein: the no-trigger area control signal generation module is an OR gate FY10 with K input signal terminals; k input signal ends of the OR gate FY10 are respectively connected to edge detection signal output ends of the K delay detection circuits; the output of or gate FY10 outputs a no trigger area control signal.