Detailed Description
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a block diagram of a system of an auto-coupling compensation type AC voltage stabilizer, in which an analog-to-digital conversion coding unit samples voltage of an AC power supply and outputs a voltage level code value P2 after analog-to-digital conversion; the delay protection unit inputs a voltage level code value P2 and outputs a delayed voltage level code value P3 and a non-trigger area control signal P4; the interlock control unit inputs the delayed voltage level code value P3 and the non-trigger area control signal P4 and outputs a trigger control signal P5; the trigger unit sends a trigger signal P6 to the self-coupling compensation type main circuit according to an input trigger control signal P5 to control the on-off of a thyristor in the thyristor switch group; the error detection control unit judges whether the input trigger control signal P5 is an effective trigger control signal or not, and sends a protection control signal to the self-coupling compensation type main circuit according to the judgment result to protect the thyristor switch group.
Fig. 2 is an embodiment 1 of the self-coupling compensation type main circuit, which comprises a compensation transformer TB1 and a self-coupling transformer TB2, wherein 6 bidirectional thyristors SR1-SR6 jointly form a thyristor switch group, and a fuse FU1, a relay normally-open switch KA-1 and a relay normally-closed switch KA-2 form a relay protection circuit.
In fig. 2, the compensation coil of the compensation transformer TB1 is connected in series to the phase line, where the input end of the phase line is L1 and the output end is L2. The voltage on the excitation coil of TB1 is controlled by the thyristor switch group. The autotransformer TB2 is provided with 3 output taps C1, C2 and C3, one ends of bidirectional thyristors SR1, SR3 and SR5 are connected in parallel and then connected to one end of a TB1 excitation coil, and the other ends of SR1, SR3 and SR5 are connected to taps C1, C2 and C3 respectively; one ends of the bidirectional thyristors SR2, SR4 and SR6 are connected in parallel and then connected to the other end of the excitation coil of TB1, and the other ends of SR2, SR4 and SR6 are respectively connected to taps C1, C2 and C3. The output voltage U12 between a tap C1 and a tap C2 of the autotransformer TB2 is different from the output voltage U23 between the tap C2 and the tap C3, so that the thyristor switch group has 6 excitation coil voltage compensation working states of a forward direction U12, a forward direction U23, a forward direction U12+ U23, a reverse direction U12, a reverse direction U23 and a reverse direction U12+ U23 at most, a0 voltage compensation working state when the input voltage is within a normal range is applied, and the alternating current power supply voltage input by the phase line input end L1 can be divided into 7 voltage intervals at most for compensation control. In fig. 2, N is a zero line, and G11, G12 to G61, and G62 are trigger signal input ends of the triacs SR1 to SR6, respectively. In fig. 2, the bidirectional thyristors SR1, SR3, and SR5 constitute the same-side thyristor, and the bidirectional thyristors SR2, SR4, and SR6 constitute the other same-side thyristor; in order to avoid short circuit, 2 or more than 2 thyristors in the thyristors at the same time can not be conducted simultaneously; for example, SR1, SR3 cannot be turned on simultaneously, SR4, SR6 cannot be turned on simultaneously, and so on.
FIG. 3 shows an embodiment 2 of the auto-coupling compensation type main circuit, which includes a compensation transformer TB1 and an auto-coupling transformer TB2, 8 bidirectional thyristors SR1-SR8 jointly form a thyristor switch group, and a fuse FU1, a relay normally-open switch KA-1 and a relay normally-closed switch KA-2 form a relay protection circuit.
In fig. 3, the compensation coil of the compensation transformer TB1 is connected in series to the phase line, where the input end of the phase line is L1 and the output end is L2. The voltage on the excitation coil of TB1 is controlled by the thyristor switch group. The autotransformer TB2 is provided with 4 output taps C1, C2, C3 and C4, one ends of the bidirectional thyristors SR1, SR3, SR5 and SR7 are connected in parallel and then connected to one end of a TB1 excitation coil, and the other ends of the SR1, SR3, SR5 and SR7 are respectively connected to the taps C1, C2, C3 and C4; one ends of the bidirectional thyristors SR2, SR4, SR6 and SR8 are connected in parallel and then connected to the other end of the excitation coil of TB1, and the other ends of the SR2, SR4, SR6 and SR8 are respectively connected to the taps C1, C2, C3 and C4. When the output voltage U12 between taps C1 and C2, the output voltage U23 between C2 and C3, and the output voltage U34 between C3 and C4 of the autotransformer TB2 are different, the thyristor switch group includes 12 excitation coil voltage compensation operating states including a forward U12, a forward U23, a forward U34, a forward U12+ U23, a forward U23+ U34, a forward U12+ U23+ U34, a reverse U12, a reverse U23, a reverse U34, a reverse U12+ U23, a reverse U23+ U34, and a reverse U12+ U23+ U34, and when an input voltage is within a normal range, the 0 voltage compensation operating state is applied, and the ac power supply voltage input at the phase line input terminal L1 can be divided into at most 13 voltage intervals for compensation control. In fig. 3, N is a zero line, and G11, G12 to G81, and G82 are trigger signal input terminals of the triacs SR1 to SR8, respectively. In fig. 3, the bidirectional thyristors SR1, SR3, SR5 and SR7 constitute the same-side thyristor, and the bidirectional thyristors SR2, SR4, SR6 and SR8 constitute the other same-side thyristor; in order to avoid short circuit, 2 or more than 2 thyristors in the thyristors at the same time can not be conducted simultaneously; for example, SR1, SR7 cannot be turned on simultaneously, SR4, SR8 cannot be turned on simultaneously, and so on.
Each of the triacs of fig. 2 and 3 may be replaced by 2 antiparallel triacs. In fig. 2 and 3, the relay normally open switch and the relay normally closed switch form a relay protection switch.
Fig. 4 shows an analog-to-digital conversion coding unit embodiment 1. In fig. 4, FD1 is a true effective value detection device LTC1966, and the LTC1966, a transformer TV1, a capacitor CV1, a capacitor CV2, a resistor RV1, and a resistor RV2 form an effective value detection circuit, and measures the effective values of the ac power supply voltages input from a phase line L1 and a zero line N to obtain a sampled ac power supply voltage value U1. UIN1 and UIN2 of LTC1966 are alternating voltage differential input terminals, USS is a negative power input terminal capable of being grounded, UDD is a positive power input terminal, GND is a ground terminal, EN is a low-level effective enable control input terminal, UOUT is a voltage output terminal, and COM is an output voltage return terminal.
In fig. 4, FD2 is a double-integration a/D converter ICL7109, which is used to divide the voltage of the ac power supply voltage fluctuation interval into voltage level intervals and convert the voltage level intervals into binary voltage level code values for output. In fig. 4, the RUN/hold terminal RUN, the low byte enable terminal LBEN, and the TEST terminal TEST of the ICL7109 are connected to the high level, the chip select terminal CE/LOAD, the MODE terminal MODE, the high byte enable terminal HBEN, and the oscillator select terminal OSC SEL are connected to the low level, and they operate in the continuous (i.e., automatic repeat) conversion MODE and the high byte direct output MODE; the crystal oscillator XT1 is connected to the oscillator input terminal OSC IN and the oscillator output terminal OSC OUT of ICL 7109; one end of an integrating capacitor C11, one end of an integrating resistor R11 and one end of an automatic zero-setting capacitor C12 are connected to form an integrating circuit, and the other end of the integrating capacitor C11, one end of an integrating resistor R11 and one end of an automatic zero-setting capacitor C12 are respectively connected to an integrating capacitor end INT, a buffer output end BUF and an automatic zero-setting capacitor end AZ of the ICL; a differential input high-side IN HOL of ICL7109 inputs the AC power supply voltage sampled value U1, and a differential input low-side IN LO is connected to a reference voltage output terminal REF OUT; the resistor RF1 and the resistor RF2 divide the reference voltage to obtain a reference voltage Uref on the resistor RF2, and the Uref is input to a reference voltage positive input end REF IN + and a reference voltage negative input end REF IN-; the reference capacitor C13 is connected to a reference capacitor positive input terminal REF CAP + and a reference capacitor negative input terminal REF CAP-; v + of ICL7109 is a positive power supply end connected to a power supply + VCC; v-of ICL7109 is a negative power supply end connected to power supply VCC; the GND of ICL7109 is the digital ground and COMMON is the analog ground, both connected to the COMMON ground GND.
Assuming that the fluctuation range of the input alternating current power supply voltage is 220V +/-10%, the self-coupling compensation type main circuit embodiment 1 is required to be adopted to stabilize the input alternating current power supply voltage within the range of 220V +/-2% for output, and the fluctuation range of the alternating current power supply voltage is 242V to 198V, at this time, the analog-to-digital conversion coding unit embodiment 1 of FIG. 4 is adopted, the voltage input between 242V and 198V can be divided into 7 voltage class intervals with the interval voltage size of 6.4V, wherein the voltage of 3 voltage class intervals is higher than the required output voltage range, and the voltage reduction compensation is required; the voltage of the 3 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 6.4V is not more than 220V +/-1.5 percent, and the requirement that the output is controlled within 220V +/-2 percent is met; the fluctuation interval of the alternating current power supply voltage corresponding to 7 voltage class intervals of 6.4V is 242.4V to 197.6V, and the actual fluctuation range is covered. The embodiment 1 of the self-coupling compensation type main circuit of FIG. 2 is adopted for compensation, and the output voltage U12 of the autotransformer TB2 is low, and U23 is high; voltage U23 is 2 times voltage U12; the input voltage of the autotransformer TB2 is alternating current 220V, and the compensation voltage of the TB1 is 6.4V when the output voltage U12 is used as the excitation coil voltage of the TB 1; the input voltage of the autotransformer TB2 is alternating current 220V, and when the output voltage U23 is used as the excitation coil voltage of TB1, the TB1 compensation voltage is 12.8V; the input voltage of the autotransformer TB2 is alternating current 220V, and when the output voltages U12 and U23 are used as the excitation coil voltage of TB1, the compensation voltage of TB1 is 19.2V. IN fig. 4, ICL7109 a/D converts the differential voltage between the differential input high side IN HOL and the differential input low side IN LO; the actual alternating-current power supply voltage fluctuation interval corresponding to 7 voltage class intervals of 6.4V is 242.4V to 197.6V, and the actual fluctuation range is covered; the reference voltage Ucp output from the reference voltage output terminal REF OUT, input to the differential input low-side IN LO should correspond to the lower theoretical value 197.6V of the fluctuation range of the ac power supply voltage; therefore, the transformation ratio of the transformer TV1 and the voltage division ratio of the resistor RV1 and the resistor RV2 are determined, and when the ac power supply voltage is 197.6V, the sampled value U1 of the ac power supply voltage should be equal to the reference voltage Ucp output by the reference voltage output terminal REF OUT. In fig. 4, the voltage level code value P2 output by the analog-to-digital conversion coding unit is composed of data Y14, Y13, Y12, Y11 output from the top 4 bits B12, B11, B10, B9 of ICL 7109; the 7 voltage level code values of Y14, Y13, Y12 and Y11 corresponding to 7 voltage level intervals from low to high are 0000, 0001, 0010, 0011, 0100, 0101 and 0110 respectively, and the method is realized by adjusting the size of the reference voltage Uref. The method for adjusting the size of the reference voltage Uref is as follows: when the voltage of the alternating current power supply fluctuates up and down at a demarcation voltage 236V of the highest 2 voltage class intervals, setting (namely adjusting) the voltage division ratio of the resistor RF1 and the resistor RF2 to enable the numerical values of Y14, Y13, Y12 and Y11 to fluctuate between 0110 and 0101; the second method for adjusting the size of the reference voltage Uref is as follows: let Ux be the voltage variation range of the differential input high-side IN HOL and the differential input low-side IN LO when the AC power supply voltage fluctuates IN the theoretical range of 197.6V to 242.4V, there are
The variation range of Ux corresponds to 7 minimum code values of B12, B11, B10 and B9; let the input-change full-scale input voltage range of 10 BCD code values corresponding to B12, B11, B10 and B9 be Um, have
The reference voltage of ICL7109 is 1/2 of full scale input voltage, there is
Therefore, in this case, it is only necessary to adjust the voltage division ratio between the resistors RF1 and RF2 so that Uref is equal to the calculated value of equation (1).
Assuming that the fluctuation range of the input alternating current power supply voltage is 220V + 10% to 220V-20%, the self-coupling compensation type main circuit embodiment 2 is required to be adopted to stably output the alternating current power supply voltage within the range of 220V ± 2%, and the fluctuation range of the alternating current power supply voltage is 242V to 176V, at this time, the analog-to-digital conversion coding unit embodiment 1 of fig. 4 is adopted, the voltage input between 242V and 176V can be divided into 10 voltage class intervals with the interval voltage size of 7V, wherein the voltage of 3 voltage class intervals is higher than the required output voltage range, and the voltage reduction compensation is required; the voltage of the 6 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 7V is 220V +/-1.6%, and the requirement that the output is controlled within 220V +/-2% is met; the fluctuation interval of the alternating current power supply voltage corresponding to 10 voltage class intervals of 7V is 244.5V to 174.5V, and the actual fluctuation range is covered. The compensation is carried out by adopting the auto compensation type main circuit embodiment 2 in the figure 3, and the output voltage U12 of the auto transformer TB2 is the lowest, and U23 is the highest; the voltage U23 is 3 times the voltage U12, the voltage U34 is 2 times the voltage U12; the input voltage of the autotransformer TB2 is alternating current 220V, and the compensation voltage of the TB1 is 7V when the output voltage U12 is used as the excitation coil voltage of the TB 1; the input voltage of the autotransformer TB2 is alternating current 220V, and when the output voltage U23 is used as the excitation coil voltage of TB1, the TB1 compensation voltage is 21V; the input voltage of the autotransformer TB2 is alternating current 220V, and when the output voltage U34 is used as the excitation coil voltage of TB1, the TB1 compensation voltage is 14V; the input voltage of the autotransformer TB2 is alternating current 220V, and when the output voltages U12 and U23 are used as the excitation coil voltage of TB1, the compensation voltage of TB1 is 28V; and so on. At this time, the actual alternating-current power supply voltage fluctuation interval corresponding to 10 voltage class intervals of 7V is 244.5V to 174.5V, and the actual fluctuation range is covered; the reference voltage Ucp output from the reference voltage output terminal REF OUT, input to the differential input low-side IN LO should correspond to the lower theoretical value 174.5V of the ac supply voltage fluctuation interval range; therefore, the transformation ratio of the transformer TV1 and the voltage division ratio of the resistor RV1 and the resistor RV2 are determined, and when the ac power supply voltage is 174.5V, the sampled value U1 of the ac power supply voltage should be equal to the reference voltage Ucp output by the reference voltage output terminal REF OUT. In fig. 4, the voltage level code value P2 output by the analog-to-digital conversion coding unit is composed of data Y14, Y13, Y12, and Y11 output from the top 4 bits B12, B11, B10, and B9 of ICL7109, and 10 voltage level code values corresponding to voltage level intervals of 10 voltage levels from low to high, Y14, Y13, Y12, and Y11, respectively, are 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, and 1001, and is implemented by adjusting the size of the reference voltage Uref. The method for adjusting the size of the reference voltage Uref is as follows: when the alternating current power supply voltage fluctuates up and down at the boundary of the two highest voltage class intervals (namely 235.4V of the alternating current power supply voltage), setting (namely adjusting) the voltage division ratio of the resistor RF1 and the resistor RF2 to enable the numerical values of Y14, Y13, Y12 and Y11 to fluctuate between 1000 and 1001; the second method for adjusting the size of the reference voltage Uref is as follows: uy is the voltage variation range of the differential input high-side IN HOL and the differential input low-side IN LO when the AC power supply voltage fluctuates IN the theoretical range of 174.5V to 244.5V, and there is a voltage variation range
The variation range of Uy corresponds to 10 code values of B12, B11, B10 and B9 output BCD codes, and the change range of Uy is full-scale input and has
Therefore, in this case, it is only necessary to adjust the voltage division ratio between the resistor RF1 and the resistor RF2 so that Uref is equal to the calculated value of equation (2).
In fig. 4, other peripheral component parameters of LTC1966 and ICL7109 can be determined by reading the corresponding device data sheet. Other detection circuits can be used for realizing the sampled value U1 of the AC power supply voltage, other devices can be used for ICL7109, for example, binary codes output by the double-integration A/D converters MAX139, MAX140, ICL7107 and the like are used for replacing ICL7109, and MAX139, MAX140, ICL7107 and the like are 7-segment codes, and the functions of the binary codes are the same as BCD codes output by ICL 7109.
Fig. 5 shows an embodiment 2 of the analog-to-digital conversion coding unit, in which ac power voltages input from a phase line L1 and a neutral line N are stepped down by a transformer TV2, rectified by a rectifier bridge composed of diodes DV1-DV4, filtered by a capacitor CV3, divided by a resistor RV3 and a resistor RV4, and an ac power voltage sampling value U2 in a direct proportional relationship with an effective value of the input ac power voltage is obtained; the resistor RV5 and the voltage regulator tube WV1 form a low-limit threshold voltage circuit, and the voltage on the voltage regulator tube WV1 is a low-limit threshold voltage U2cp corresponding to the low limit value of the alternating-current power supply voltage fluctuation range. The sampled ac supply voltage U2 may also be fed to the differential input high side IN HOL of ICL7109 IN fig. 4, and converted by ICL7109 into a binary voltage level code and output.
In fig. 5, FD3 is a double-integration a/D converter MC14433 for dividing the voltage range of the ac power supply voltage fluctuation interval into voltage level intervals and converting the voltage level intervals into binary voltage level code values for output. In fig. 5, the end-of-conversion output terminal EOC of the MC14433 is connected to the conversion result output control terminal DU, so that it operates in the automatic repeat conversion state; the integrating resistor R14 and the integrating capacitor C14 are connected to the external integral element ends R1, R1/C1 and C1 of the MC 14433; the oscillation resistor R15 is connected to the clock external element terminals CP0 and CP1 of the MC 14433; the compensation capacitor C15 is connected to the external compensation capacitor ends C01 and C02 of the MC 14433; the resistor RF3 and the resistor RF4 divide the voltage of the power supply + VCC, a reference voltage Uref1 is obtained on the resistor RF4, and Uref1 is input to a reference voltage input end VREF; VDD is a positive power supply end of the MC14433 and is connected to a power supply + VCC; VSS is the digital ground and VAG is the analog ground, both connected to common ground.
In FIG. 5, FD4 is a 4-way D latch CD4042, with the 4-bit data input terminals D0-D3 of CD4042 connected to the 4-bit data output terminals Q0-Q3 of MC 14433; the trigger clock input CP of the CD4042 is connected to the hundred-bit strobe signal output DS2 of the MC 14433; the clock polarity control terminal POL of CD4042 is connected to high, the positive power terminal VDD is connected to the power supply + VCC, and the digital ground terminal VSS is connected to the common ground. The CD4042 latches hundred-bit BCD data time-divisionally output after the MC14433 finishes conversion, and the voltage level code value P2 output by the analog-to-digital conversion coding unit consists of data Y14, Y13, Y12 and Y11 output from output ends Q3, Q2, Q1 and Q0 of the CD 4042. CD4042 may be replaced with other latches.
Assuming that the fluctuation range of the input alternating current power supply voltage is 220V +/-10%, the self-coupling compensation type main circuit embodiment 1 is required to be adopted to stabilize the input alternating current power supply voltage within the range of 220V +/-2% for output, and the fluctuation range of the alternating current power supply voltage is 242V to 198V, at this time, the analog-to-digital conversion coding unit embodiment 2 of FIG. 5 is adopted, the voltage input between 242V and 198V can be divided into 7 voltage class intervals with the interval voltage size of 6.4V, wherein the voltage of 3 voltage class intervals is higher than the required output voltage range, and the voltage reduction compensation is required; the voltage of the 3 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out.
In FIG. 5, the input VX of the measured voltage of MC14433 is connected to the output of the sampled value of the AC supply voltage U2, and the low-threshold voltage U2cp is connected to the common ground GND, therefore, MC14433 converts the voltage difference between the sampled value of the AC supply voltage U2 and the low-threshold voltage U2 cp; the actual alternating-current power supply voltage fluctuation interval corresponding to 7 voltage class intervals of 6.4V is 242.4V to 197.6V, and the low-limit threshold voltage U2cp corresponds to a low-limit theoretical value of the alternating-current power supply voltage fluctuation interval range of 197.6V; therefore, when the conversion ratio of the transformer TV2 and the voltage division ratio of the resistor RV3 and the resistor RV4 are lower limit theoretical values of 197.6V, the sampled value U2 of the ac power supply voltage should be equal to the lower limit threshold voltage U2 cp. In fig. 5, the voltage level code value P2 output by the analog-to-digital conversion coding unit is composed of data Y14, Y13, Y12, Y11 output from MC14433 hundreds bits; since it is required to divide the voltage input between 242.4V and 197.6V into 7 voltage class intervals with a class voltage size of 6.4V, and 7 voltage class code values of Y14, Y13, Y12 and Y11, which correspond to the 7 voltage class intervals from low to high one by one, are 0000, 0001, 0010, 0011, 0100, 0101 and 0110, respectively, it is implemented by adjusting the size of the reference voltage U2ref input to the MC 14433. The method for adjusting the size of the reference voltage U2ref is as follows: when the voltage of the alternating current power supply fluctuates up and down at a demarcation voltage 236V of the highest 2 voltage class intervals, the reference voltage is reduced from the maximum value, and the voltage division ratio of the resistor RF3 and the resistor RF4 is adjusted to enable the numerical values of Y14, Y13, Y12 and Y11 to fluctuate between 0110 and 0101; the second method for adjusting the magnitude of the reference voltage U2ref is as follows: let Ux be the voltage variation range of the alternating current power supply voltage when the voltage fluctuates in the theoretical range of 197.6V to 242.4V, and
because the measurement output of the MC14433 is 3-bit half BCD data, corresponding to full-scale input, the thousand bits plus hundred bits have 20 BCD coding values, and the variation range of Ux corresponds to 7 minimum coding values; let the input voltage range of input variation full scale corresponding to 20 BCD code values be Uz, have
The reference voltage of MC14433 is equal to the full-scale input voltage, has
Therefore, at this time, it is only necessary to adjust the voltage division ratio between the resistor RF3 and the resistor RF4 so that U2ref is equal to the calculated value of equation (3).
Assuming that the fluctuation range of the input alternating current power supply voltage is 220V + 10% to 220V-20%, the self-coupling compensation type main circuit embodiment 2 is required to be adopted to stably output the alternating current power supply voltage within the range of 220V +/-2%, and the fluctuation range of the alternating current power supply voltage is 242V to 176V, at this time, the analog-to-digital conversion coding unit embodiment 2 of FIG. 5 is adopted, the voltage input between 242V and 176V can be divided into 10 voltage grade intervals with the interval voltage size of 7V, wherein the voltage of 3 voltage grade intervals is higher than the required output voltage range, and the voltage reduction compensation is required; the voltage of the 6 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The actual alternating-current power supply voltage fluctuation interval corresponding to 10 voltage class intervals of 7V is 244.5V to 174.5V, and the low-limit threshold voltage U2cp corresponds to the low-limit theoretical value 174.5V of the alternating-current power supply voltage fluctuation interval range; therefore, when the conversion ratio of the transformer TV2 and the voltage division ratio of the resistor RV3 and the resistor RV4 are lower limit theoretical values 174.5V, the sampled value U2 of the ac power supply voltage should be equal to the lower limit threshold voltage U2 cp. In fig. 5, the voltage level code value P2 output by the adc coding unit is composed of data Y14, Y13, Y12, and Y11 output from MC14433 hundreds, and 10 voltage level code values, which are respectively 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, and 1001 corresponding to 10 voltage level intervals from low to high in voltage level, of Y14, Y13, Y12, and Y11 are respectively implemented by adjusting the size of the reference voltage U2 ref. The method for adjusting the size of the reference voltage U2ref is as follows: when the alternating current power supply voltage fluctuates up and down at the boundary of two highest voltage level intervals (namely 235.4V of the alternating current power supply voltage), the reference voltage is reduced from the maximum value, and the voltage division ratio of the resistor RF3 and the resistor RF4 is adjusted to enable the numerical values of Y14, Y13, Y12 and Y11 to fluctuate between 1000 and 1001; the second method for adjusting the magnitude of the reference voltage U2ref is as follows: when Uy is the voltage variation range of the alternating current power supply voltage when the alternating current power supply voltage fluctuates in the theoretical range of 174.5V to 244.5V, the voltage variation range includes
The variation range of Uy corresponds to 10 minimum encoding values in 20 BCD encoding values of MC14433 kbits plus hundred bits; let the input voltage range of full scale of input change corresponding to 20 BCD code values at this time be Uz, have
The reference voltage of MC14433 is equal to the full-scale input voltage, has
Therefore, at this time, it is only necessary to adjust the voltage division ratio between the resistor RF3 and the resistor RF4 so that U2ref is equal to the calculated value of equation (4).
In fig. 5, other peripheral component parameters of MC14433 can be determined by reading the corresponding device data manual. The ac supply voltage sample value U2 may also be implemented using other detection circuits, such as various true valid value detection chips. The difference between the sampled ac supply voltage U2 and the corresponding low threshold voltage may also be obtained by other methods, such as subtracting the corresponding low threshold voltage value from the sampled ac supply voltage U2 using an analog voltage subtractor circuit.
In the above embodiments, when the self-coupled compensation type main circuit embodiment 1 is used to perform voltage compensation, and the adc embodiment 1 in fig. 4 or the adc embodiment 2 in fig. 5 is used to divide the voltage input between 242V and 198V into 7 voltage level intervals with an interval voltage of 6.4V, among the voltage level code values consisting of Y14, Y13, Y12 and Y11, Y14 is constantly equal to 0, so that the actual voltage level code value at this time may also be considered to consist of 3 bits, i.e., Y13, Y12 and Y11, and the 7 voltage level code values corresponding to the voltage level intervals from low to high 7, i.e., Y13, Y12 and Y11, are 000, 001, 010, 011, 100, 101 and 110, respectively.
Fig. 6 is a block diagram of an embodiment of a delay protection unit, wherein a delay detection module YC1 respectively delays input voltage level code values Y14, Y13, Y12, and Y11 to obtain delayed voltage level code values Y24, Y23, Y22, and Y21, and Y23, Y24, Y22, and Y21 form P3; the YC1 module simultaneously and respectively carries out edge detection on Y14, Y13, Y12 and Y11 to obtain edge detection signals Y34, Y33, Y32 and Y31; the no-trigger area control signal generation module YC2 converts the input edge detection signals Y34, Y33, Y32, Y31 into the no-trigger area control signal P4 for output. In the block diagram of the embodiment of fig. 6, the voltage level code values input by the delay detection module YC1 have 4 bits, such as Y14, Y13, Y12, Y11, etc., and K is equal to 4; if K is equal to 3, the voltage level code value inputted by the delay detection module YC1 is composed of 3 bits binary value, for example, when Y13, Y12 and Y11 are included, the voltage level code value after signal delay is performed to obtain delay is only 3 bits such as Y23, Y22 and Y21, the edge detection signal obtained by edge detection on Y13, Y12 and Y11 is only 3 bits such as Y33, Y32 and Y31, and the edge detection signal inputted by the non-trigger area control signal generation module YC2 is only 3 bits such as Y33, Y32 and Y31.
Fig. 7 is a circuit embodiment 1 of the delay detection module for detecting the delay of the voltage level code value signal Y11. The resistor RY0, the capacitor CY0 and the driving gate FY0 realize signal delay of Y11, and a delayed signal Y21 of Y11 is obtained. The resistor RY1, the capacitor CY1, the diode DY1 and the inverter FY1 form a rising edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is output in the output signal YP1 of the inverter FY 1. The resistor RY2, the capacitor CY2, the diode DY2, the inverters FY2 and FY3 constitute a falling edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the falling edge of Y11 is output in the output signal YP2 of the inverter FY 3. The nand gate FY4 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY4, that is, when the input signal Y11 changes, the nand gate FY4 outputs a single pulse in the form of a positive pulse. In fig. 7, the drive gate FY0, inverter FY1, inverter FY3 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; the drive gate FY0 may consist of 2 inverters with schmitt inputs.
Fig. 8 is a circuit embodiment 2 of the delay detection module for detecting the delay of the voltage level code value signal Y11. The inverter FY5, the resistor RY3 and the capacitor CY3 invert and delay the input signal Y11 to obtain a delayed inverted signal YP0 of Y11; the inverter FY6 inverts YP0 to obtain a delayed Y11 signal Y21. The signal input by the nand gate FY7 is a delayed inverted signal YP0 of Y11 and Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is generated in the output signal YP 1; the or gate FY8 receives the inverted signals YP0 of Y11 and Y11, and the output signal YP2 generates a single pulse in the form of a negative pulse corresponding to the falling edge of Y11. The nand gate FY9 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY9, that is, when the input signal Y11 changes, the nand gate FY9 outputs a single pulse in the form of a positive pulse. In fig. 8, inverter FY6, nand gate FY7, or gate FY8 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; nand gate select 74HC132, CD4093, etc.; or gate select 74HC7032 or 2 inverters with schmitt inputs and 1 nand gate to implement the or gate function.
Fig. 9 is a delay detection circuit embodiment 3 of the delay detection module for the voltage level encoded value signal Y11, in which a rising edge detection circuit for the input signal Y11 is composed of a resistor RY1, a capacitor CY1, a diode DY1 and an inverter FY1, and a falling edge detection circuit for the input signal Y11 is composed of a resistor RY2, a capacitor CY2, a diode DY2, an inverter FY2 and an inverter FY3, and a circuit for outputting the edge detection signal Y31 by using the nand gate FY4 is the same as in embodiment 1 of fig. 7. In fig. 9, the signal delay of Y11 is realized by inverters FY11, FY12, FY13, and FY14, and a delayed signal Y21 of Y11 is obtained.
The embodiments 1-3 of fig. 7, 8 and 9 are all delay detection circuits for the signal Y11 in the voltage level code value, and the delay detection circuits for the other signals in the voltage level code value, for example, the delay detection circuits for the input signals Y13 and Y12, and the delay detection circuit for the Y14 in the 4-bit voltage level code value, have the same circuit structure and function as the circuit for performing delay detection for the input signal Y11 in the corresponding embodiments. The delay detection circuit may also adopt other circuits meeting the requirements to realize the functions thereof.
The function of the no-trigger area control signal generation module is to output a single pulse in the no-trigger area control signal when any one or more of the input edge detection signals generate a single pulse related to an edge. Fig. 10 shows an embodiment of the no-trigger area control signal generation module, where the or gate FY10 implements the corresponding function, and the input signals of the or gate FY10 are edge detection signals Y34, Y33, Y32, and Y31, and the output signal is a no-trigger area control signal P4. In the embodiment of fig. 10, the single pulse not triggering the output of the zone control signal is a positive pulse, i.e. the high level of the zone control signal is not activated; when the or gate FY10 is replaced by a nor gate, the single pulse that does not trigger the output of the zone control signal is a negative pulse, and the low level of the zone control signal is active. If the single pulse associated with an edge generated in the input edge detection signals Y34, Y33, Y32 and Y31 is a negative pulse, the or gate in fig. 10 should be changed to a nand gate or an and gate to implement a negative logic or logic function. If the input edge detection signal has only 3 bits, for example, only the edge detection signals Y33, Y32, and Y31, the or gate in fig. 10, or other gates for implementing the function of the trigger zone free control signal generation module, such as nor gate, nand gate, and gate, etc., is also a 3-input gate circuit accordingly.
Fig. 11 is a schematic diagram of a partial correlation waveform in the delay protection unit. In fig. 11, Y11 among the voltage level code values undergoes a rising edge change and a falling edge change, respectively, and Y21 is the voltage level code value of Y11 delayed by T1 time; in embodiment 1 of the delay detection circuit in fig. 7, T1 is determined by the magnitude of the product of the resistor RY0 and the capacitor CY0 (i.e., the magnitude of the time constant); in embodiment 2 of the delay detection circuit in fig. 8, T1 is determined by the product of the resistor RY3 and the capacitor CY 3; in the embodiment 3 of the delay detection circuit in fig. 9, T1 is determined by the gate delay time of the inverters FY11, FY12, FY13 and FY 14. In fig. 11, the negative pulse width of the signal YP1 due to the rising edge of Y11 is T2; in the delay detection circuit embodiment 1 of fig. 7 and the delay detection circuit embodiment 3 of fig. 9, T2 is determined by the magnitude of the product of the resistor RY1 and the capacitor CY 1; in embodiment 2 of the delay detection circuit in fig. 8, T2 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 11, the negative pulse width generated by the falling edge of Y11 in the signal YP2 is T3; in the delay detection circuit embodiment 1 of fig. 7 and the delay detection circuit embodiment 3 of fig. 9, T3 is determined by the magnitude of the product of the resistor RY2 and the capacitor CY 2; in embodiment 2 of the delay detection circuit in fig. 8, T3 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 11, 2 positive pulses in the edge detection signal Y31 correspond to a negative pulse due to a rising edge of Y11 in the signal YP1 and a negative pulse due to a falling edge of Y11 in the signal YP2, respectively. When Y11 in the voltage level code value of fig. 11 is changed in rising edge, Y12, Y13 and Y14 in the voltage level code value are not changed, and the corresponding edge detection signals Y32, Y33 and Y34 do not generate positive pulses; when Y11 is changed by a falling edge, Y12 in the voltage level code value is changed at the same time, Y13 and Y14 are not changed, and a positive pulse related to Y12 change is generated in the corresponding edge detection signal Y32; since Y33 and Y34 remain at the low level, they are not shown in fig. 11. According to the logic function of the non-trigger area control signal generation module, the width of the single pulse output by the non-trigger area control signal generation module is the same as the widest pulse width of the input pulses which jointly generate the single pulse in the input edge detection signals. In FIG. 11, the 1 st positive pulse in the non-trigger area control signal P4 is generated by the 1 st negative pulse in the edge detection signal Y31, and the widths of the two pulses are the same; the 2 nd positive pulse in the no-trigger-zone control signal P4 is generated by the influence of the 2 nd negative pulse in the edge detection signal Y31 and the negative pulse in the edge detection signal Y32, and has the same width as the negative pulse with the widest width among the 2 negative pulses generating the positive pulse; as can be seen from fig. 11, the negative pulse width in Y32 is wide, and the 2 nd positive pulse width in P4 is the same as the negative pulse width in Y23. The width difference is caused by the difference between the resistance and capacitance values of T2 and T3 determined in different delay detection circuits.
In the embodiment 1 of the delay detection circuit in the delay protection unit of fig. 7, the delay time for the voltage level code value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY1 and FY4 and FY10 in fig. 10, or the sum of the delay times of the gates FY3 and FY4 and FY10 in fig. 10; the selection range of the signal delay time T1 of the voltage level code value determined by the product of the resistor RY0 and the capacitor CY0 is ms order of magnitude, obviously, is greater than the delay time of the voltage level code value changing to the leading edge of the single pulse of the corresponding non-trigger area control signal, that is, the time of the delay change of the level code value signal is later than the leading edge time of the single pulse output after the voltage level code value changes. Strictly speaking, T1 actually includes the sum of the delay time caused by resistor RY0 and capacitor CY0, and the delay time of gate FY 0. In embodiment 1 of fig. 7, when selecting the parameters, the value of T2 and the value of T3 are both made to be greater than the value of T1, so that the timing at which the gradation code value signal changes with a delay meets the requirement that the timing of the trailing edge of the output single pulse be earlier than the timing at which the voltage gradation code value changes.
In the embodiment 2 of the delay detection circuit in the delay protection unit of fig. 8, the delay time for the voltage level code value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY7 and FY9 and FY10 in fig. 10, or the sum of the delay times of the gates FY8 and FY9 and FY10 in fig. 10; t1 is a value of ms magnitude, and it is obvious that the signal delay time T1 of the voltage level code value determined by the product of the resistor RY3 and the capacitor CY3 is longer than the delay time of the voltage level code value changing to the leading edge of the corresponding single pulse of the no-trigger-zone control signal, i.e. the time of the delay change of the voltage level code value signal is later than the time of the leading edge of the single pulse output after the voltage level code value changes. In the embodiment 2 of the delay detection circuit in fig. 8, both the time when the voltage level code value signal changes in delay and the time when the trailing edge of the output single pulse after the voltage level code value changes are affected by the change of the signal YP 0; the time when the voltage level code value signal delay changes is the delay of the gate circuit FY6 after the signal YP0 changes; the trailing edge time of the single pulse output after the voltage level code value is changed is the sum of the delay time of the gate circuits FY7 and FY9 after the signal YP0 is changed and FY10 in FIG. 10, or the sum of the delay time of the gate circuits FY8 and FY9 after the signal YP0 is changed and FY10 in FIG. 10; obviously, the time of the delay change of the voltage level code value signal is less than the time of the trailing edge of the output single pulse after the voltage level code value is changed by 2 gate circuits, and the requirement that the time of the delay change of the voltage level code value signal is earlier than the time of the trailing edge of the output single pulse after the voltage level code value is changed is met.
Fig. 12 shows an example of an interlock control unit, and fig. 12(a) shows an interlock control unit example 1 in which YR1 is a ROM memory. In embodiment 1 of the self-coupled compensation type main circuit of fig. 2, the output voltage U12 of the autotransformer TB2 is low, and U23 is high; the voltage U23 is 2 times the voltage U12. Table 1 is a logic truth table for performing compensation control by using the self-coupled compensation main circuit embodiment 1 of fig. 2, and dividing the power voltage into 7 voltage level intervals by using the adc unit embodiment 1 of fig. 4 or the adc unit embodiment 2 of fig. 5, and performing logic control when 7 voltage level code values are formed by Y13, Y12, and Y11, or by delayed Y23, Y22, and Y21; the fluctuation range of the alternating current power supply voltage is 220V +/-10%, and the alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. When the logic function of the interlocking control unit is realized by adopting a ROM, P4 and Y23-Y21 are respectively connected to the address input ends A3-A0 of the ROM in sequence, the data outputs D0-D5 of the ROM are the logic outputs of the interlocking control unit, and 6 output signals P51-P56 form a trigger control signal P5.
TABLE 1
In table 1, when the trigger zone control signal is not valid, P4 is equal to 0, and the voltage level code value is a value corresponding to the voltage level 1-7, the interlock control unit controls the self-coupled compensation type main circuit embodiment 1 to perform the corresponding voltage compensation; for example, when the input voltage is the lowest voltage level 1, the outputs of the P51 and the P56 are controlled to be 0 to turn on the bidirectional thyristors SR1 and SR6, the other outputs of the P52 and the like are controlled to be 1 to turn off other bidirectional thyristors, and the output voltage U12+ U23 is used for forward compensation of the excitation coil voltage of the TB 1; when the input voltage is in a voltage class of 2, the outputs of P53 and P56 are controlled to be 0 to turn on the bidirectional thyristors SR3 and SR6, the other outputs of P51 and the like are controlled to be 1 to turn off other bidirectional thyristors, and the forward compensation is carried out by only adopting the output voltage U23 as the excitation coil voltage of TB 1; when the input voltage is at a voltage level of 4, the outputs of P55 and P56 are controlled to be 0 to turn on the bidirectional thyristors SR5 and SR6, and the other outputs of P51 and the like are controlled to be 1 to turn off other bidirectional thyristors, so that 0 voltage compensation is realized; when the input voltage is in the voltage class of 5, the outputs of P52 and P53 are controlled to be 0 to turn on the bidirectional thyristors SR2 and SR3, the other outputs of P51 and the like are controlled to be 1 to turn off other bidirectional thyristors, and the reverse output voltage U12 is only used for performing reverse compensation on the excitation coil voltage of TB 1; and so on. When the P4 is equal to 1, the fluctuation of the alternating current power supply voltage is indicated, so that the voltage level code value is changed, the switching of the on-off combination state of the thyristor switch group is required, and the compensation mode is changed. In the switching process of the electronic switch, in order to avoid the situation that the power supply is short-circuited due to the factor of delayed turn-off of the electronic switch when the thyristors in the thyristor switch group are switched, for example, the thyristors SR1 and SR3 are turned on simultaneously to cause short-circuiting, and the like, during the period when the zone control signal is not triggered to be valid, that is, when the P4 in the embodiment is equal to 1, all the triacs in the thyristor switch group are turned off, and the interlock control unit controls the P51-P56 to all output 1.
In Table 1, M is equal to 7. When the control signal of the non-trigger area is invalid (P4 is equal to 0), the valid code values of 7 voltage level code values P3 correspond to 7 groups of valid trigger control signals, and accordingly control of 7 voltage compensation states is realized; when the P2 is changed to make P4 active (P4 equals 1), 1 group of active trigger control signals are corresponded, and the interlock control unit outputs 8 groups of active trigger control signals in total. When P4 is invalid (P4 is equal to 0) and the voltage level code value P3 inputted by the interlock control unit is an invalid code value, the interlock control unit corresponds to 1 specific group of invalid trigger control signals. With the analog-to-digital conversion coding unit embodiment 1 in fig. 4 or the analog-to-digital conversion coding unit embodiment 2 in fig. 5, the power supply voltage is divided into 7 voltage level intervals, valid code values of 7 voltage level code values are output by Y13, Y12, and Y11, and only 1 invalid code value may be output by Y13, Y12, Y11 or Y23, Y22, and Y21, which is 111. In Table 1, the 1 group of invalid trigger control signals makes the P56 output 0 and the P51-P55 outputs 1; the specific invalid trigger control signal does not actually control the thyristor, even if the trigger control function of the thyristor is performed, only the TB1 excitation coil is connected to one tap of the autotransformer TB2, the excitation voltage is 0, and no voltage compensation is performed; the 1 specific inactive trigger control signal may also select other trigger combinations that are not voltage compensated, for example, such that the P55 output is 0 and the other outputs are 1.
In table 1, the trigger control signal output by the interlock control unit triggers the triac to be active at a low level when it is turned on. If the trigger control signal output by the interlocking control unit requires that the high level is effective when the trigger bidirectional thyristor is conducted, 1 in the output signal of the logic truth table in the table 1 needs to be changed into 0, and 0 needs to be changed into 1; when the function is realized by a ROM, the content of the memory cell is inverted according to Table 1.
Fig. 12(b) shows an interlock control unit embodiment 2 in which YR2 is a ROM memory. In the embodiment 2 of the self-coupled compensation type main circuit in fig. 3, the output voltage U12 of the autotransformer TB2 is the lowest, and U23 is the highest; the voltage U23 is 3 times the voltage U12 and the voltage U34 is 2 times the voltage U12. Table 2 is a logic truth table for performing compensation control by using the self-coupled compensation main circuit embodiment 2 of fig. 3, and dividing the power voltage into 10 voltage level intervals by using the adc unit embodiment 1 of fig. 4 or the adc unit embodiment 2 of fig. 5, and performing logic control when 10 voltage level code values are formed by Y14, Y13, Y12, and Y11, or by delayed Y24, Y23, Y22, and Y21; the fluctuation range of the alternating current power supply voltage is 220V + 10% to 220V-20%, and the alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. When the ROM YR2 is adopted to realize the logic function, inputs P4 and Y24-Y21 are respectively connected to address terminals A4-A0 of the ROM in sequence, data outputs D0-D7 of the ROM are the logic outputs of the interlocking control unit, and 8 output signals P51-P58 form a trigger control signal P5.
In table 2, when the trigger zone control signal is not valid, P4 is equal to 0, and the voltage level code value is a value corresponding to the voltage level 1-10, the interlock control unit controls the self-coupled compensation type main circuit embodiment 2 to perform the corresponding voltage compensation; for example, when the input voltage is at voltage level 7, the outputs of P57 and P58 are controlled to be 0 to turn on the triacs SR7 and SR8, and the other outputs of P51 and the like are controlled to be 1 to turn off other triacs, so that 0 voltage compensation is realized; when the input voltage is in the voltage class of 8, the outputs of P52 and P53 are controlled to be 0 to turn on the bidirectional thyristors SR2 and SR3, the other outputs of P51 and the like are controlled to be 1 to turn off other bidirectional thyristors, and the reverse output voltage U12 is only used for performing reverse compensation on the excitation coil voltage of TB 1; when the input voltage is 9, the outputs of P56 and P57 are controlled to be 0 to turn on the bidirectional thyristors SR6 and SR7, the other outputs of P51 and the like are controlled to be 1 to turn off other bidirectional thyristors, and the reverse output voltage U34 is only used for performing reverse compensation on the excitation coil voltage of TB 1; when the input voltage is in a voltage level of 10, the outputs of P54 and P55 are controlled to be 0 to turn on the bidirectional thyristors SR4 and SR5, the other outputs of P51 and the like are controlled to be 1 to turn off other bidirectional thyristors, and the reverse output voltage U23 is only used for performing reverse compensation on the excitation coil voltage of TB 1; when the input voltage is in the voltage class of 6, the outputs of P51 and P54 are controlled to be 0 to turn on the bidirectional thyristors SR1 and SR4, the other outputs of P52 and the like are controlled to be 1 to turn off other bidirectional thyristors, and the forward compensation is carried out by only adopting the output voltage U12 as the excitation coil voltage of TB 1; when the input voltage is in a voltage class of 4, the outputs of P53 and P56 are controlled to be 0 to turn on the bidirectional thyristors SR3 and SR6, the other outputs of P51 and the like are controlled to be 1 to turn off other bidirectional thyristors, and the forward compensation is carried out by only adopting the output voltage U23 as the excitation coil voltage of TB 1; when the input voltage is in a voltage class of 3, the outputs of P51 and P56 are controlled to be 0 to turn on the bidirectional thyristors SR1 and SR6, the other outputs of P52 and the like are controlled to be 1 to turn off other bidirectional thyristors, and the output voltage U12+ U23 is used as the excitation coil voltage of TB1 for forward compensation; when the input voltage is in the voltage class 1, the outputs of P51 and P58 are controlled to be 0 to turn on the bidirectional thyristors SR1 and SR8, the other outputs of P52 and the like are controlled to be 1 to turn off other bidirectional thyristors, and the output voltage U12+ U23+ U34 is adopted to carry out forward compensation on the excitation coil voltage of TB 1; and so on. When the control signal of the non-trigger area is effective, when the P4 is equal to 1, the fluctuation of the voltage of the alternating current power supply is shown, the voltage level code value is changed, the switching of the on-off combination state of the thyristor switch group is required, the compensation mode is changed, all the bidirectional thyristors in the thyristor switch group are switched off at the moment, and the interlocking control unit controls the P51-P58 to output 1 in total.
In Table 2, M is equal to 10. When the control signal of the non-trigger area is invalid (P4 is equal to 0), the valid code values of 10 voltage level code values P3 correspond to 10 groups of valid trigger control signals, and accordingly control of 10 voltage compensation states is realized; when the change in P2 makes P4 active (P4 equal to 1), there are 1 active set of trigger control signals, and the interlock control unit has 11 active set of trigger control signals. When the P4 is invalid (P4 is equal to 0) and the voltage level code value P3 input by the interlock control unit is an invalid code value, the interlock control unit corresponds to 1 group of specific invalid trigger control signals; with the analog-to-digital conversion coding unit embodiment 1 of fig. 4 or the analog-to-digital conversion coding unit embodiment 2 of fig. 5, the power supply voltage is divided into 10 voltage level intervals, the voltage level code values composed of Y14, Y13, Y12, and Y11 output valid code values of 10 voltage level code values in total, and the 4-bit voltage level code values Y14, Y13, Y12, and Y11, or Y24, Y23, Y22, and Y21 may also have outputs of 6 invalid code values, all of which enable the interlock control unit to output the same 1 set of invalid trigger control signals; in Table 2, the 1 group of invalid trigger control signals makes the P58 output 0 and the P51-P57 outputs 1; the specific invalid trigger control signal does not actually control the thyristor, even if the trigger control function of the thyristor is performed, only the TB1 excitation coil is connected to one tap of the autotransformer TB2, the excitation voltage is 0, and no voltage compensation is performed; the 1 specific inactive trigger control signal may also select other trigger combinations that are not voltage compensated, for example, such that the P57 output is 0 and the other outputs are 1.
In table 2, the trigger control signal output by the interlock control unit triggers the triac to be active at a low level when it is turned on. If the trigger control signal output by the interlock control unit requires that the high level is effective when the trigger bidirectional thyristor is conducted, 1 in the output signal of the logic truth table in the table 2 needs to be changed into 0, and 0 needs to be changed into 1; when the function is realized by a ROM memory, the contents of the memory cells are inverted according to table 2.
TABLE 2
The combinational logic functions in table 1 or the truth table of table 2 can be implemented by other means besides ROM memory.
Fig. 13 shows an embodiment of a trigger circuit for triggering the triac SR1 in the trigger unit, which is composed of an ac trigger optocoupler UG1, a resistor RG1, and a resistor RG2, and the trigger control signal P51 is active at low level. The alternating current trigger optocoupler UG1 can be selected from phase-shifting bidirectional thyristor output optocouplers such as MOC3021, MOC3022, MOC3023, MOC3051, MOC3052 and MOC 3053. Power supply + VCCK is the controlled power supply controlled by the error detection control unit. The circuit structure of the trigger circuit for triggering the bidirectional thyristors SR2-SR6 in the embodiment 1 of the self-coupling compensation type main circuit in FIG. 2 or the bidirectional thyristors SR2-SR8 in the embodiment 2 of the self-coupling compensation type main circuit in FIG. 3 is the same as that of the trigger bidirectional thyristor SR 1. The trigger pulses output by the alternating current trigger optocoupler UG1 in fig. 13 from G11 and G12 and the trigger pulses output by other alternating current trigger optocouplers in the trigger unit jointly form a trigger signal P6.
FIG. 14 shows an embodiment of an error detection control unit, wherein YR3 is a ROM memory, and the ROM memory constitutes a determination module for determining whether the input trigger control signal P5 is a valid trigger control signal; the triode VT, the triode VK1, the triode VK2, the relay coil KA, the freewheeling diode VD, the resistor RK1, the resistor RK2 and the resistor RK3 form a protection control circuit. + VCC2 is the power supply for the relay coil and the source for the trigger unit controlled power supply.
The error detection control unit in the embodiment of fig. 14 is configured to determine the trigger control signal sent by the interlock control unit in the embodiment 1 in fig. 12(a), and table 3 is a logic truth table for determining whether the trigger control signal sent by the interlock control unit in the embodiment 1 is a valid trigger control signal, where the autotransformer has 3 taps and the thyristor switch group is composed of 6 triacs.
TABLE 3
When the trigger control signal sent by the interlock control unit embodiment 1 is 1 of 8 effective trigger control signals listed in the front 8 rows in table 3, the trigger control determination signal output by the determination module is effective, that is, P7 is 1, which indicates that the trigger control signal is an effective trigger control signal, the triodes VK1 and VK2 are turned on, the controlled power supply + VCCK is powered on, and the trigger unit normally operates and sends a corresponding trigger pulse according to the trigger control signal. The P7 is 1, and simultaneously controls the triode VT to be conducted, the relay coil KA is electrified, so that the normally open switch KA-1 of the relay in the embodiment 1 of the self-coupling compensation type main circuit in the figure 2 is closed, the normally closed switch KA-2 of the relay is disconnected, and the thyristor switch group is in a compensation working state. When the trigger control signal sent by the interlock control unit embodiment 1 is other signals, and is not any 1 of the 8 groups of valid trigger control signals listed in the front 8 rows in table 3, the trigger control determination signal output by the determination module is invalid, i.e., P7 is 0, the triodes VK1 and VK2 are turned off, the controlled power supply + VCCK is powered off, and the trigger unit does not work, i.e., does not send the trigger pulse for triggering the thyristor. When the P7 is 0, the triode VT is controlled to be cut off, and the relay coil KA loses power, so that the normally open switch KA-1 of the relay in the embodiment 1 of the self-coupling compensation type main circuit in fig. 2 is turned off, that is, the power supply voltage at the input side of the self-coupling transformer is controlled to be turned off, the voltage between all taps of the self-coupling transformer is 0, and the thyristor switch group is protected; the normally closed switch KA-2 of the relay is controlled to be closed, so that the voltage applied to the excitation coil of TB1 is 0. When the input of the interlocking control unit embodiment 1 is an invalid code value and outputs an invalid trigger control signal, as can be seen from table 3, the output of the discrimination module is also 0, so that the protection of the thyristor switch group is realized; therefore, no matter an invalid code value is output due to the fact that the analog-to-digital conversion coding unit has a coding error fault, or an invalid trigger control signal is output due to the fact that the interlocking control unit has a control error, the error detection control unit starts to protect the thyristor switch group. When the logic truth table in table 3 is implemented by using a ROM memory, the address input of the ROM memory needs 6 bits, i.e., a0-a5 in table 3, and is correspondingly connected with input signals P51-P56; the data output of the ROM memory requires 1 bit, d0 in table 3, corresponding to the control signal P7 of the connection output.
When the error detection control unit needs to determine the trigger control signal sent out by the interlock control unit in embodiment 2 in fig. 12(b), table 4 is a logic truth table for determining whether the trigger control signal sent out by the interlock control unit in embodiment 2 is an effective trigger control signal, and at this time, the autotransformer has 4 taps and the thyristor switch group is composed of 8 triacs.
TABLE 4
When the trigger control signal sent by the interlock control unit embodiment 2 is 1 of the 11 effective trigger control signals listed in the front 11 rows in table 4, the trigger control determination signal output by the determination module is effective, that is, P7 is 1, which indicates that the trigger control signal is an effective trigger control signal, the triodes VK1 and VK2 are turned on, the controlled power supply + VCCK is powered on, and the trigger unit normally operates and sends a corresponding trigger pulse according to the trigger control signal. The P7 is 1, and controls the relay normally open switch KA-1 to close and the relay normally closed switch KA-2 to open in the embodiment 2 of the self-coupling compensation type main circuit of the 3, and the circuit is in a compensation working state. When the trigger control signal sent by the interlock control unit embodiment 2 is other signals, and is not any 1 of the 11 groups of valid trigger control signals listed in the front 11 rows in table 4, the trigger control determination signal output by the determination module is invalid, i.e., P7 is 0, the triodes VK1 and VK2 are turned off, the controlled power supply + VCCK is powered off, and the trigger unit does not operate, i.e., does not send the trigger pulse for triggering the thyristor. P7 is 0, and the normally open switch KA-1 of the relay in embodiment 2 of the self-coupling compensation type main circuit of fig. 3 is controlled to be turned off, that is, the power supply voltage at the input side of the self-coupling transformer is controlled to be turned off, so that the voltage between all taps of the self-coupling transformer is 0, and the thyristor switch group is protected; the normally closed switch KA-2 of the relay is controlled to be closed, so that the voltage applied to the excitation coil of TB1 is 0. When the input of the interlocking control unit embodiment 2 is an invalid code value and outputs an invalid trigger control signal, as can be seen from table 4, the output of the discrimination module is 0, so that the protection of the thyristor switch group is realized; similarly, whether an invalid code value is output due to a coding error fault of the analog-to-digital conversion coding unit or an invalid trigger control signal is output due to a control error of the interlocking control unit, the error detection control unit starts to protect the thyristor switch group.
When the logic truth table of table 4 is implemented by ROM memory, for example, the embodiment of fig. 14 is used to implement the function of error detection control unit, the address input of ROM memory YR3 in fig. 14 needs to be expanded to 8 bits, i.e., the address input needs a0-a7, corresponding to the connection input signals P51-P58; the data output of the ROM memory requires 1 bit, d0 in table 4, corresponding to the control signal P7 of the connection output. When the error detection control unit judges that the input trigger control signal is not an effective trigger control signal, the error detection control unit sends a protection control signal to the self-coupling compensation type main circuit, so that the thyristor switch group is in a protection state, the self-coupling compensation type alternating current voltage stabilizer does not compensate the input voltage, and the voltage output by the voltage stabilizer is the input alternating current power supply voltage. When the thyristor switch group is in the protection state, if the error detection control unit judges that the input trigger control signal is recovered to be an effective trigger control signal, the error detection control unit automatically stops the protection state of the thyristor switch group, and the thyristor switch group is in the compensation working state again.
The combinational logic functions in table 3 or the truth table of table 4 can be implemented by other means besides ROM memory.
As can be seen from the above embodiments and the working process thereof, as long as the error detection control unit determines that the input trigger control signal is not an effective trigger control signal, that is, the trigger control signal is invalid, the thyristor switch group is started and is in a protection state while the trigger pulse for triggering the thyristor is not sent out; when the interlocking control unit outputs an effective trigger control signal to ensure that the thyristors at the same side in the self-coupling compensation type main circuit thyristor switch group are not conducted at the same time, the interlocking control of the thyristors is realized, and simultaneously, the system also outputs an invalid code value for other abnormal control logic errors including the analog-to-digital conversion fault or logic error of the analog-to-digital conversion coding unit, and when the interlocking control unit generates the logic error and outputs the invalid trigger control signal, the error detection control unit starts and enables the thyristor switch group to be in a protection state; when the thyristor switch group is in the protection state, if the error detection control unit judges that the self-coupling compensation type alternating current voltage stabilizer enters the normal logic control state again, namely the error detection control unit judges that the input trigger control signal is recovered to be the effective trigger control signal, the protection state of the thyristor switch group can be automatically stopped and the thyristor switch group is enabled to be in the compensation working state again. The function effectively strengthens the protection force aiming at the abnormal working in the voltage stabilizing process, so that the single-phase alternating current voltage stabilizing process is more stable and reliable.
In the above embodiments, all ROM memories, logic gates and logic function integrated circuits are powered by a positive single power supply + VCC. In addition to the technical features described in the specification, other techniques for implementing the control method of the self-coupled compensated ac voltage regulator of the present invention are conventional techniques known to those skilled in the art.