CN109213245B

CN109213245B - Partitioned self-coupling compensation type alternating current voltage stabilization control method

Info

Publication number: CN109213245B
Application number: CN201811355956.8A
Authority: CN
Inventors: 文定都; 凌云; 刘建华; 孔玲爽
Original assignee: Hunan University of Technology
Current assignee: Suzhou Descarte Technology Co.,Ltd.
Priority date: 2018-11-15
Filing date: 2018-11-15
Publication date: 2020-07-31
Anticipated expiration: 2038-11-15
Also published as: CN109213245A

Abstract

A partitioned auto-coupling compensation type alternating current voltage stabilization control method is realized by an alternating current voltage stabilizer which comprises an auto-coupling compensation type main circuit, a sampling comparison unit, a time delay protection unit, a trigger gating configuration unit, a trigger unit, an error detection judgment unit and a protection driving unit, wherein the auto-coupling compensation type main circuit comprises a compensation transformer, an auto-coupling transformer, a thyristor switch group and a relay protection switch. The trigger gating configuration unit outputs a trigger control signal according to the delayed trigger gating control value output by the sampling comparison unit, and the trigger control signal is sent to the trigger unit to control the on-off of the thyristors in the thyristor switch group. The method can adjust the partition number of the voltage in the fluctuation range of the input alternating-current power supply voltage, and change the compensation mode and the compensation precision; when the interlocking control is realized, the protection of the thyristor switch group is started/stopped according to whether the trigger gating control value is effective or not, the power supply of the trigger unit is controlled, and the protection force for the abnormity of the working process is effectively enhanced.

Description

Partitioned self-coupling compensation type alternating current voltage stabilization control method

Technical Field

The invention relates to the technical field of power supplies, in particular to a partitioned self-coupling compensation type alternating current voltage stabilization control method.

Background

The existing compensation type AC voltage stabilizer has the advantages of wide voltage stabilizing range, almost no distortion of waveform, high efficiency of the whole machine and strong load adaptability. The principle is that switching of different winding coils of a primary winding on a compensation transformer is automatically controlled according to the high-low condition of input voltage, bidirectional multi-gear voltage compensation is provided by utilizing the transformation ratio relation of a primary side working winding and a secondary winding or by adjusting the voltage applied to the primary winding, and therefore the purpose of voltage regulation and stabilization is achieved.

The existing compensation type alternating current voltage stabilizer has the defects that when a motor is used for controlling the movement of the carbon brush to change the situation that different voltages are applied to the excitation coil of the compensation transformer, the carbon brush is easy to wear and often fails, when an electronic switch switching mode is used for switching different winding coils of a primary winding on the compensation transformer, or when the voltage applied to the primary winding is adjusted, the delayed turn-off of the electronic switch is easy to cause a power supply short-circuit fault, when a program mode of a single chip microcomputer, P L C and the like is used for controlling the switching of the electronic switch, the problems of program runaway, dead halt and the like can also cause the failure of the voltage stabilizer, or the power supply short-circuit fault.

Disclosure of Invention

In order to solve the problems of the existing compensation type alternating current voltage stabilizer, the invention provides a control method of a partitioned self-coupling compensation type alternating current voltage stabilizer, which comprises the following steps:

adjusting the voltage in the alternating current power supply voltage fluctuation interval range into M voltage grade intervals; identifying a voltage grade interval of the alternating-current power supply voltage to obtain an M-bit trigger gating control value; configuring a configuration switch in a diode trigger configuration matrix, selecting and enabling a corresponding trigger control signal to be effective by the diode trigger configuration matrix according to an M-bit trigger gating control value, and controlling the on-off combination state of a thyristor in a thyristor switch group; the on-off combined state of the thyristors in the thyristor switch group controls and selects 0 or 1 or the superposition of a plurality of voltages in a plurality of output voltages of the autotransformer as the excitation coil voltage of the compensation transformer to realize the voltage compensation state corresponding to the voltage grade interval; each voltage grade interval of the alternating current power supply voltage corresponds to a voltage compensation state; m is not less than 3, and M is not less than 2 and not more than M.

The thyristor switch group is provided with N thyristors in total; the diode trigger configuration matrix comprises m trigger control row lines and N trigger drive column lines; the N triggering driving column lines correspond to the N thyristors one by one, and the signal of one triggering driving column line effectively corresponds to the triggering control signal of one thyristor; a configuration branch consisting of a diode and a configuration switch in series connection is arranged at the crossing position of each trigger control row line and each trigger driving column line, and the configuration switch can be connected in series with the cathode end of the diode or the anode end of the diode; when the trigger control row line signal is active at a low level, the cathode side of the diode of the configuration branch is connected to the trigger control row line, and the anode side of the diode of the configuration branch is connected to the trigger driving column line; when the trigger control row line signal is high level and effective, the anode side of the diode of the configuration branch is connected to the trigger control row line, and the cathode side of the diode is connected to the trigger drive column line; and N is greater than or equal to 4.

The configuration method of the configuration switch in the configuration branch circuit is that M of M trigger control row lines are selected as trigger gating control row lines; m triggering gating control row lines correspond to M bit triggering gating control values one by one, and an effective triggering gating control value correspondingly enables one triggering gating control row line to be effective; when each trigger gating control row line signal is effective, the on-off combination state of a thyristor in a corresponding thyristor switch group is corresponded; configuring a configuration switch in a configuration branch between each trigger gating control row line and a trigger driving row line which is in a corresponding on-off combination state and needs to control the conduction of a thyristor when a signal of the row line is effective into an on state; and configuring the configuration switches in the configuration branches between the trigger driving column lines of which the thyristors are required to be controlled to be turned off in a corresponding on-off combination state when the signals of each trigger gating control row line and the row line are effective into an off state.

And judging whether the trigger gating control value is effective or not, and controlling the thyristor switch group to be in a protection state when the trigger gating control value is ineffective. Triggering a gating control value to be an M-bit binary value; judging whether the trigger gating control value is effective or not according to the fact that the trigger gating control value is effective when one bit is effective in M-bit binary values of the trigger gating control value; otherwise, the trigger gating control value is invalid. Further, the bit in the trigger gating control value is 1 valid and 0 invalid, that is, the high level in the trigger gating control value signal is valid and the low level is invalid; or, the bit in the trigger gating control value is 0 valid and 1 invalid, that is, the low level in the trigger gating control value signal is valid and the high level is invalid; the M trigger gating control values are all effective, and M trigger gating control values are all effective.

And identifying the voltage grade interval of the alternating-current power supply voltage to obtain a trigger gating control value, wherein the trigger gating control value is realized by a sampling comparison unit. The sampling comparison unit comprises an alternating current power supply voltage sampling circuit and a multi-interval voltage comparator circuit, and the alternating current power supply voltage sampling circuit converts an alternating current power supply voltage effective value into an alternating current power supply voltage sampling value.

The multi-interval voltage comparator circuit comprises m-1 comparators, compares input voltage with m-1 different threshold voltages and outputs m-bit comparison output values; and m-1 comparators are all powered by a positive single power supply. m-1 different threshold voltages are respectively connected to the inverting input ends of m-1 comparators, and the input voltage is simultaneously connected to the non-inverting input ends of m-1 comparators. The high level of the m-bit comparison output values output by the multi-interval voltage comparator is effective, and only one of the m-bit comparison output values is effective. In m-1 comparators, the comparator with the highest threshold voltage is directly powered by a positive single power supply, and other comparators are powered by controllable power supplies; when the comparator is powered by the controllable power supply, the controllable power supply supplies power to the positive power supply end of the comparator only when all the comparators with the threshold voltages higher than the threshold voltages output low levels, otherwise, the controllable power supply stops supplying power to the positive power supply end of the comparator. The comparator adopts a controllable power supply to supply power, and outputs low level when the controllable power supply stops supplying power to the positive power supply end. The m-bit comparison output value consists of the output values of m-1 comparators and the minimum interval judgment value; and when all the output values of the m-1 comparators are at low level, the lowest interval judgment value is at high level, otherwise, the lowest interval judgment value is at low level.

The voltage within the alternating current power supply voltage fluctuation interval range is adjusted into M voltage grade intervals, and the voltage level intervals are realized by adjusting the parameters of the sampling comparison unit; further, the method is realized by adjusting parameters of the multi-interval voltage comparator circuit. The multi-interval voltage comparator circuit also comprises a multi-threshold voltage output circuit consisting of an upper threshold potentiometer, a lower threshold potentiometer and a plurality of intermediate voltage-dividing resistors, and m-1 different threshold voltages are provided for m-1 comparators. Adjusting the parameter values of the upper threshold potentiometer and the lower threshold potentiometer, and adjusting the voltage in the alternating current power supply voltage fluctuation interval range into M voltage grade intervals, wherein the M voltage grade intervals correspond to M effective M-bit trigger gating control values output by the sampling comparison unit one by one; the M-bit trigger gating control value consists of the lower M bits in the M-bit comparison output value, namely the M-bit trigger gating control value consists of the output of M-1 comparators with the lowest threshold voltage in the multi-interval voltage comparator circuit and the lowest interval judgment value. The M-1 lowest threshold voltages are respectively voltage sampling values of alternating current power supply voltage values separating M voltage class intervals.

When the comparator is powered by a controllable power supply, the output end of the comparator is connected with a pull-down resistor, the controllable power supply supplies power to the positive power supply end of the comparator only when all the comparators with the threshold voltages higher than the threshold voltages output low levels, and otherwise, the controllable power supply stops supplying power to the positive power supply end of the comparator. The positive power supply end of the comparator is connected to the output end of the NOR gate, and the input end of the NOR gate is respectively connected to the output ends of the comparators with the threshold voltages higher than that of the NOR gate.

The comparators in the multi-interval voltage comparator circuit preferably adopt a low-power-consumption rail-to-rail operational amplifier powered by a single power supply.

When the trigger gating control value changes and the thyristors in the thyristor switch group need to be switched to be in different on-off combination states, maintaining a non-trigger area time between the 2 on-off combination states, and turning off all the thyristors in the thyristor switch group.

The maintaining of the one non-trigger area time is realized by a non-trigger area control signal; controlling the control signal of the non-trigger area to output a single pulse after the trigger gating control value is changed; the control signal of the non-trigger area is effective in the period of outputting the single pulse and is ineffective in the period of not outputting the single pulse; and when the control signal of the non-trigger area is effective, maintaining a time of the non-trigger area. Further, after the trigger gating control value is changed, the width time of a single pulse in the non-trigger area control signal is selected from 10ms to 30 ms.

The trigger control signal for controlling the thyristor switch group is generated by the delayed trigger gating control value; the delayed signal change time of the trigger gating control value is later than the leading edge time of a single pulse in the non-trigger area control signal after the trigger gating control value is changed and earlier than the trailing edge time of the single pulse in the non-trigger area control signal after the trigger gating control value is changed.

The functions of delaying the trigger gating control value output by the sampling comparison unit and generating a control signal of a non-trigger area are realized by a delay protection unit; the error detection judging unit is used for inputting the delayed trigger gating control value, judging whether the delayed trigger gating control value is effective or not and outputting a trigger gating control value judging signal.

The method is realized by an alternating current voltage stabilizer comprising a self-coupling compensation type main circuit, a sampling comparison unit, a time delay protection unit, a trigger gating configuration unit, a trigger unit, an error detection judgment unit and a protection driving unit. The auto-coupling compensation type main circuit comprises a compensation transformer, an auto-coupling transformer, a thyristor switch group and a relay protection switch; the trigger unit controls the on-off of the thyristors in the thyristor switch group of the main circuit according to the input trigger control signal. The protection driving unit stops/starts the protection of the thyristor switch group according to whether the trigger gating control value is effective or not; when the thyristor switch group is in a protection state, and the error detection judging unit judges that the input trigger gating control value is recovered to be effective, the protection driving unit automatically stops the protection state of the thyristor switch group.

The trigger gating configuration unit comprises a diode trigger configuration matrix. The method for enabling the trigger control signal of the thyristor to be effective by enabling the trigger driving column line signal to be effective correspondingly is characterized in that N trigger driving column line signals are directly used as the trigger control signals of N thyristors in a one-to-one correspondence manner; a trigger driving column line signal is effective and corresponds to a method for enabling a trigger control signal of a thyristor to be effective, or the trigger gating configuration unit further comprises a trigger control signal driving circuit; the input of the trigger control signal driving circuit is N signals for triggering and driving the column lines, and the output is trigger control signals of N thyristors in one-to-one correspondence.

The protection driving unit controls the power supply of the triggering unit according to whether the triggering gating control value is effective or not and whether the control signal of the non-triggering area is effective or not, and the specific method is that only when the triggering gating control value is effective and the control signal of the non-triggering area is ineffective, the power supply of the triggering unit is controlled to be switched on, the triggering unit works normally, and triggering pulse is sent out according to the input triggering control signal; otherwise, the power supply of the trigger unit is cut off, and all trigger pulses are stopped to be sent out.

The thyristors in the thyristor switch group are bidirectional thyristors or thyristor alternating current switches formed by connecting 2 unidirectional thyristors in reverse parallel.

The partitioned auto-compensation type AC voltage stabilizing control method has the advantages that the number of partitions of voltage in the fluctuation range of input AC power supply voltage can be adjusted, the compensation mode and the compensation precision are changed, different configurations are carried out on a diode trigger configuration matrix to adapt to different partition numbers and compensation modes, the partitioned auto-compensation type AC voltage stabilizing control method ensures that thyristors on the same side in a thyristor switch group are not conducted at the same time by adopting the diode trigger configuration matrix, interlocking control of the thyristors is achieved, meanwhile, when voltage grade intervals of the AC power supply voltage are identified, errors occur, invalid trigger gating control values are output, trigger pulses are stopped to be sent out, the thyristor switch group is protected, the protection strength for abnormity of the AC voltage stabilizing working process is effectively enhanced, when the thyristor switch group is in a protection state, if the trigger gating control values are recovered to be valid, the protection state of the thyristor switch group can be automatically stopped and is enabled to be in a compensation working state again, program modes such as a single chip microcomputer and P L C are not adopted to control on-off switching of the thyristors, and the on-off switching of the thyristor is controlled, and the voltage stabilizing working process of the partitioned auto-compensation type AC voltage stabilizing control method is more.

Drawings

FIG. 1 is a block diagram of an AC voltage regulator implementing a partitioned auto-coupled compensation type AC voltage regulation control method;

FIG. 2 shows an embodiment of a self-coupled compensated main circuit 1;

FIG. 3 illustrates an embodiment of a self-coupled compensated main circuit 2;

FIG. 4 shows a sample comparison unit of example 1;

FIG. 5 shows a sample comparison unit of example 2;

FIG. 6 is a block diagram of an embodiment of a delay protection unit;

FIG. 7 is a diagram of an embodiment of a delay detection circuit 1 of the delay detection module for triggering the strobe control value signal Y10;

FIG. 8 is a circuit diagram of embodiment 2 of the delay detection circuit for triggering the strobe control value signal Y10 in the delay detection module;

FIG. 9 is a block diagram of an embodiment of a delay detection circuit 3 for triggering the strobe control value signal Y10 in the delay detection module;

FIG. 10 is a block diagram of an embodiment of a no trigger area control signal generation module;

FIG. 11 is a diagram illustrating a partial correlation waveform in the delay protection unit;

FIG. 12 is an embodiment of a trigger circuit for triggering the triac SR1 in the trigger unit;

FIG. 13 shows an embodiment of a trigger strobe configuration unit 1;

FIG. 14 shows an embodiment of a trigger strobe configuration unit 2;

FIG. 15 shows an error detection and determination unit in embodiment 1;

FIG. 16 shows an error detection and discrimination unit in embodiment 2;

fig. 17 is a protection drive unit embodiment.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

Fig. 1 is a block diagram of an ac voltage regulator implementing a partitioned self-coupling compensation type ac voltage stabilization control method, in which a sampling comparison unit samples the voltage of an ac power supply and outputs a trigger gating control value P2; the delay protection unit inputs a trigger gating control value P2 and outputs a delayed trigger gating control value P3 and a non-trigger area control signal P4; the trigger gating configuration unit inputs the delayed trigger gating control value P3 and outputs a trigger control signal P5; the trigger unit sends a trigger signal P6 to the self-coupling compensation type main circuit according to an input trigger control signal P5 to control the on-off of the bidirectional thyristor in the thyristor switch group; the error detection judging unit inputs the delayed trigger gating control value P3 and outputs a trigger gating control value judging signal P7; the protection driving unit inputs a non-trigger area control signal P4 and a trigger gating control value judging signal P7, stops/starts protection of the thyristor switch group according to whether the trigger gating control value judging signal P7 is effective, and controls the power supply of the trigger unit according to whether the trigger gating control value judging signal P7 is effective and whether the non-trigger area control signal P4 is effective.

Fig. 2 is an embodiment 1 of the self-coupling compensation type main circuit, which comprises a compensation transformer TB1 and a self-coupling transformer TB2, wherein 6 bidirectional thyristors SR1-SR6 jointly form a thyristor switch group, and a fuse FU1, a relay normally-open switch KA-1 and a relay normally-closed switch KA-2 form a relay protection circuit.

In FIG. 2, a compensation coil of a compensation transformer TB is connected in series on a phase line, the input end of the phase line is A, the output end of the phase line is A2, the voltage on a magnet exciting coil is A2, the output end of the magnet exciting coil is A2, the voltage on the magnet exciting coil is controlled by a thyristor switch group, the autotransformer TB has 3 output taps C, C and C, one ends of the bidirectional thyristors SR, SR and SR are connected in parallel and then connected to the other end of the magnet exciting coil, the other ends of the SR, SR and SR are connected to the taps C, C and U respectively, the output voltage U of the autotransformer TB is low and U is high, the voltage U is 2 times of the voltage U, the switch group has 6 voltage compensation modes of the forward U, the forward U + U, the reverse U + U, an input voltage of the magnet exciting coil is in a0 voltage compensation mode when the input voltage is within a normal range, the phase line voltage input end A of the compensation thyristor can be divided into 7 voltage intervals to carry out compensation, N2, the thyristor is controlled in the compensation thyristor, the phase line, the two thyristors G, the SR, the signal can not be conducted to the same side, the same as the SR, the signal can be conducted, the signal of the same as the signal of the bidirectional thyristor, the signal of the thyristor, the bidirectional thyristor, the same side of the same as the SR, the same as the SR.

FIG. 3 shows an embodiment 2 of the auto-coupling compensation type main circuit, which includes a compensation transformer TB1 and an auto-coupling transformer TB2, 8 bidirectional thyristors SR1-SR8 jointly form a thyristor switch group, and a fuse FU1, a relay normally-open switch KA-1 and a relay normally-closed switch KA-2 form a relay protection circuit.

In FIG. 3, a compensation coil of a compensation transformer TB1 is connected in series with a phase line, an input end of the phase line is L A1, an output end of the phase line is L A2. TB1 voltage on an excitation coil is controlled by a thyristor switch group, an autotransformer TB2 has 4 output taps C1, C2, C3 and C4, bidirectional thyristors SR1, and SR1 are connected in parallel to one end of the excitation coil of the TB1, the other ends of the SR1, SR1 and SR1 are respectively connected to one end of the excitation coil of the TB1, C1 and C1, C1 and C1, the other ends of the thyristors 72, SR1 and SR1 are respectively connected to the input ends of the thyristors of the forward thyristors C1, C + 7 and the forward switch 72, the reverse thyristors 72, the SCR 72, the forward switch and the forward switch 72, the SCR 72, the forward switch and the reverse switch are respectively connected to the normal switch 1, the forward switch 1, the reverse switch 1, the forward switch is connected between the forward switch 1, the forward switch is connected to the normal switch 1, the reverse switch is connected 1, the normal switch 1, the reverse switch is connected 1, the reverse switch is connected between the SR1, the reverse switch is connected 1, the normal switch is connected between the normal switch 1, the reverse switch is connected 1, the normal switch is connected when the SR1, the reverse switch is connected 1, the SR1, the forward switch is connected.

Each of the triacs of fig. 2 and 3 may be replaced by 2 antiparallel triacs. In fig. 2 and 3, the relay normally open switch and the relay normally closed switch form a relay protection switch.

Adjusting the voltage in the alternating current power supply voltage fluctuation interval range into M voltage grade intervals, sampling the alternating current power supply voltage by a sampling comparison unit to obtain an alternating current power supply voltage sampling value, comparing the alternating current power supply voltage sampling value by M or M-1 comparators, and outputting a trigger gating control value formed by M binary digits; when the alternating current power supply voltage is in one of the M voltage grade intervals, the M bits trigger the corresponding one bit in the gating control value to be valid, and the other bits are invalid. The effective bit of the M bit trigger gating control value is high level, namely binary 1; the invalid bit is low level, i.e. binary 0; or, the effective bit of the M-bit trigger gating control value is low level, namely binary 0; the invalid bit is high, i.e. binary 1.

Fig. 4 shows an embodiment of a sampling comparison unit 1, where m is equal to 7, and compensation control is performed on the embodiment 1 of the self-coupling compensation type main circuit, in an ac power supply voltage sampling circuit, ac power supply voltages input from a phase line L a1 and a zero line N are stepped down by a transformer TV, rectified by a rectifier bridge composed of diodes DV1-DV4, filtered by a capacitor CV1, and divided by resistors RV1 and RV2, so as to obtain an ac power supply voltage sampling value U1 in a direct proportional relationship with an effective value of the input ac power supply voltage.

In the multi-interval voltage comparator circuit shown in fig. 4, an upper limit threshold potentiometer RPH, a lower limit threshold potentiometer RP L and intermediate voltage-dividing resistors RF2-RF6 form a voltage-dividing circuit, after voltage division is performed on a power supply + VCC1, 6 threshold voltages UF2-UF7 are 6 intermediate divided voltage values of voltage sampling values corresponding to alternating-current power supply voltage values divided by 7 voltage-level intervals, 6 comparators FA2-FA7 realize comparison of the alternating-current power supply voltage sampling values U1 and 6 threshold voltages UF 2-2, 7-bit comparison output values of the multi-interval voltage comparator circuit are composed of output Y2-Y2 of the 6 comparators FA2-FA 2 and a lowest interval judgment value Y2, the voltage of the alternating-current power supply voltage fluctuation interval is divided into 7 voltage-level intervals 1-7, the alternating-current power supply voltage U2 is simultaneously sent to a non-inverting input end of the comparators FA2-FA 2, the 6 threshold voltages RP 72-FA are respectively sent to an inverted power supply voltage-FA voltage-2, the power supply voltage-ac power supply voltage-FA 2, the power supply voltage-FA voltage-b 2, the power supply circuit can be replaced by a single voltage-FA voltage divider circuit, the optimal single voltage-FA power supply circuit, the power supply circuit can be replaced by a power supply circuit, the optimal single voltage-FA power supply circuit, the optimal voltage.

In FIG. 4, the NOR gates FH2-FH6 constitute controllable power supplies for the comparators FA2-FA6, i.e., the power supplies for the comparators FA2-FA6 are controlled by the outputs Y13-Y17, respectively; the resistors RB2-RB6 are pull-down resistors of the outputs Y12-Y16 respectively, and when the power supply of the corresponding comparator is close to 0V and the output of the corresponding comparator is in a high-impedance state, the level is pulled to be low. The power supply of the comparator FA7 is connected to the power supply + VCC1, and is in a normal working state, and the output Y17 controls the power supplies of the comparators FA2-FA 6. For example, when the voltage of the input alternating-current power supply is high and is in the highest voltage class section 7 of 7 voltage class sections, Y17 outputs high level, all the outputs of NOR gates FH2-FH6 are low level, all the single-power-supply power supplies of comparators FA2-FA6 are close to 0V, all the outputs are close to 0V or high-impedance state, and resistors RB2-RB6 respectively pull the outputs Y12-Y16 to low level. When the input alternating current power supply voltage is not in the highest voltage grade interval 7 of the 7 voltage grade intervals, Y17 outputs low level, NOR gate FH6 outputs high level to provide power supply for comparator FA6, at the moment, if the input alternating current power supply voltage is in the voltage grade interval 6, Y16 outputs high level, NOR gates FH2-FH5 all output low level, single power supply of comparators FA2-FA5 all approach 0V, the output all approach 0V or high impedance state, and resistors RB2-RB5 respectively pull the output Y12-Y15 low level. When the input alternating current power supply voltage is lower than the voltage grade interval 6, Y17 and Y16 both output low level, NOR gates FH6 and FH5 both output high level, and power supplies are respectively provided for comparators FA6 and FA5, at this time, if the input alternating current power supply voltage is in the voltage grade interval 5, Y15 outputs high level, NOR gates FH2-FH4 all output low level, single power supplies of comparators FA2-FA4 are all close to 0V, the outputs are all close to 0V or high resistance state, and resistors RB2-RB4 respectively pull the outputs Y12-Y14 low level. By analogy, when the input alternating-current power supply voltage is in the voltage class interval 4, the Y14 outputs high level, and other outputs are low level; when the input alternating current power supply voltage is in a voltage class interval 3, Y13 outputs high level, and other outputs are low level; when the input alternating current power supply voltage is in a voltage class interval 2, Y12 outputs high level, and other outputs are low level; only when the input ac power supply voltage is at or below the voltage class section 1, the outputs Y12 to Y17 of the comparators FA2 to FA7 are all at the low level, and the lowest section determination value Y11 of the nor gate FH1 is made at the high level. When the nor gate FH1-FH6 selects a 74HC series high-speed CMOS gate, for example, when the 8-input nor gate 74HC4078, the three-input nor gate 74HC27, the four-input nor gate 74HC02, etc. are selected, or when the nor gate function is realized by a 74HC series high-speed CMOS or nor gate, the high-level driving current of the 74HC series high-speed CMOS can reach 4mA, which is enough to drive a single-channel rail-to-rail operational amplifier with the static operating power supply current less than 1 mA. The power supply of the NOR gate FH1-FH6 is power supply + VCC 1.

The method comprises the steps of setting an input alternating current power supply voltage fluctuation range to be 220V +/-10%, requiring the input alternating current power supply voltage fluctuation range to be stabilized within a range of 220V +/-2% for output, adopting an embodiment 1 of a sampling comparison unit in fig. 4, dividing voltages input between 242V and 198V into 7 voltage class intervals with interval voltage size of 8V, namely M is equal to 7, integrally forming a trigger gating control value P2 by Y11-Y17 included in 7-bit comparison output values, wherein 3 voltage class intervals are higher than a required output voltage range and need to be subjected to voltage reduction compensation, 3 voltage class intervals are lower than a required output voltage range and need to be subjected to voltage boosting compensation, 1 voltage class interval is within a required output voltage range, namely 0 voltage compensation is carried out, namely, the voltage interval of the 8V is about 220V +/-1.82%, the requirement of output control within 220V +/-2% is met, when the voltage fluctuation of an alternating current power supply voltage reaches a required threshold voltage UF range of 7V 34V, a threshold voltage UF 14V, a threshold voltage selected from an effective value of an excitation coil voltage UF 72V, a sampling value of an excitation coil 72V, a sampling interval of an excitation coil 72V, a sampling value UF 72V, a sampling value V, an excitation coil 72V, an excitation coil voltage interval of an excitation coil voltage, an.

The method comprises the steps of setting an input alternating current power supply voltage fluctuation range to be 220V +/-10%, enabling the fluctuation range to be stabilized within a range of 220V +/-4% to be output, reducing the number of voltage intervals, and avoiding frequent adjustment, adopting an embodiment 1 of a sampling comparison unit of a power supply 4, dividing a voltage input between 242V and 198V into 3 voltage level intervals with an interval voltage size of 16V, wherein M is equal to 3, wherein the voltage of 1 voltage level interval is higher than the required output voltage range and needs to be subjected to voltage reduction compensation, the voltage of 1 voltage level interval is lower than the required output voltage range and needs to be subjected to voltage boosting compensation, carrying out voltage compensation within 1 voltage level interval, namely, the voltage interval of the alternating current power supply 72V is not compensated, namely, the voltage interval of the alternating current power supply 72V is about 220V +/-3.64%, the requirement of output control within 220V +/-4% is met, the fluctuation of the alternating current power supply voltage corresponding to the 3 voltage intervals of the 3 voltage classes of 16V is 244V to 196V, the fluctuation range of the alternating current power supply voltage UF 52V, the alternating current power supply 72V 52V, the alternating current power supply voltage is equal to 3V, the maximum output of a power supply voltage UF 72V 52V, the power supply voltage equivalent to the maximum value of a power supply voltage equivalent to the power supply voltage equivalent to be equal to the maximum output voltage of the power supply voltage equivalent to be equivalent to the maximum value of the maximum power supply voltage equivalent to be equivalent to the maximum value of the maximum power supply voltage equivalent to the maximum power supply voltage of the power supply voltage equivalent to the maximum power supply voltage equivalent to the maximum power supply voltage equivalent to the maximum power supply voltage.

Since the compensation mode of the self-coupled compensation type main circuit embodiment 1 automatically has the schmitt characteristic, the comparator FA2 to the comparator FA7 do not constitute a schmitt comparator. The trigger strobe control value output in FIG. 4 is active high; the output end of each of the comparators FA2-FA7 is added with a stage of inverter, and the NOR gate FH1 is changed into an OR gate, so that the output trigger gating control value is changed into low level and effective.

Embodiment 1 of fig. 4 can also be performed for the self-coupled compensation type main circuit embodiment 2, and in this case, the voltage in the fluctuation interval range of the ac power supply voltage needs to be divided into more voltage class intervals. For example, when the voltage in the fluctuation interval of the ac power supply voltage is divided into 13 voltage class intervals, the circuit of fig. 4 should be extended to 12 comparators for comparison with 12 threshold voltages of different sizes; the output trigger strobe control value P2 will consist of 13 bits, e.g., Y11-Y113.

Fig. 5 shows an embodiment 2 of the sampling comparison unit, where m is equal to 10, and is used to perform compensation control on the self-coupling compensation main circuit embodiment 2, in fig. 5, FD1 is a true effective value detection device L TC1966, L TC1966, a transformer TV1, a capacitor CV2, and a capacitor CV3 form an ac power supply voltage sampling circuit, and ac power supply voltages input from a phase line L a1 and a zero line N are measured to obtain ac power supply voltage sampling values U2, UIN1, UIN2 of L TC1966 are ac voltage differential input terminals, USS is a negative power supply input terminal that can be grounded, UDD is a positive power supply input terminal, GND is a ground terminal, EN is a low-level effective enable control input terminal, UOUT is a voltage output terminal, and COM is an output voltage return terminal.

In fig. 5, FD2, RD1 and RD2 form a multi-interval voltage comparator circuit, FD2 is a 10-stage comparison display driver L M3914, an internal voltage divider circuit with 10 1k Ω precision resistors connected in series is provided therein, 10 comparison threshold voltages are formed and connected to the positive input terminals of the 10 internal comparators, the voltage within the fluctuation interval of the ac power voltage is divided into 10 voltage class intervals 1-10.6, which are the high terminals of the internal voltage divider circuit, and connected to power supply + VCC1 through an upper threshold potentiometer RD1, 4, which are the low terminals of the internal voltage divider circuit, which are connected to ground through a lower threshold potentiometer RD2, 8, which is the low terminal of an internal standard power supply, which is connected to ground, 2, which is the negative terminal, 3, which is a positive terminal, which is connected to power supply + VCC1, 5, which is a signal input terminal, which is connected to ac power supply voltage U2, which is internally connected to the negative input terminals of 10 comparators, 10-18, 1, the output voltage Y110 to Y11, which is the result of the comparison with 10 comparators, and Y2, when the ac voltage is in the low voltage level, the other low voltage level, the ac voltage is output voltage, the ac voltage is in turn, the low voltage output level, when the other low voltage level, the ac voltage is in other low voltage class intervals, the ac voltage output voltage is in other valid levels, the ac voltage range, the ac voltage output level interval, Y voltage output level is in no more than Y voltage range, no more than Y9, No. 3, no more than Y9, No. 3, No. Y9.

The voltage fluctuation range of an input alternating current power supply is 220V + 10% to 220V-20%, the voltage fluctuation range is required to be stabilized within the range of 220V +/-2% to be output, the sampling comparison unit embodiment 2 of FIG. 5 is adopted, the voltage input between 242V and 176V is divided into 10 voltage class intervals with the interval voltage size of 7V, namely M is equal to 10, a trigger gating control value P is integrally formed by Y-Y110 included in 10 comparison output values, the voltage of 3 voltage class intervals is higher than the required output voltage range and needs to be subjected to voltage reduction compensation, the voltage of 6 voltage class intervals is lower than the required output voltage range and needs to be subjected to voltage boosting compensation, 1 voltage class interval is within the required output voltage range, namely 0 voltage compensation is carried out, namely, the voltage interval of 7V is 220V +/-1.6%, the requirement of output control within 220V +/-2% is met, the voltage interval corresponding to 10 voltage class intervals is 244.5V to be subjected to voltage compensation, the fluctuation control, the voltage fluctuation range of the alternating current source voltage TB is equal to the standard voltage TB 2V + 14V + V.

In embodiment 2 of the sampling comparing unit in fig. 5, when the input ac power voltage is higher than the range of the maximum voltage class interval, the output trigger strobe control value is valid for the output signal corresponding to the maximum voltage class interval, that is, the output is valid for Y110, and the main circuit performs corresponding voltage step-down compensation according to the ac power voltage in the maximum voltage class interval. When the input alternating current power supply voltage is lower than the range of the minimum voltage grade interval, all signals in the output trigger gating control value are invalid, and the main circuit does not perform voltage compensation at the moment.

In fig. 5, 10 comparators in L M3914 internal 10 comparators are used to divide the ac power supply voltage comparison into 10 voltage class intervals, only 9 comparators in L M3914 internal 10 comparators may be used to divide the ac power supply voltage comparison into 10 voltage class intervals, the comparison threshold voltages of the 9 comparators are 9 intermediate division voltage values of the voltage sampling values corresponding to the ac power supply voltage values divided by 10 voltage class intervals, for example, the comparison threshold voltages of the comparators are not changed, the output of pin 1 of L M3914 in fig. 5 is not used as Y11, Y11 selects the trigger control value generated by Y12-Y110 control in the trigger gate control value, that is, Y12-Y110 is all invalid, Y11 is valid, otherwise, Y11 is invalid, when the input ac power supply voltage is in or exceeds the maximum voltage class interval, the output trigger control value is Y110 valid, the main circuit performs the corresponding voltage compensation according to the ac power supply voltage class interval, and when the input voltage is in or exceeds the maximum voltage class interval, the corresponding ac power supply voltage compensation is performed according to the minimum voltage input voltage range, and when the input voltage compensation is performed according to the minimum voltage class interval, the input voltage compensation performed according to Y11.

The method comprises the steps of setting the fluctuation range of an input alternating current power supply voltage to be 220V +/-15%, requiring the input alternating current power supply voltage to be stabilized in the range of 220V +/-3.5% for output, reducing the requirement on voltage stabilization precision, reducing the number of voltage intervals to avoid frequent adjustment, adopting an embodiment 2 of a sampling comparison unit of the alternating current power supply 5, dividing the voltage input between 253V and 187V into 5 voltage level intervals with the interval voltage size of 14V, namely M is equal to 5, wherein the voltage of 2 voltage level intervals is higher than the required output voltage range and needs to be subjected to voltage reduction compensation, the voltage of 2 voltage level intervals is lower than the required output voltage range and needs to be subjected to compensation, 1 voltage level interval is within the required output voltage range, carrying out voltage compensation, namely, uncompensated, 14V is smaller than 220V +/-3.2%, the requirement of output control within 220V +/-3.5% is met, the fluctuation range of the alternating current power supply voltage corresponding to the fluctuation range of 255V to 185V, covering the actual range of voltage of the alternating current power supply 3V, the sampling range of the sampling coil is equivalent to 220V +/-26.85V, the voltage of a sampling value of a sampling transformer 57V, the sampling interval of a sampling value of a sampling transformer 7V, the sampling value of a sampling.

The sampling comparison unit embodiment 2 in fig. 5 can also perform compensation control on the self-coupling compensation type main circuit embodiment 1, and at this time, only the voltages within the fluctuation interval range of the input ac power voltage need to be divided into intervals of no more than 7 voltage levels, that is, the comparison output of no more than 7 levels is selected.

In addition to the sampling comparison unit embodiment shown in fig. 4 or 5, when compensation control is performed on the self-coupled compensation type main circuit embodiment 1 or embodiment 2, another ac power supply voltage sampling circuit and comparison circuit may be selected to implement the required functions. The ac power voltage sampling value U1 output by the ac power voltage sampling circuit of fig. 4 may be sent to the multi-interval voltage comparator circuit of fig. 5 for comparison, and a trigger gating control value is output; the sampled value U2 of the ac power voltage output by the ac power voltage sampling circuit of fig. 5 may be sent to the multi-interval voltage comparator circuit of fig. 4 for comparison, and a trigger gating control value is output.

FIG. 6 is a block diagram of an embodiment of a delay protection unit, wherein a delay detection module YC1 respectively performs signal delay on input signals Y11-Y1M including M-bit trigger strobe control values Y11-Y1M to obtain delayed signals Y21-Y2M, and Y21-Y2M therein form a delayed trigger strobe control value P3; the YC1 module simultaneously and respectively carries out edge detection on the input signals Y11-Y1m to obtain edge detection signals Y31-Y3 m; the triggerless area control signal generation module YC2 inputs the edge detection signals Y31-Y3M, and converts the edge variation in the M-bit trigger gate control value Y11-Y1M into a triggerless area control signal P4 for output. In the block diagram of the embodiment in fig. 6, when the input of the delay detection module YC1 is the trigger gating control value output by the embodiment 1 of the sampling comparison unit in fig. 4, m is equal to 7; in the block diagram of the embodiment in fig. 6, when the input of the delay detection module YC1 is the trigger gating control value output by the embodiment 2 of the sampling comparison unit in fig. 5, m is equal to 10.

Fig. 7 shows an embodiment 1 of a delay detection circuit for the input signal Y11 in the delay detection module. The resistor RY0, the capacitor CY0 and the driving gate FY0 realize signal delay of Y11, and a delayed signal Y21 of Y11 is obtained. The resistor RY1, the capacitor CY1, the diode DY1 and the inverter FY1 form a rising edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is output in the output signal YP1 of the inverter FY 1. The resistor RY2, the capacitor CY2, the diode DY2, the inverters FY2 and FY3 constitute a falling edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the falling edge of Y11 is output in the output signal YP2 of the inverter FY 3. The nand gate FY4 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY4, that is, when the input signal Y11 changes, the nand gate FY4 outputs a single pulse in the form of a positive pulse. In fig. 7, the drive gate FY0, inverter FY1, inverter FY3 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; the drive gate FY0 may consist of 2 inverters with schmitt inputs.

Fig. 8 shows an embodiment 2 of the delay detection circuit for the input signal Y11 in the delay detection module. The inverter FY5, the resistor RY3 and the capacitor CY3 invert and delay the input signal Y11 to obtain a delayed inverted signal YP0 of Y11; the inverter FY6 inverts YP0 to obtain a delayed Y11 signal Y21. The signal input by the nand gate FY7 is a delayed inverted signal YP0 of Y11 and Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is generated in the output signal YP 1; the or gate FY8 receives the inverted signals YP0 of Y11 and Y11, and the output signal YP2 generates a single pulse in the form of a negative pulse corresponding to the falling edge of Y11. The nand gate FY9 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY9, that is, when the input signal Y11 changes, the nand gate FY9 outputs a single pulse in the form of a positive pulse. In fig. 8, inverter FY6, nand gate FY7, or gate FY8 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; nand gate select 74HC132, CD4093, etc.; or gate select 74HC7032 or 2 inverters with schmitt inputs and 1 nand gate to implement the or gate function.

Fig. 9 is a delay detection circuit embodiment 3 for the input signal Y11 in the delay detection module, wherein a rising edge detection circuit for the input signal Y11 is composed of the resistor RY1, the capacitor CY1, the diode DY1 and the inverter FY1, and a falling edge detection circuit for the input signal Y11 is composed of the resistor RY2, the capacitor CY2, the diode DY2, the inverter FY2 and the inverter FY3, and a circuit for outputting the edge detection signal Y31 by using the nand gate FY4 is the same as in embodiment 1 of fig. 7. In fig. 9, the signal delay of Y11 is realized by inverters FY11, FY12, FY13, and FY14, and a delayed signal Y21 of Y11 is obtained.

The delay detection circuits of the embodiments 1 to 3 in fig. 7, 8 and 9 are all delay detection circuits for the input signal Y11, and the delay detection circuits for the other signals Y12-Y1m have the same circuit structure and function as those of the corresponding embodiments for performing delay detection on the input signal Y11. The delay detection circuit may also adopt other circuits meeting the requirements to realize the functions thereof.

The function of the no-trigger area control signal generation module is to output a single pulse in the no-trigger area control signal when any one or more of the input edge detection signals for triggering the strobe control value generate a single pulse related to an edge. FIG. 10 is a non-trigger area control signal generating module embodiment, in which a circuit including m input NOR gates FY10, m pull-down resistors Rz1-Rzm, and m edge-detecting signal gate switches z1-zm is used to implement corresponding functions, m bit edge-detecting signals Y31-Y3m are respectively connected to m input terminals of the NOR gates FY10 via the edge-detecting signal gate switches z1-zm, and the pull-down resistors RZ1-RZm are used to pull down the corresponding input signals of the NOR gates FY10 to a low level when a certain one of the edge-detecting signal gate switches z1-zm is open; the nor gate FY10 outputs the no trigger area control signal P4. In the embodiment of fig. 10, the single pulse that does not trigger the output of the zone control signal is a negative pulse, i.e., the low level of the zone control signal is not active; when the nor gate FY10 is replaced by an or gate, the single pulse that does not trigger the zone control signal output is a positive pulse. If the single pulse associated with an edge generated in the input edge detection signals Y31-Y3M is a negative pulse, the nor gate FY10 in fig. 10 should be changed to a nand gate or an and gate to implement an or logic function under negative logic.

The m-bit comparison output values output by the sampling comparison unit are all sent to the m-bit input end of the delay protection unit; the M edge detection signal gating switches z1-zm are used for connecting M bit trigger gating control values in M bit comparison output values to the input end of the NOR gate FY10, and when M is smaller than M, redundant input signals are not connected to the input end of the NOR gate FY 10; for example, when M equals 7 and M also equals 7, the edge detection signal gate switches z1-z7 are all turned on; when M is equal to 7, and M is equal to 3, the edge detection signal gating switch z1-z3 is turned on, z4-z7 is turned off, and the pull-down resistor RZ4-RZ7 pulls down the signal at the input end of the NOR gate FY10 behind the switch z4-z7 to low level, and at the moment, the non-trigger area control signal is generated by edge change in Y11-Y13. In embodiments 1 and 2 of the sampling comparison unit, when M is smaller than M, other data in M-bit data except the M-bit trigger strobe control value does not change, for example, when M is equal to 3 in embodiment 1 of the sampling comparison unit, the remaining 4 bits output a constant low level, and no edge detection signal is generated; when M is equal to 5 in embodiment 2 of the sampling comparison unit, the output of the remaining 5 bits is a constant high level, and no edge detection signal is generated; therefore, when M is smaller than M, even if all of the M-bit edge detection signals Y31-Y3M are connected to the input terminal of the nor gate FY10, the signals other than the M-bit trigger gate control value in the M-bit comparison output value do not cause a single pulse to be output in the no-trigger area control signal; therefore, when the sampling comparison unit in embodiment 1 or embodiment 2 is used to output m-bit comparison output values, the m pull-down resistors Rz1-Rz m and the m edge detection signal gate switches z1-zm in fig. 10 may not be used, and the m-bit edge detection signals Y31-Y3m are directly and entirely connected to the input terminal of the nor gate FY 10.

All gates in the delay protection unit are powered by a single power supply + VCC 1. Fig. 11 is a schematic diagram of a partial correlation waveform in the delay protection unit. From the principle and requirements of the sampling comparison unit, when the output trigger strobe control value is changed normally, 2 bits are changed every time. In fig. 11, Y11 in the trigger strobe control values has a rising edge change and a falling edge change respectively, and Y21 is the trigger strobe control value of Y11 delayed by T1 time; in embodiment 1 of the delay detection circuit in fig. 7, T1 is determined by the magnitude of the product of the resistor RY0 and the capacitor CY0 (i.e., the magnitude of the time constant); in embodiment 2 of the delay detection circuit in fig. 8, T1 is determined by the product of the resistor RY3 and the capacitor CY 3; in the embodiment 3 of the delay detection circuit in fig. 9, T1 is determined by the gate delay time of the inverters FY11, FY12, FY13 and FY 14. In fig. 11, the negative pulse width of the signal YP1 due to the rising edge of Y11 is T2; in the delay detection circuit embodiment 1 of fig. 7 and the delay detection circuit embodiment 3 of fig. 9, T2 is determined by the magnitude of the product of the resistor RY1 and the capacitor CY 1; in embodiment 2 of the delay detection circuit in fig. 8, T2 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 11, the negative pulse width generated by the falling edge of Y11 in the signal YP2 is T3; in the delay detection circuit embodiment 1 of fig. 7 and the delay detection circuit embodiment 3 of fig. 9, T3 is determined by the magnitude of the product of the resistor RY2 and the capacitor CY 2; in embodiment 2 of the delay detection circuit in fig. 8, T3 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 11, 2 positive pulses in the edge detection signal Y31 correspond to a negative pulse due to a rising edge of Y11 in the signal YP1 and a negative pulse due to a falling edge of Y11 in the signal YP2, respectively. When Y11 in the trigger gate control value in fig. 11 changes in rising edge, Y12 in the trigger gate control value changes in falling edge, and the corresponding edge detection signal Y32 generates a positive pulse correspondingly; when Y11 is changed by a falling edge, Y12 in the trigger gate control value is changed by a rising edge at the same time, and a positive pulse is correspondingly generated in the corresponding edge detection signal Y32; during this period, the comparison output value signals including the trigger strobe control value signals other than Y11 and Y12 are unchanged, and the corresponding edge detection signals are all at low level, which is not shown in fig. 11. According to the logical or function of the non-trigger area control signal generation module, the width of the single pulse output by the non-trigger area control signal generation module is the same as the widest pulse width of the input pulses in the input edge detection signals, and the width difference is caused by the difference between the resistance and capacitance values of T2 and T3 determined in the different delay detection circuits. In fig. 11, the 1 st positive pulse in Y31 is wider than the 1 st positive pulse in Y32, the 2 nd positive pulse in Y31 is narrower than the 2 nd positive pulse in Y32, the 1 st negative pulse width in the no-trigger-region control signal P4 coincides with the 1 st positive pulse width in the edge detection signal Y31, and the 2 nd negative pulse width in the no-trigger-region control signal P4 coincides with the 2 nd positive pulse width in the edge detection signal Y32.

In the embodiment 1 of the delay detection circuit of the delay protection unit in fig. 7, the delay time for the trigger gating control value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY1 and FY4 and FY10 in fig. 10, or the sum of the delay times of the gates FY3 and FY4 and FY10 in fig. 10; the selection range of the signal delay time T1 of the trigger gate control value determined by the product of the resistor RY0 and the capacitor CY0 is ms order of magnitude, obviously, is greater than the delay time of the trigger gate control value changing to the leading edge of the corresponding single pulse of the no-trigger area control signal, that is, the time of the delay change of the trigger gate control value signal is later than the leading edge time of the single pulse output after the trigger gate control value changes. Strictly speaking, T1 actually includes the sum of the delay time caused by resistor RY0 and capacitor CY0, and the delay time of gate FY 0. In embodiment 1 of fig. 7, when selecting parameters, the value of T2 and the value of T3 are both greater than the value of T1, so that the time of delayed change of the trigger gate control value signal meets the requirement of earlier time of the trailing edge of a single pulse of the control signal of the non-trigger area output after the change of the trigger gate control value.

In the embodiment 2 of the delay detection circuit in the delay protection unit in fig. 8, the delay time for the trigger gate control value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY7 and FY9 and FY10 in fig. 10, or the sum of the delay times of the gates FY8 and FY9 and FY10 in fig. 10; t1 is a value of ms magnitude, and it is obvious that the signal delay time T1 of the trigger gate control value determined by the product of the resistor RY3 and the capacitor CY3 is longer than the delay time of the trigger gate control value changing to the leading edge of the corresponding single pulse of the non-trigger area control signal, i.e. the time of the trigger gate control value signal delay changing is later than the leading edge of the single pulse output after the trigger gate control value changing. In the embodiment 2 of the delay detection circuit in fig. 8, both the time when the trigger gate control value signal changes in delay and the time when the trailing edge of the output single pulse after the trigger gate control value changes are affected by the change of the signal YP 0; the time when the delay of the trigger gating control value signal changes is the delay of the gate circuit FY6 after the signal YP0 changes; the trailing edge time of the single pulse output after the trigger gating control value is the sum of the delay time of the gate circuits FY7 and FY9 after the signal YP0 is changed and FY10 in the graph 10, or the sum of the delay time of the gate circuits FY8 and FY9 after the signal YP0 is changed and FY10 in the graph 10; obviously, the time of the delayed change of the trigger gating control value signal is less than the time of the back edge of the output single pulse after the change of the trigger gating control value by 2 gate circuits, and the requirement that the time of the delayed change of the trigger gating control value signal is earlier than the time of the back edge of the output single pulse after the change of the trigger gating control value is met.

Fig. 12 is a trigger circuit embodiment for triggering the self-coupling compensation type main circuit embodiment 1 in fig. 2 or triggering the triac SR1 in the self-coupling compensation type main circuit embodiment 2 in fig. 3, and the trigger circuit embodiment is composed of an ac trigger optocoupler UG1, a resistor RG1, and a resistor RG2, and the trigger control signal P51 is active at a low level. The alternating current trigger optocoupler UG1 can be selected from phase-shifting bidirectional thyristor output optocouplers such as MOC3022, MOC3023, MOC3052 and MOC 3053. Power supply + VCCK is the controlled power supply controlled by the protected drive unit. The circuit structure of the trigger circuit for triggering the bidirectional thyristors SR2-SR6 in the embodiment 1 of the self-coupling compensation type main circuit in FIG. 2 or the bidirectional thyristors SR2-SR8 in the embodiment 2 of the self-coupling compensation type main circuit in FIG. 3 is the same as that of the trigger bidirectional thyristor SR 1. The trigger pulses output by the alternating current trigger optocoupler UG1 in fig. 12 from G11 and G12 and the trigger pulses output by other alternating current trigger optocouplers in the trigger unit jointly form a trigger signal P6.

Fig. 13 is embodiment 1 of a trigger strobe configuration unit, which is used to implement a trigger strobe configuration when the trigger strobe control value is active high and M is equal to 7, i.e. M does not exceed 7, the trigger control signal is active low and N is equal to 6. In fig. 13, 42 diodes D11-D76, 42 configuration switches K11-K76, 7 trigger control row lines Y21-Y27, and 6 trigger drive column lines VK1-VK6 form a diode trigger configuration matrix, resistors RS1-RS6 and triodes VS1-VS6 form a drive circuit of trigger control signals P51-P56, and at most, P51-P56 form a trigger control signal P5 to control 6 thyristors. At the crossing positions of 7 trigger control row lines Y21-Y27 and 6 trigger drive column lines VK1-VK6, configuration branches composed of diodes and configuration switches in series are arranged, the anode sides of the diodes of the configuration branches are connected to the trigger control row lines, and the cathode sides of the diodes of the configuration branches are connected to the trigger drive column lines.

Using the trigger gating configuration unit embodiment 1 of fig. 13 for compensation control with respect to the self-coupled compensated main circuit embodiment 1 of fig. 2; setting the fluctuation range of the alternating current power supply voltage as 220V +/-10%, and requiring the alternating current power supply voltage to be stabilized within the range of 220V +/-2% for output; at this time, the trigger strobe control value is Y21-Y27 of 7 bits, and all of the 7 trigger control row lines Y21-Y27 in FIG. 13 are selected as trigger strobe control row lines. Table 1 is a trigger strobe configuration table of the trigger strobe configuration unit at this time, and lists the configuration states of the configuration switches in the diode trigger configuration matrix when the corresponding active trigger control signals are configured when the trigger strobe control values Y21-Y27 for 7 bits are respectively active. The trigger gating control values Y21-Y27 effectively correspond to the voltage class intervals 1-7, respectively, and the trigger gating configuration unit controls the on-off state of the bidirectional thyristor in the embodiment 1 of the self-coupling compensation type main circuit to perform corresponding voltage compensation according to the trigger gating control values through the trigger control signals.

In table 1, the listed configuration switches need to be configured in the on state, and the unlisted configuration switches need to be configured in the off state; a total of 14 configuration switches in table 1 need to be configured in the on state. When a certain trigger gating control row line is effective, the configuration switch between the trigger driving row lines of the bidirectional thyristor which needs to be conducted in the corresponding on-off combination state when the certain trigger gating control row line is effective is configured to be in a conducting state, and the configuration switch is connected through the diode, so that the trigger driving row line of the bidirectional thyristor which needs to be conducted is effective. For example, when the input voltage is at the lowest voltage level 1, that is, Y21 is at a high level, K11 and K16 in the diode trigger configuration matrix are turned on to turn on diodes D11 and D16, trigger drive row lines VK1 and VK6 are at a high level to control the triodes VS1 and VS6 to be turned on respectively to effectively turn on the triacs SR1 and SR6 from P51 and P56, and the other diodes in the diode trigger configuration matrix are turned off to control the other triacs to be turned off, and output voltage U12+ U23 is used as the excitation coil voltage of TB1 to perform forward compensation; when the input voltage is in a voltage class 2, namely Y22 is effectively in a high level, K23 and K26 in the diode trigger configuration matrix are conducted to enable diodes D23 and D26 to be conducted, triodes VS3 and VS6 are respectively controlled to be conducted to enable P53 and P56 to effectively turn on bidirectional thyristors SR3 and SR6 when trigger drive row lines VK3 and VK6 are in a high level, other diodes in the diode trigger configuration matrix are cut off to control the other bidirectional thyristors to be turned off, and only output voltage U23 is used for forward compensation of excitation coil voltage of TB 1; when the input voltage is at a voltage level of 4, namely Y24 is effectively at a high level, K45 and K46 in the diode trigger configuration matrix are conducted to enable diodes D45 and D46 to be conducted, triodes VS5 and VS6 are respectively controlled to be conducted to enable P55 and P56 to effectively turn on bidirectional thyristors SR5 and SR6 when trigger drive row lines VK5 and VK6 are at a high level, and other diodes in the diode trigger configuration matrix are turned off to control other bidirectional thyristors to be turned off, so that 0-voltage compensation is realized, namely the voltage of an excitation coil of TB1 is 0; when the input voltage is at voltage level 5, namely Y25 is effectively at a high level, K52 and K53 in the diode trigger configuration matrix are conducted to enable diodes D52 and D53 to be conducted, triodes VS2 and VS3 are respectively controlled to be conducted to enable P52 and P53 to effectively turn on bidirectional thyristors SR2 and SR3 when trigger drive row lines VK2 and VK3 are at a high level, other diodes in the diode trigger configuration matrix are cut off to control the other bidirectional thyristors to be turned off, and the reverse output voltage U12 is only adopted to carry out reverse compensation on the excitation coil voltage of TB 1; and so on.

TABLE 1

The trigger gating configuration unit embodiment 1 of fig. 13 is used for compensation control aiming at the self-coupling compensation type main circuit embodiment 1 of fig. 2, the fluctuation range of the alternating current power supply voltage is 220V +/-10%, and the alternating current power supply voltage is required to be stabilized within the range of 220V +/-4% for output; at this time, the trigger strobe control value is Y21-Y23 with 3 bits, and 3 trigger control row lines Y21-Y23 in FIG. 13 are selected as the trigger strobe control row lines. Table 2 is a trigger strobe configuration table of the trigger strobe configuration unit at this time, and lists the configuration states of the configuration switches in the diode trigger configuration matrix when the corresponding active trigger control signals are configured when the trigger strobe control values Y21-Y23 for 3 bits are respectively active. The trigger strobe control values Y21-Y23 effectively correspond to voltage level intervals 1-3, respectively.

In table 2, the listed configuration switches need to be configured in the on state, and the unlisted configuration switches need to be configured in the off state; in table 2, a total of 6 configuration switches need to be configured in the on state. When the input voltage is in a voltage level 1, namely Y21 is effectively in a high level, K13 and K16 in the diode trigger configuration matrix are conducted to enable diodes D13 and D16 to be conducted, triodes VS3 and VS6 are respectively controlled to be conducted to enable P53 and P56 to effectively turn on bidirectional thyristors SR3 and SR6 when trigger drive row lines VK3 and VK6 are in a high level, other diodes in the diode trigger configuration matrix are cut off to control the other bidirectional thyristors to be turned off, and only output voltage U23 is used for forward compensation of excitation coil voltage of TB 1; when the input voltage is in a voltage class 2, namely Y22 is effectively in a high level, K25 and K26 in the diode trigger configuration matrix are conducted to enable diodes D25 and D26 to be conducted, the trigger drive row lines VK5 and VK6 are in a high level and respectively control triodes VS5 and VS6 to be conducted to enable P55 and P56 to effectively turn on bidirectional thyristors SR5 and SR6, and other diodes in the diode trigger configuration matrix are turned off to control other bidirectional thyristors to be turned off, so that 0-voltage compensation is realized; when the input voltage is in a voltage class 3, namely Y23 is effectively in a high level, K34 and K35 in the diode trigger configuration matrix are conducted to enable diodes D34 and D35 to be conducted, triodes VS4 and VS5 are controlled to be conducted to enable P54 and P55 to effectively turn on bidirectional thyristors SR4 and SR5 respectively when trigger drive row lines VK4 and VK5 are in a high level, other diodes in the diode trigger configuration matrix are turned off to control the other bidirectional thyristors to be turned off, and the excitation coil voltage of TB1 is reversely compensated by only adopting a reverse output voltage U23.

TABLE 2

Fig. 14 is an embodiment 2 of the trigger strobe configuration unit, which is used to implement the trigger strobe configuration when the trigger strobe control value is active low and M is equal to 10, i.e. M does not exceed 10, and the trigger control signal is active low and 8, i.e. N is equal to 8. In fig. 14, 80 diodes D01-D98, 80 configuration switches K01-K98, 10 trigger control row lines Y21-Y210, and 8 trigger driving column lines VK1-VK8 form a diode trigger configuration matrix, and 8 trigger driving column lines VK1-VK8 in the diode trigger configuration matrix directly output low-level active trigger control signals P51-P58. At the crossing positions of 10 trigger control row lines Y21-Y210 and 8 trigger driving column lines VK1-VK8, configuration branches composed of diodes and configuration switches connected in series are arranged, the cathode sides of the diodes of the configuration branches are connected to the trigger control row lines, and the anode sides of the diodes of the configuration branches are connected to the trigger driving column lines. The main difference between the embodiment 2 of the trigger gating configuration unit in fig. 14 and the embodiment 1 of the trigger gating configuration unit in fig. 13 is that the trigger gating control value is active at low level, and the diodes which are conducted by the active low level of the trigger gating control value are directly used as the driving source of the light emitting diodes at the input ends of the multiple ac trigger optocouplers without a trigger control signal driving circuit.

Using the trigger strobe configuration unit embodiment 2 of fig. 14 for compensation control for the self-coupled compensated main circuit embodiment 2 of fig. 3; setting the fluctuation range of the alternating current power supply voltage to be 220V + 10% to 220V-20%, and requiring the alternating current power supply voltage to be stabilized within the range of 220V +/-2% for output; at this time, the trigger strobe control value is Y21-Y210 with 10 bits, and all of the 10 trigger control row lines Y21-Y210 in FIG. 14 are selected as trigger strobe control row lines. Table 3 is a trigger strobe configuration table of the trigger strobe configuration unit at this time, which lists the configuration states of the configuration switches in the diode trigger configuration matrix when the corresponding active trigger control signals are configured when the trigger strobe control values Y21-Y210 for 10 bits are respectively active. The trigger gating control values Y21-Y210 effectively correspond to the voltage class intervals 1-10, respectively, and the trigger gating configuration unit controls the on-off state of the triac in the embodiment 2 of the self-coupling compensation type main circuit to perform corresponding voltage compensation according to the trigger gating control values through the trigger control signals.

In table 3, the listed configuration switches need to be configured in the on state, and the unlisted configuration switches need to be configured in the off state; a total of 20 configuration switches in table 3 need to be configured in the on state. When a certain trigger gating control row line is effective, the configuration switch between the trigger driving row lines of the bidirectional thyristor which needs to be conducted in the corresponding on-off combination state when the certain trigger gating control row line is effective is configured to be in a conducting state, and the configuration switch is connected through the diode, so that the trigger driving row line of the bidirectional thyristor which needs to be conducted is effective. For example, when the input voltage is at voltage level 7, that is, Y27 is active low, K77 and K78 in the diode trigger configuration matrix are turned on to turn on diodes D77 and D78, trigger to drive row lines VK7 and VK8 to be low to turn on triacs SR7 and SR8, and other diodes in the diode trigger configuration matrix are turned off to turn off other triacs, thereby implementing 0 voltage compensation, that is, the voltage of the excitation coil of TB1 is 0; when the input voltage is at a voltage level of 8, namely Y28 is at a low level, K82 and K83 in the diode trigger configuration matrix are conducted to enable diodes D82 and D83 to be conducted, trigger driving row lines VK2 and VK3 to be at a low level to turn on bidirectional thyristors SR2 and SR3, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and reverse output voltage U12 is only adopted to carry out reverse compensation on excitation coil voltage of TB 1; when the input voltage is in a voltage class 9, namely Y29 is in a low level effectively, K96 and K97 in the diode trigger configuration matrix are conducted, diodes D96 and D97 are conducted, trigger driving row lines VK6 and VK7 to be in a low level to turn on bidirectional thyristors SR6 and SR7, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and reverse output voltage U34 is only adopted to carry out reverse compensation on excitation coil voltage of TB 1; when the input voltage is in a voltage class of 10, namely Y210 is effectively in a low level, K04 and K05 in the diode trigger configuration matrix are conducted, diodes D04 and D05 are conducted, row lines VK4 and VK5 are triggered and driven to be in a low level to turn on bidirectional thyristors SR4 and SR5, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and reverse output voltage U23 is only adopted to be used as excitation coil voltage of TB1 for reverse compensation; when the input voltage is at voltage level 6, namely Y26 is at low level effectively, K61 and K64 in the diode trigger configuration matrix are conducted, diodes D61 and D64 are conducted, row lines VK1 and VK4 are triggered and driven to be at low level to turn on bidirectional thyristors SR1 and SR4, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and only the output voltage U12 is used as the excitation coil voltage of TB1 to perform forward compensation; when the input voltage is in a voltage class of 4, namely Y24 is effectively in a low level, K43 and K46 in the diode trigger configuration matrix are conducted, diodes D43 and D46 are conducted, trigger driving row lines VK3 and VK6 to be in a low level to turn on bidirectional thyristors SR3 and SR6, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and forward compensation is carried out by only adopting an output voltage U23 as the excitation coil voltage of TB 1; when the input voltage is in a voltage class 3, namely Y23 is effectively in a low level, K31 and K36 in the diode trigger configuration matrix are conducted, so that diodes D31 and D36 are conducted, row lines VK1 and VK6 are triggered and driven to be in a low level to turn on bidirectional thyristors SR1 and SR6, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and the output voltage U12+ U23 is used as the excitation coil voltage of TB1 for forward compensation; when the input voltage is in a voltage class 1, namely Y21 is effectively in a low level, K11 and K18 in the diode trigger configuration matrix are conducted, diodes D11 and D18 are conducted, row lines VK1 and VK8 are triggered and driven to be in a low level to turn on bidirectional thyristors SR1 and R8, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and output voltage U12+ U23+ U34 is adopted to serve as excitation coil voltage of TB1 for forward compensation; and so on.

TABLE 3

Using the trigger strobe configuration unit embodiment 2 of fig. 14 for compensation control for the self-coupled compensated main circuit embodiment 2 of fig. 3; setting the fluctuation range of the alternating current power supply voltage as 220V +/-15%, and requiring the alternating current power supply voltage to be stabilized within the range of 220V +/-3.5% for output; at this time, the trigger strobe control value is Y21-Y25 with 5 bits, and 5 trigger control row lines Y21-Y25 in FIG. 14 are selected as the trigger strobe control row lines. Table 4 is a table of trigger strobe configurations of the trigger strobe configuration unit, which lists the configuration states of the configuration switches in the diode trigger configuration matrix when the corresponding active trigger control signals are configured when the trigger strobe control values Y21-Y25 for 5 bits are respectively active. The trigger gating control values Y21-Y25 are respectively and effectively corresponding to the voltage level intervals 1-5, and the trigger gating configuration unit controls the on-off state of the bidirectional thyristor in the embodiment 2 of the self-coupling compensation type main circuit to perform corresponding voltage compensation according to the trigger gating control values through the trigger control signals.

In table 4, the listed configuration switches need to be configured in the on state, and the unlisted configuration switches need to be configured in the off state; a total of 10 configuration switches in table 4 need to be configured in the on state. For example, when the input voltage is at voltage level 3, that is, Y23 is at a low level, K37 and K38 in the diode trigger configuration matrix are turned on to turn on diodes D37 and D38, trigger and drive row lines VK7 and VK8 to be at a low level to turn on triacs SR7 and SR8, and other diodes in the diode trigger configuration matrix are turned off to turn off other triacs, thereby implementing 0 voltage compensation; when the input voltage is in a voltage class 1, namely Y21 is effectively in a low level, K11 and K16 in the diode trigger configuration matrix are conducted, diodes D11 and D16 are conducted, the row lines VK1 and VK6 are triggered and driven to be in a low level to turn on bidirectional thyristors SR1 and SR6, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and the output voltage U12+ U23 is used as the excitation coil voltage of TB1 for forward compensation; when the input voltage is in a voltage class of 4, namely Y24 is effectively in a low level, K46 and K47 in the diode trigger configuration matrix are conducted, so that diodes D46 and D47 are conducted, row lines VK6 and VK7 are triggered and driven to be in a low level to turn on bidirectional thyristors SR6 and SR7, other diodes in the diode trigger configuration matrix are cut off, other bidirectional thyristors are turned off, and the reverse output voltage U34 is only used as the excitation coil voltage of TB1 for reverse compensation; and so on.

TABLE 4

When the embodiment 2 of the trigger gating configuration unit in fig. 14 is used for performing compensation control on the embodiment 2 of the self-coupling compensation type main circuit in fig. 3, a low level in a trigger gating control value needs to directly drive the input end light emitting diodes of 2 ac trigger optocouplers to emit light; when the alternating current trigger optocoupler selects MOC3022, MOC3052 and the like, a driving current of 20mA is needed; when the alternating current trigger optocoupler selects MOC3023, MOC3053 and the like, 10mA of driving current is needed. The embodiment 2 of the trigger gating configuration unit in fig. 14 may also be used to perform compensation control on the embodiment 1 of the self-coupling compensation type main circuit in fig. 2, and at this time, the low level in the trigger gating control value also needs to directly drive the input end light emitting diode of the 2 ac trigger optocouplers to emit light.

Embodiment 1 of the trigger strobe configuration unit of fig. 13 can also be used to perform compensation control for embodiment 2 of the self-coupled compensated main circuit of fig. 3, where the number of trigger control row lines and the number of trigger driving column lines need to be increased. When fig. 13 and fig. 14 are expanded, the diode triggering configuration matrix needs to be provided with configuration branches formed by connecting diodes and configuration switches in series at all intersections of triggering control row lines and triggering driving column lines.

The function of the error detection judging unit is to enable the output trigger gating control value judging signal P7 to be effective when judging that only one of M bits of the trigger gating control value is effective, or to enable the output trigger gating control value judging signal P7 to be ineffective; that is, when not only one of the M bits of the trigger strobe control value is valid, or when no one of the M bits of the trigger strobe control value is valid, the output trigger strobe control value determination signal P7 is invalidated.

FIG. 15 shows an error detection and determination unit in embodiment 1, with inputs Y21-Y27, which determines the trigger strobe control value P3 with high level, m being 7, i.e. at most 7 bits; the output trigger gating control value judges whether the signal P7 is effective at high level or ineffective at low level; that is, the output P7 is 1, indicating that the trigger strobe control value is valid; the output P7 is 0 indicating that the trigger strobe control value is invalid. In fig. 15, FD3 is a ROM memory having a 10-bit address input and a 1-bit data output, 7-bit trigger strobe control values Y21-Y27 are connected to 7-bit address inputs a0-a6 via strobe switches k1-k7, respectively, and a trigger strobe control value decision signal P7 is output from a data output terminal D0; pull-down resistors RX1-RX7 are used to pull down the corresponding ROM memory input signal to a low level when the gate switches are open. Table 5 is a logical truth table of the error detection and determination unit in embodiment 1, and is also a table of contents of the ROM memory in fig. 15.

The contents of the ROM memory storage unit in fig. 15 are written in accordance with the data of table 5. If the input trigger strobe control value P3 is 7 bits, i.e., M equals 7, then the strobe switches k1-k7 in FIG. 15 are all closed and the 7-bit trigger strobe control values Y21-Y27 are all actually input to the 7-bit address inputs A0-A6 of the ROM memory. In table 5, only one of the 7 bits Y21-Y27 of the trigger strobe control value is valid 1, the output trigger strobe control value decision signal P7 is made to be valid 1, otherwise the output trigger strobe control value decision signal P7 is made to be invalid 0, so as to satisfy the functional requirements of the error detection decision unit.

TABLE 5

In FIG. 15, if the input trigger gate control value P3 is 3 bits, i.e. M equals to 3, then the gate switches k1-k3 in FIG. 15 are closed and k4-k7 are opened; the 3-bit trigger strobe control value Y21-Y23 is actually input to the 3-bit address input A0-A2 of the ROM memory, and the other 4-bit address input A3-A6 of the ROM memory is pulled down to 0 by a pull-down resistor; at this time, the input conditions of the rows 4 to 7 in table 5 cannot be generated, and only one of the 3 bits Y21 to Y23 of the trigger strobe control value is valid 1, the output trigger strobe control value determination signal P7 is made to be valid 1, otherwise the output trigger strobe control value determination signal P7 is made to be invalid 0, so as to satisfy the functional requirements of the error detection determination unit.

In fig. 15, if the trigger strobe control value determination signal P7 to be output is active at low and inactive at high, all the contents of the last 1 column data in table 5 need to be changed from 0 to 1 and from 1 to 0.

FIG. 16 shows an error detection and determination unit of embodiment 2, with inputs Y21-Y210, which determines the trigger strobe control value P3 with low level, effective, m being 10, i.e. at most 10 bits; the output trigger gating control value judges whether the signal P7 is effective at high level or ineffective at low level; that is, the output P7 is 1, indicating that the trigger strobe control value is valid; the output P7 is 0 indicating that the trigger strobe control value is invalid. In fig. 16, FD4 is a ROM memory having a 10-bit address input and a 1-bit data output, 10-bit trigger strobe control values Y21-Y210 are connected to the 10-bit address input a0-a9 via strobe switches j1-j10, respectively, and a trigger strobe control value decision signal P7 is output from a data output terminal D0; pull-up resistors RJ1-RJ10 are used to pull up the corresponding ROM memory input signal to a high level when the gating switches are open. Table 6 is a logical truth table of the error detection and determination unit in embodiment 2, and is also a table of contents of the ROM memory in fig. 16.

The contents of the ROM memory storage unit in fig. 16 are written in accordance with the data of table 6. If the input trigger strobe control value P3 is 10 bits, i.e., M equals 10, then the strobe switches j1-j10 in FIG. 16 are all closed and the 10-bit trigger strobe control values Y21-Y210 are all actually input to the 10-bit address inputs A0-A9 of the ROM memory. In table 6, only one of the 10 bits Y21-Y210 of the trigger strobe control value is a valid 1, the output trigger strobe control value determination signal P7 is a valid 1, otherwise, the output trigger strobe control value determination signal P7 is an invalid 0, so as to satisfy the functional requirements of the error detection determination unit.

In FIG. 16, if the input trigger gate control value P3 is 9 bits, i.e., M equals 9, then the gate switches k1-k9 in FIG. 16 are closed and k10 is opened; the 9-bit trigger strobe control value Y21-Y29 is actually input to 9-bit address inputs A0-A8 of the ROM memory, and the other 1-bit address input A9 of the ROM memory is pulled up to 1 by a pull-up resistor; at this time, the input condition of the 10 th row in table 6 cannot be generated, and only one valid 0 out of the 9 bits Y21-Y29 of the trigger strobe control value makes the output trigger strobe control value decision signal P7 be a valid 1, otherwise makes the output trigger strobe control value decision signal P7 be a invalid 0, so as to satisfy the functional requirements of the error detection decision unit.

TABLE 6

In FIG. 16, if the input trigger strobe control value P3 is 7 bits, i.e., M equals 7, then the strobe switches j1-j7 in FIG. 15 are closed and j8-j10 are opened; the 7-bit trigger strobe control value Y21-Y27 is actually input to the 7-bit address input A0-A6 of the ROM memory, and the other 3-bit address input A7-A9 of the ROM memory is pulled up to 0 by a pull-up resistor; at this time, the input conditions of the 8 th to 10 th rows in table 6 cannot be generated, and only one valid 0 out of the 7 bits Y21 to Y27 of the trigger strobe control value makes the output trigger strobe control value decision signal P7 be a valid 1, otherwise makes the output trigger strobe control value decision signal P7 be a invalid 0, so as to satisfy the functional requirements of the error detection decision unit.

In fig. 16, if the trigger strobe control value determination signal P7 to be output is active at a low level and inactive at a high level, all the contents of the data in the last 1 column in table 6 need to be changed from 0 to 1, and from 1 to 0.

In

embodiments

1 and 2 of the sampling comparison unit, when M is smaller than M, except for the M-bit trigger gating control value, the state of other comparison output values of M-M bits and the state after delay of the signals sent to the delay protection unit by the sampling comparison unit are the same as the state of an invalid bit in the M-bit trigger gating control value, and the judgment on whether the M-bit trigger gating control value is valid or not is not influenced; thus, at this time, the gate switches k1-k7 and the pull-down resistors RX1-RX7 in FIG. 15 may be eliminated, and the 7-bit comparison output values Y21-Y27 are directly connected to the 7-bit address inputs A0-A6 of the ROM memory; the gating switches j1-j10 and pull-up resistors RJ1-RJ10 in FIG. 16 may be eliminated, and the 10-bit comparison output values Y21-Y210 may be directly connected to the 10-bit address inputs A0-A9 of the ROM memory.

The logic function of the error detection decision unit can also be implemented in other ways, for example, tables 5 and 6 are logic truth tables, and the function can be implemented by combining with or not logic gate. The ROM memory in the error detection judging unit or the logic gate is used for realizing the function, and the single power supply + VCC1 is used for supplying power.

FIG. 17 shows an embodiment of the protection driving unit, wherein the high level of the input trigger gate control value determining signal P7 is asserted, i.e. P7 is 1 to indicate that the trigger gate control value is asserted; the P7 is inactive low, i.e., P7 is 0, indicating that the trigger strobe control value is inactive. The low level of an input control signal P4 of the non-trigger area is effective, namely when P4 is equal to 0, the control value of the trigger gating is changed due to the fact that the alternating current power supply voltage fluctuates, switching of the on-off state of a bidirectional thyristor in a thyristor switch group is needed, and a compensation mode is changed; in the switching process, in order to avoid that 2 or more than 2 thyristors are simultaneously conducted in the thyristors at the same side due to the delayed turn-off factor of the bidirectional thyristors, so as to cause a power supply short circuit, all the bidirectional thyristors in the thyristor switch group are turned off in the effective period of the control signal of the non-trigger area, namely when the P4 of the embodiment is equal to 0.

In fig. 17, a transistor VT, a relay coil KA, a freewheeling diode VD, and a resistor RK1 form a protection control circuit, a transistor VK1, a transistor VK2, a resistor RK2, a resistor RK3, and an and gate FY21 form a trigger unit controlled power control circuit, and the and gate FY21 is powered by a single power supply + VCC 1. The + VCC2 is the power supply for the relay coil and the source supply for the controlled power supply + VCCK in the trigger unit. When the input trigger gating control value judging signal P7 is at a low level, namely the trigger gating control value is invalid, the AND gate FY21 outputs a low level, the triodes VK1 and VK2 are cut off, the controlled power supply + VCCK loses power, the trigger unit does not have a power supply and does not work, namely, the trigger unit does not send out trigger pulses for triggering the bidirectional thyristor; p7 is low level and controls the transistor VT to stop, the relay coil KA loses power, so that the self-coupling compensation type main circuit embodiment 1 in fig. 2 or the relay normally open switch KA-1 in the self-coupling compensation type main circuit embodiment 2 in fig. 3 is turned off, that is, the input side power supply voltage of the autotransformer is controlled to be turned off, the voltage between all taps of the autotransformer is 0, and the protection of the thyristor switch group is realized; the normally closed relay switch KA-2 is closed, and the voltage applied to the excitation coil of TB1 is set to 0. When the sampling comparison unit fails to work to cause the trigger gating control value to be invalid, or the input alternating current power supply voltage is lower than the range of the minimum voltage level interval to cause the output trigger gating control value to be invalid, the protection driving unit cuts off the power supply of the trigger unit no matter whether the input non-trigger area control signal P4 is valid or not, stops sending out trigger pulses of all the bidirectional thyristors, and controls to cut off the input side power supply voltage of the autotransformer to realize the protection of the thyristor switch group. When the input trigger gating control value judging signal P7 is at a high level, that is, the trigger gating control value is valid, the control transistor VT is turned on, and the relay coil KA is powered on, so that the normally open relay switch KA-1 in the self-coupling compensation type main circuit embodiment 1 in fig. 2 or the normally open relay switch KA-1 in the self-coupling compensation type main circuit embodiment 2 in fig. 3 is turned on, the normally closed relay switch KA-2 is turned off, and the circuit is in a compensation working state. When the trigger gating control value is valid, namely P7 is 1, and the control signal of the non-trigger area is valid, namely P4 is equal to 0, the AND gate FY21 outputs low level, the triodes VK1 and VK2 are cut off, the controlled power supply + VCCK loses power, the trigger unit does not work, namely, the trigger pulse for triggering the bidirectional thyristor is not sent out, all the bidirectional thyristors in the thyristor switch group are cut off, the alternating-current power supply voltage at the moment is fluctuated, the trigger gating control value is changed, the electronic switch needs to be switched, and the compensation mode is changed. When the trigger gating control value is valid, namely P7 is 1, and the control signal of the non-trigger area is invalid, namely P4 is equal to 1, the AND gate FY21 outputs high level, the triodes VK1 and VK2 are both conducted, the controlled power supply + VCCK is electrified, the trigger unit works normally, the trigger gating configuration unit selects the corresponding trigger control signal to be valid according to the valid trigger gating control value corresponding to a certain voltage grade interval, the trigger unit sends out trigger pulse to control the on-off state of the bidirectional thyristors in the thyristor switch group, and the main circuit is in a compensation working state corresponding to the voltage grade interval.

When the error detection judging unit judges that the input trigger gating control value is invalid, the protection driving unit sends a protection control signal to the main circuit, so that the thyristor switch group is in a protection state, the alternating current voltage stabilizer does not compensate the input voltage, and the voltage output by the voltage stabilizer is the input alternating current power supply voltage. When the thyristor switch group is in the protection state, if the error detection judging unit judges that the input trigger gating control value is recovered to be an effective signal, the protection driving unit automatically stops the protection state of the thyristor switch group, and the thyristor switch group is in the compensation working state again.

As can be known from the above embodiments and the working process thereof, when the input is the effective trigger gating control value, the trigger gating configuration unit ensures that the thyristors at the same side in the self-coupling compensation type main circuit thyristor switch group are not conducted at the same time, thereby realizing the interlocking control of the thyristors; when the trigger gating control value is invalid, the protection driving unit simultaneously cuts off the power supply of the autotransformer on the basis of rapidly cutting off the power supply of the trigger unit and avoiding short circuit caused by error conduction of the bidirectional thyristor, so that the thyristor switch group is in a protection state. When the thyristor switch group is in the protection state, if the error detection judging unit judges that the alternating current voltage stabilizer enters the normal logic control state again, namely the error detection judging unit judges that the input trigger gating control value is recovered to be an effective signal, the protection driving unit can automatically stop the protection state of the thyristor switch group and enable the thyristor switch group to be in the compensation working state again. The function effectively strengthens the protection force of the alternating current voltage stabilizer against the abnormity of the working process, so that the working process of the partition self-coupling compensation type alternating current voltage stabilization control method is more reliable.

Besides the technical features described in the specification, other techniques of the partitioned self-coupled compensation type ac voltage stabilizing control method are conventional techniques known to those skilled in the art.

Claims

1. A partition self-coupling compensation type alternating current voltage stabilization control method is characterized by comprising the following steps: adjusting the voltage in the alternating current power supply voltage fluctuation interval range into M voltage grade intervals; identifying the voltage grade interval to obtain a trigger gating control value; configuring a configuration switch in a diode trigger configuration matrix, selecting and enabling a corresponding trigger control signal to be effective according to a trigger gating control value of the diode trigger configuration matrix, and controlling the on-off combination state of a thyristor in a thyristor switch group; the on-off combined state of the thyristors in the thyristor switch group controls and selects 0 of a plurality of output voltages of the autotransformer, or more than 0 of output voltages are superposed to be used as the excitation coil voltage of the compensation transformer, so that the voltage compensation state corresponding to the voltage grade interval is realized; each voltage grade interval of the alternating current power supply voltage corresponds to a voltage compensation state; m is less than or equal to M, and M is greater than or equal to 3;

the thyristor switch group is provided with N thyristors in total; the diode trigger configuration matrix comprises m trigger control row lines and N trigger drive column lines; the N triggering driving column lines correspond to the N thyristors one by one, and the signal of one triggering driving column line effectively corresponds to the triggering control signal of one thyristor;

a configuration branch circuit formed by connecting a diode and a configuration switch in series is arranged at the crossing position of each trigger control row line and each trigger driving column line;

when the trigger control row line signal is active at a low level, the cathode side of the diode of the configuration branch is connected to the trigger control row line, and the anode side of the diode of the configuration branch is connected to the trigger driving column line; when the trigger control row line signal is high level and effective, the anode side of the diode of the configuration branch is connected to the trigger control row line, and the cathode side of the diode is connected to the trigger drive column line; the N is more than or equal to 4;

the configuration method of the configuration switch in the configuration branch circuit is that M of M trigger control row lines are selected as trigger gating control row lines; m triggering gating control row lines correspond to M bit triggering gating control values one by one, and one triggering gating control value correspondingly enables one triggering gating control row line to be effective; when each trigger gating control row line signal is effective, the on-off combination state of a thyristor in a corresponding thyristor switch group is corresponded; configuring a configuration switch in a configuration branch between each trigger gating control row line and a trigger driving row line which is in a corresponding on-off combination state and needs to control the conduction of a thyristor when a signal of the row line is effective into an on state; configuring a configuration switch in a configuration branch between each trigger gating control row line and a trigger driving row line which is in a corresponding on-off combination state and needs to control the turn-off of the thyristor when the row line signal is effective into an off state;

identifying the voltage grade interval to obtain a trigger gating control value, and realizing the trigger gating control value by a sampling comparison unit; the sampling comparison unit comprises m-1 comparators, an upper limit threshold potentiometer and a lower limit threshold potentiometer; the voltage in the alternating current power supply voltage fluctuation interval range can be adjusted into M voltage grade intervals by adjusting the upper threshold potentiometer and the lower threshold potentiometer, and M trigger gating control values are output; the M voltage class intervals correspond to the M trigger gating control values one by one.

2. The sectional self-coupling compensation type alternating current voltage stabilizing control method according to claim 1, characterized in that: and judging whether the trigger gating control value is effective or not, and controlling the thyristor switch group to be in a protection state when the trigger gating control value is ineffective.

3. The sectional self-coupling compensation type alternating current voltage stabilizing control method according to claim 2, characterized in that: the method for controlling the thyristor switch group to be in the protection state is to control and disconnect the input side power supply voltage of the autotransformer.

4. The sectional self-coupling compensation type alternating current voltage stabilizing control method according to claim 2, characterized in that: judging whether the trigger gating control value is effective or not according to the fact that the trigger gating control value is effective when one bit is effective in M-bit binary values of the trigger gating control value; otherwise, the trigger gating control value is invalid.

5. The sectional self-coupling compensation type alternating current voltage stabilizing control method according to claim 2, characterized in that: when the trigger gating control value changes and the thyristor switch group needs to be switched to be in different on-off combination states, maintaining a non-trigger area time between the 2 on-off combination states, and turning off all thyristors in the thyristor switch group.

6. The sectional self-coupling compensation type alternating current voltage stabilizing control method according to claim 5, characterized in that: the maintaining of the one non-trigger area time is realized by a non-trigger area control signal; controlling the control signal of the non-trigger area to output a single pulse after the trigger gating control value is changed; the control signal of the non-trigger area is effective in the period of outputting the single pulse and is ineffective in the period of not outputting the single pulse; and when the control signal of the non-trigger area is effective, maintaining a time of the non-trigger area.

7. The sectional self-coupling compensation type alternating current voltage stabilizing control method according to claim 6, characterized in that: the trigger control signal for controlling the thyristor switch group is generated by the delayed trigger gating control value; the delayed signal change time of the trigger gating control value is later than the leading edge time of a single pulse in the non-trigger area control signal after the trigger gating control value is changed and earlier than the trailing edge time of the single pulse in the non-trigger area control signal after the trigger gating control value is changed.