CN109358679B

CN109358679B - Thyristor triggering gating configuration method

Info

Publication number: CN109358679B
Application number: CN201811355945.XA
Authority: CN
Inventors: 凌云; 徐敬成; 侯文浩; 王兵
Original assignee: Hunan University of Technology
Current assignee: Liu Zheng
Priority date: 2018-11-15
Filing date: 2018-11-15
Publication date: 2020-11-06
Anticipated expiration: 2038-11-15
Also published as: CN109358679A

Abstract

A thyristor triggering gating configuration method is used for on-off combination control of thyristors in a thyristor bridge, and the on-off combination state of the thyristors in the thyristor bridge is controlled by selecting and enabling a corresponding triggering control signal to be effective through a diode triggering configuration matrix according to a triggering gating control value. When the thyristor triggering gating configuration method is used for the partition compensation alternating current voltage stabilizer, a sampling comparison circuit samples the voltage of an alternating current power supply and outputs a triggering gating control value; the thyristor triggering gating configuration circuit outputs a triggering control signal according to the delayed triggering gating control value, the triggering circuit controls the on-off of the thyristor in the thyristor bridge, the error detection judging circuit and the protection driving circuit start/stop the open-circuit protection of the thyristor bridge according to whether the triggering gating control value is effective or not while the interlocking control is realized, the power supply of the triggering circuit is controlled, and the protection strength for the abnormity of the working process is effectively enhanced.

Description

Thyristor triggering gating configuration method

Technical Field

The invention relates to the technical field of power supplies, in particular to a thyristor triggering gating configuration method.

Background

The existing compensation type AC voltage stabilizer has the advantages of wide voltage stabilizing range, almost no distortion of waveform, high efficiency of the whole machine and strong load adaptability. The principle is that switching of different winding coils of a primary winding on a compensation transformer is automatically controlled according to the high-low condition of input voltage, bidirectional multi-gear voltage compensation is provided by utilizing the transformation ratio relation of a primary side working winding and a secondary winding or by adjusting the voltage applied to the primary winding, and therefore the purpose of voltage regulation and stabilization is achieved.

At present, controllers such as a single chip microcomputer and a PLC are mainly adopted to judge the level of input voltage and partition a voltage interval, and a software logic mode is adopted to realize switching and interlocking of combined control of a plurality of thyristor electronic switches.

Disclosure of Invention

In order to solve the problems of the existing compensation type alternating current voltage stabilizer, the invention provides a thyristor triggering gating configuration method, which selects and enables a corresponding triggering control signal in an output triggering control signal to be effective through a diode triggering configuration matrix according to an input triggering gating control value, and controls the on-off combination state of a thyristor in a thyristor bridge, and is used for the on-off combination control of the thyristor in the thyristor bridge. Triggering a gating control value to be an M-bit binary value; the trigger gating control values of M bits are M trigger gating control values, and one trigger gating control value corresponds to the on-off combination state of a thyristor in a thyristor bridge; configuring the diode trigger configuration matrix, and changing the on-off combination of the on-off combination state of the thyristor in the thyristor bridge corresponding to each trigger gating control value; one and only one of the M binary values triggering the gating control value is valid; and M is an integer greater than or equal to 2.

The thyristor bridge is provided with N thyristors; the diode trigger configuration matrix comprises m trigger control row lines and N trigger drive column lines; the N triggering driving column lines correspond to the N thyristors one by one, and the signal of one triggering driving column line effectively corresponds to the triggering control signal of one thyristor; a configuration branch consisting of a diode and a configuration switch in series connection is arranged at the crossing position of each trigger control row line and each trigger driving column line, and the configuration switch can be connected in series with the cathode end of the diode or the anode end of the diode; when the trigger control row line signal is active at a low level, the cathode side of the diode of the configuration branch is connected to the trigger control row line, and the anode side of the diode of the configuration branch is connected to the trigger driving column line; when the trigger control row line signal is high level and effective, the anode side of the diode of the configuration branch is connected to the trigger control row line, and the cathode side of the diode is connected to the trigger drive column line; m is greater than or equal to 3, and M is less than or equal to M; and N is greater than or equal to 4.

The configuration method of the configuration switch in the configuration branch circuit is that M of M trigger control row lines are selected as trigger gating control row lines; m triggering gating control row lines correspond to M effective triggering gating control values one by one, and one effective triggering gating control value correspondingly enables a signal of one triggering gating control row line to be effective; when each trigger gating control row line signal is effective, the on-off combination state of a thyristor in a corresponding thyristor bridge is corresponded; configuring a configuration switch in a configuration branch between each trigger gating control row line and a trigger driving row line which is in a corresponding on-off combination state and needs to control the conduction of a thyristor when a signal of the row line is effective into an on state; and configuring the configuration switches in the configuration branches between the trigger driving column lines of which the thyristors are required to be controlled to be turned off in a corresponding on-off combination state when the signals of each trigger gating control row line and the row line are effective into an off state.

The method for enabling the trigger control signal of the thyristor to be effective by enabling the signal of one trigger driving column line to be effective corresponds to that is that the signal of one trigger driving column line is directly used as the trigger control signal of one thyristor, namely N trigger driving column line signals are directly used as the trigger control signals of N thyristors in a one-to-one correspondence mode. The signal of one trigger driving column line is effectively corresponding to a method for enabling the trigger control signal of one thyristor to be effective or is realized by a trigger control signal driving circuit; the input of the trigger control signal driving circuit is signals of N trigger driving column lines, and the output is trigger control signals of N thyristors corresponding to each other one by one.

The thyristor triggered gating configuration method is realized by a thyristor triggered gating configuration circuit and is used for on-off combination control of a thyristor bridge in the partitioned compensation alternating current voltage stabilizer. The partition compensation alternating current voltage stabilizer comprises a compensation type main circuit, a sampling comparison circuit, a delay protection circuit, a thyristor trigger gating configuration circuit, a trigger circuit, an error detection judgment circuit and a protection driving circuit; the compensation type main circuit comprises a compensation transformer bank, a thyristor bridge and a relay protection switch.

The sampling comparison circuit comprises an alternating current power supply voltage sampling circuit and a multi-interval voltage comparator circuit, wherein the alternating current power supply voltage sampling circuit converts an alternating current power supply voltage effective value into an alternating current power supply voltage sampling value.

The multi-interval voltage comparator circuit comprises m-1 comparators, compares input voltage with m-1 different threshold voltages and outputs m-bit comparison output values; and m-1 comparators are all powered by a positive single power supply. m-1 different threshold voltages are respectively connected to the inverting input ends of m-1 comparators, and the input voltage is simultaneously connected to the non-inverting input ends of m-1 comparators. The high level of the m-bit comparison output values output by the multi-interval voltage comparator is effective, and only one of the m-bit comparison output values is effective. In m-1 comparators, the comparator with the highest threshold voltage is directly powered by a positive single power supply, and other comparators are powered by controllable power supplies; when the comparator is powered by the controllable power supply, the controllable power supply supplies power to the positive power supply end of the comparator only when all the comparators with the threshold voltages higher than the threshold voltages output low levels, otherwise, the controllable power supply stops supplying power to the positive power supply end of the comparator. The comparator adopts a controllable power supply to supply power, and outputs low level when the controllable power supply stops supplying power to the positive power supply end. The m-bit comparison output value consists of the output values of m-1 comparators and the minimum interval judgment value; and when all the output values of the m-1 comparators are at low level, the lowest interval judgment value is at high level, otherwise, the lowest interval judgment value is at low level.

The voltage within the alternating current power supply voltage fluctuation interval range can be adjusted to M voltage grade intervals by adjusting the parameters of the sampling comparison circuit and further by adjusting the parameters of the multi-interval voltage comparator circuit. The multi-interval voltage comparator circuit also comprises a multi-threshold voltage output circuit consisting of an upper threshold potentiometer, a lower threshold potentiometer and a plurality of intermediate voltage-dividing resistors, and m-1 different threshold voltages are provided for m-1 comparators. Adjusting the parameter values of the upper threshold potentiometer and the lower threshold potentiometer, and adjusting the voltage in the alternating current power supply voltage fluctuation interval range into M voltage grade intervals, wherein the M voltage grade intervals correspond to M effective M-bit trigger gating control values output by the sampling comparison circuit one by one; the M-bit trigger gating control value consists of the lower M bits in the M-bit comparison output value, namely the M-bit trigger gating control value consists of the output of M-1 comparators with the lowest threshold voltage in the multi-interval voltage comparator circuit and the lowest interval judgment value. The M-1 lowest threshold voltages are respectively voltage sampling values of alternating current power supply voltage values separating M voltage class intervals. M is not less than 3, and M is not less than 2 and not more than M.

When the comparator is powered by a controllable power supply, the output end of the comparator is connected with a pull-down resistor, the controllable power supply supplies power to the positive power supply end of the comparator only when all the comparators with the threshold voltages higher than the threshold voltages output low levels, and otherwise, the controllable power supply stops supplying power to the positive power supply end of the comparator. The positive power supply end of the comparator is connected to the output end of the NOR gate, and the input end of the NOR gate is respectively connected to the output ends of the comparators with the threshold voltages higher than that of the NOR gate.

The comparators in the multi-interval voltage comparator circuit preferably adopt a low-power-consumption rail-to-rail operational amplifier powered by a single power supply.

The functions of delaying the trigger gating control value output by the sampling comparison unit and generating the control signal of the non-trigger area are realized by a delay protection circuit. The error detection judging circuit inputs the delayed trigger gating control value and judges whether the trigger gating control value is effective or not according to the judgment that the trigger gating control value is effective when only one bit is effective in M-bit binary values of the trigger gating control value; otherwise, the trigger gating control value is invalid. The bit in the trigger gating control value is 1 valid and 0 invalid, namely the high level in the trigger gating control value signal is valid and the low level is invalid; or, the bit in the trigger gating control value is 0 valid and 1 invalid, that is, the low level in the trigger gating control value signal is valid and the high level is invalid; a total of M trigger strobe control values are valid.

When the voltage level interval is changed due to the voltage fluctuation of the alternating-current power supply, so that the trigger gating control value is changed, and the on-off combination state of the thyristors in the thyristor bridge needs to be switched, maintaining a non-trigger area time between 2 different on-off combination states in sequence, and switching off all the thyristors in the thyristor bridge; maintaining a no-trigger zone time is accomplished by a no-trigger zone control signal. The delay protection circuit inputs a trigger gating control value and outputs a delayed trigger gating control value and a non-trigger area control signal; the control signal of the non-trigger area outputs a single pulse after the trigger gating control value is changed; the no-trigger area control signal is active during the output of a single pulse and inactive during the non-output of a single pulse. Further, after the trigger gating control value is changed, the width time of a single pulse in the non-trigger area control signal is selected from 10ms to 30 ms. The delayed trigger gating control value signal change time is later than the leading edge time of a single pulse in the non-trigger area control signal after the trigger gating control value is changed and is earlier than the trailing edge time of the single pulse in the non-trigger area control signal after the trigger gating control value is changed.

The specific method for starting/stopping the open-circuit protection of the thyristor bridge by the protection driving circuit according to whether the trigger gating control value is effective is that when the trigger gating control value is ineffective, all upper bridge arms of the thyristor bridge are controlled to be disconnected to enable the thyristor bridge to be in an open-circuit protection state, or all lower bridge arms of the thyristor bridge are controlled to be disconnected to enable the thyristor bridge to be in the open-circuit protection state. When the thyristor bridge is in an open-circuit protection state, and the error detection judging circuit judges that the input trigger gating control value is recovered to be effective, the protection driving circuit automatically stops the open-circuit protection state of the thyristor bridge.

The protection driving circuit controls the power supply of the trigger circuit according to whether the trigger gating control value is effective or not and whether the control signal of the non-trigger area is effective or not, and the specific method is that only when the trigger gating control value is effective and the control signal of the non-trigger area is ineffective, the power supply of the trigger circuit is controlled to be switched on, the trigger circuit works normally, and a trigger pulse is sent out according to the input trigger control signal; otherwise, the power supply of the trigger circuit is cut off, and all trigger pulses are stopped to be sent out.

The thyristors in the thyristor bridge are bidirectional thyristors or thyristor alternating current switches formed by connecting 2 unidirectional thyristors in reverse parallel.

The invention has the beneficial effects that: the thyristor triggering gating configuration method adopts only one effective and different triggering gating control value, realizes gating control of different on-off combination states of thyristors in the thyristor bridge by the diode triggering configuration matrix, and ensures that upper and lower bridge arm thyristors of the same full bridge circuit of the thyristor bridge cannot be conducted simultaneously, namely, realizes interlocking control of the upper and lower bridge arm thyristors of the same full bridge circuit; the on-off combination state of a thyristor in a thyristor bridge corresponding to the trigger gating control value can be changed by configuring a diode trigger configuration matrix so as to adapt to the number of different partitions and the compensation mode formed by the voltage fluctuation range of the input alternating-current power supply by adjusting and changing the resistance values of an upper threshold potentiometer and a lower threshold potentiometer in the sampling comparison circuit; when the requirement of voltage stabilization precision is higher, more partitions can be configured to meet the precision requirement. Meanwhile, the alternating current voltage stabilizer which adopts the compensation transformer bank and the thyristor bridge to carry out the partition voltage compensation also stops sending the trigger pulse and carries out the open circuit protection of the thyristor bridge under the condition that the sampling comparison circuit outputs an invalid trigger gating control value due to the error, thereby effectively strengthening the protection strength of the alternating current voltage stabilizer against the abnormity of the working process; when the thyristor bridge is in the open-circuit protection state, if the trigger gating control value is recovered to be effective, the open-circuit protection state of the thyristor bridge can be automatically stopped and the thyristor bridge is in the compensation working state again; the on-off switching of the thyristor is controlled without adopting a program mode of a singlechip, a PLC and the like, so that the faults of the voltage stabilizer caused by the problems of program runaway, dead halt and the like are avoided.

Drawings

FIG. 1 is a block diagram of a system configuration of a zone compensated AC voltage regulator;

FIG. 2 shows an embodiment 1 of a compensated main circuit;

FIG. 3 illustrates an embodiment of a compensated main circuit 2;

FIG. 4 shows a sampling comparison circuit of embodiment 1;

FIG. 5 shows a sample comparison circuit embodiment 2;

FIG. 6 is a block diagram of an embodiment of a delay protection circuit;

FIG. 7 is a diagram of an embodiment of a delay detection circuit 1 of the delay detection module for triggering the strobe control value signal Y10;

FIG. 8 is a circuit diagram of embodiment 2 of the delay detection circuit for triggering the strobe control value signal Y10 in the delay detection module;

FIG. 9 is a block diagram of an embodiment of a delay detection circuit 3 for triggering the strobe control value signal Y10 in the delay detection module;

FIG. 10 is a block diagram of an embodiment of a no trigger area control signal generation module;

FIG. 11 is a diagram illustrating a portion of related waveforms in the delay protection circuit;

FIG. 12 is an embodiment of a trigger circuit for triggering the triac SR1 in the trigger circuit;

fig. 13 is a thyristor-triggered gating configuration circuit embodiment 1;

fig. 14 is a thyristor-triggered gating configuration circuit embodiment 2;

FIG. 15 shows an error detection circuit of embodiment 1;

FIG. 16 shows an error detection decision circuit embodiment 2;

fig. 17 shows an embodiment of a protection driving circuit.

Detailed Description

The invention is further described below with reference to the accompanying drawings by using a thyristor triggered gate configuration method and circuit for application in a partitioned compensated ac voltage regulator.

FIG. 1 is a block diagram of a system of a partitioned compensation AC voltage stabilizer, wherein a sampling comparison circuit samples the voltage of an AC power supply and outputs a trigger gating control value P2; the delay protection circuit inputs a trigger gating control value P2 and outputs a delayed trigger gating control value P3 and a non-trigger area control signal P4; the thyristor triggering gating configuration circuit inputs the delayed triggering gating control value P3 and outputs a triggering control signal P5; the trigger circuit sends a trigger signal P6 to the compensation type main circuit according to an input trigger control signal P5 to control the on-off of a bidirectional thyristor in a thyristor bridge; the error detection judging circuit inputs the delayed trigger gating control value P3 and outputs a trigger gating control value judging signal P7; the protection driving circuit inputs a non-trigger area control signal P4 and a trigger gating control value judging signal P7, starts/stops the open-circuit protection of the thyristor bridge according to whether the trigger gating control value judging signal P7 is effective, and controls the power supply of the trigger circuit according to whether the trigger gating control value judging signal P7 is effective and whether the non-trigger area control signal P4 is effective.

Fig. 2 shows a compensation type main circuit embodiment 1, in which a compensation transformer bank is composed of compensation transformers TB1 and TB2, a thyristor bridge is composed of 6 bidirectional thyristors SR1-SR6, a fuse FU1, normally open switches KA-1, KA-2 and KA-3 of a relay, and normally closed switches KA-5 and KA-6 of the relay constitute a relay protection circuit.

In fig. 2, the compensation coils of the compensation transformers TB1 and TB2 are both connected in series to the phase line, the input end of the phase line is LA1, and the output end is LA 2. The voltage on the TB1, TB2 excitation coils is controlled by a thyristor bridge. In fig. 2, one ends of excitation coils TB1 and TB2 are connected in parallel and then connected to a thyristor full-bridge circuit formed by SR1 and SR2, and the other ends of excitation coils TB1 and TB2 are respectively connected to a thyristor full-bridge circuit formed by SR3 and SR4, and SR5 and SR 6. The compensation voltage of TB2 is 2 times of the compensation voltage of TB1, and no compensation mode that the compensation voltages are mutually offset is considered, the compensation transformer bank has 6 compensation modes of forward TB1, forward TB2, forward TB1+ TB2, reverse TB1, reverse TB2 and reverse TB1+ TB2 at most, and a0 voltage compensation mode when the input voltage is within a normal range is added, so that the alternating-current power supply voltage input by a phase line input end LA1 can be divided into 7 voltage intervals at most for compensation control. In fig. 2, N is a zero line, and G11, G12 to G61, and G62 are trigger signal input ends of the triacs SR1 to SR6, respectively.

Fig. 3 shows a compensation type main circuit embodiment 2, in which a compensation transformer bank is composed of compensation transformers TB1, TB2, TB3, a thyristor bridge is composed of 8 bidirectional thyristors SR1-SR8, a fuse FU1, normally open switches KA-1, KA-2, KA-3, KA-4 of relays, and normally closed switches KA-4, KA-5, KA-6 of relays constitute a relay protection circuit.

In fig. 3, the compensation coils of the compensation transformers TB1, TB2, and TB3 are all connected in series to the phase line, where the input end of the phase line is LA1 and the output end is LA 2. The voltages of the excitation coils of TB1, TB2 and TB3 are controlled by a thyristor bridge, one ends of the excitation coils of TB1, TB2 and TB3 are connected in parallel and then connected to a thyristor full-bridge circuit consisting of SR1 and SR2, and the other ends of the excitation coils of TB1, TB2 and TB3 are respectively connected to a thyristor full-bridge circuit consisting of SR3 and SR4, SR5 and SR6, and SR7 and SR 8. Assuming that the compensation voltage of TB2 is 2 times of the compensation voltage of TB1, the compensation voltage of TB3 is 2 times of the compensation voltage of TB2, and no compensation mode for mutual cancellation of the compensation voltages is considered, the compensation transformer bank has 7 compensation modes in the forward direction, 7 compensation modes in the reverse direction and 14 compensation modes in total, and a0 voltage compensation mode when the input voltage is within a normal range is added, so that the alternating current power supply voltage input by a phase line input end LA1 can be divided into 15 voltage intervals at most for compensation control. In fig. 3, N is a zero line, and G11, G12 to G81, and G82 are trigger signal input terminals of the triacs SR1 to SR8, respectively.

Each of the triacs of fig. 2 and 3 may be replaced by 2 antiparallel triacs. In fig. 2 and 3, the relay normally open switch and the relay normally closed switch form a relay protection switch.

Adjusting the voltage in the alternating current power supply voltage fluctuation interval range into M voltage grade intervals, sampling the alternating current power supply voltage by a sampling comparison circuit to obtain an alternating current power supply voltage sampling value, comparing the alternating current power supply voltage sampling value by M or M-1 comparators, and outputting a trigger gating control value formed by M binary digits; when the alternating current power supply voltage is in one of the M voltage grade intervals, the M bits trigger the corresponding one bit in the gating control value to be valid, and the other bits are invalid. The effective bit of the M bit trigger gating control value is high level, namely binary 1; the invalid bit is low level, i.e. binary 0; or, the effective bit of the M-bit trigger gating control value is low level, namely binary 0; the invalid bit is high, i.e. binary 1.

Fig. 4 shows a sample comparison circuit embodiment 1, where m is equal to 7, and compensation control is performed for a compensation type main circuit embodiment 1. In the alternating current power supply voltage sampling circuit, alternating current power supply voltage input from a phase line LA1 and a zero line N is subjected to voltage reduction through a transformer TV, is rectified by a rectifier bridge consisting of diodes DV1-DV4, and is subjected to filtering through a capacitor CV1 and voltage division through resistors RV1 and RV2, so that an alternating current power supply voltage sampling value U1 in a positive proportional relation with an effective value of the input alternating current power supply voltage is obtained.

In the multi-section voltage comparator circuit shown in fig. 4, the upper threshold level potentiometer RPH, the lower threshold level potentiometer RPL, and the intermediate voltage dividing resistors RF2 to RF6 constitute a voltage dividing circuit, and after voltage division of the power supply + VCC1, the obtained 6 threshold voltages UF2 to UF7 are 6 intermediate division voltage values of voltage sampling values corresponding to the ac power supply voltage values divided into 7 voltage class sections. The 6 comparators FA2-FA7 realize comparison between the AC power supply voltage sampling value U1 and 6 threshold voltages UF2-UF7, the 7-bit comparison output value of the multi-interval voltage comparator circuit is composed of the output Y12-Y17 of the 6 comparators FA2-FA7 and the lowest interval judgment value Y11, and the voltage in the AC power supply voltage fluctuation interval range is divided into 7 voltage grade intervals 1-7 at most. The sampled value U1 of the AC power supply voltage is simultaneously sent to the non-inverting input end of the comparator FA2-FA 7; the 6 threshold voltages UF2-UF7 are respectively supplied to the inverting inputs of the comparators FA2-FA 7. In fig. 4, the power supply + VCC1 may be replaced by another precision power supply, and the voltage divider circuit divides the precision power supply to make the threshold voltage more accurate. The comparators FA2-FA7 are preferably all low-power single-power-supply rail-to-rail operational amplifiers, for example, single-channel rail-to-rail operational amplifiers with the static working power supply current less than 1mA, such as OPA317, AD8517, MCP6291, TLV2450, TLV2451, TLV2460 and TLV2461, are selected.

In FIG. 4, the NOR gates FH2-FH6 constitute controllable power supplies for the comparators FA2-FA6, i.e., the power supplies for the comparators FA2-FA6 are controlled by the outputs Y13-Y17, respectively; the resistors RB2-RB6 are pull-down resistors of the outputs Y12-Y16 respectively, and when the power supply of the corresponding comparator is close to 0V and the output of the corresponding comparator is in a high-impedance state, the level is pulled to be low. The power supply of the comparator FA7 is connected to the power supply + VCC1, and is in a normal working state, and the output Y17 controls the power supplies of the comparators FA2-FA 6. For example, when the voltage of the input alternating-current power supply is high and is in the highest voltage class section 7 of 7 voltage class sections, Y17 outputs high level, all the outputs of NOR gates FH2-FH6 are low level, all the single-power-supply power supplies of comparators FA2-FA6 are close to 0V, all the outputs are close to 0V or high-impedance state, and resistors RB2-RB6 respectively pull the outputs Y12-Y16 to low level. When the input alternating current power supply voltage is not in the highest voltage grade interval 7 of the 7 voltage grade intervals, Y17 outputs low level, NOR gate FH6 outputs high level to provide power supply for comparator FA6, at the moment, if the input alternating current power supply voltage is in the voltage grade interval 6, Y16 outputs high level, NOR gates FH2-FH5 all output low level, single power supply of comparators FA2-FA5 all approach 0V, the output all approach 0V or high impedance state, and resistors RB2-RB5 respectively pull the output Y12-Y15 low level. When the input alternating current power supply voltage is lower than the voltage grade interval 6, Y17 and Y16 both output low level, NOR gates FH6 and FH5 both output high level, and power supplies are respectively provided for comparators FA6 and FA5, at this time, if the input alternating current power supply voltage is in the voltage grade interval 5, Y15 outputs high level, NOR gates FH2-FH4 all output low level, single power supplies of comparators FA2-FA4 are all close to 0V, the outputs are all close to 0V or high resistance state, and resistors RB2-RB4 respectively pull the outputs Y12-Y14 low level. By analogy, when the input alternating-current power supply voltage is in the voltage class interval 4, the Y14 outputs high level, and other outputs are low level; when the input alternating current power supply voltage is in a voltage class interval 3, Y13 outputs high level, and other outputs are low level; when the input alternating current power supply voltage is in a voltage class interval 2, Y12 outputs high level, and other outputs are low level; only when the input ac power supply voltage is at or below the voltage class section 1, the outputs Y12 to Y17 of the comparators FA2 to FA7 are all at the low level, and the lowest section determination value Y11 of the nor gate FH1 is made at the high level. When the nor gate FH1-FH6 selects a 74HC series high-speed CMOS gate, for example, when the 8-input nor gate 74HC4078, the three-input nor gate 74HC27, the four-input nor gate 74HC02, etc. are selected, or when the nor gate function is realized by a 74HC series high-speed CMOS or nor gate, the high-level driving current of the 74HC series high-speed CMOS can reach 4mA, which is enough to drive a single-channel rail-to-rail operational amplifier with the static operating power supply current less than 1 mA. The power supply of the NOR gate FH1-FH6 is power supply + VCC 1.

The fluctuation range of the input alternating current power supply voltage is set as 220V +/-10%, and the input alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. With the sampling comparison circuit embodiment 1 of fig. 4, the voltage input between 242V and 198V can be divided into 7 voltage class intervals with the interval voltage size of 8V, i.e., M is equal to 7, and the trigger gate control value P2 is composed of the whole of Y11-Y17 included in the 7-bit comparison output value; the voltage of 3 voltage class intervals is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of the 3 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 8V is about 220V +/-1.82%, and the requirement that the output is controlled within 220V +/-2% is met; the fluctuation interval of the alternating-current power supply voltage corresponding to the 8V 7 voltage class intervals is 248V to 192V, and the actual fluctuation range of the input voltage is covered. When the compensation is performed by using the compensation type main circuit embodiment 1 of fig. 2, when the voltage on the exciting coil is 220V, the TB1 compensation voltage is 8V, and the TB2 compensation voltage is 16V. The selection of the threshold voltages UF2-UF7 is related to the ratio between the sampled values of the AC supply voltage U1 and the AC supply voltage; setting the proportion of the alternating current power supply voltage sampling value U1 to the alternating current power supply voltage to be 0.01, namely the alternating current power supply voltage sampling value U1 is 1% of the effective value of the alternating current power supply voltage, and the voltage sampling value range corresponding to the voltage input between 242V and 198V is 2.42V to 1.98V; when the alternating current power supply voltage is divided into 7 voltage class intervals with interval voltage of 8V, 6 threshold voltages UF7-UF2 are respectively 2.40V, 2.32V, 2.24V, 2.16V, 2.08V and 2.00V and are 6 middle separation voltage values of voltage sampling values corresponding to the alternating current power supply voltage values separating the 7 voltage class intervals; the difference values of the 6 threshold voltages are the same and are all 0.08V; the middle voltage-dividing resistors RF2-RF6 select the same resistance value, and adjust the resistance values of the upper threshold potentiometer RPH and the lower threshold potentiometer RPL respectively, so that the 6 threshold voltages UF7-UF2 can be adjusted to the required values. In this example, when the input ac power voltage is higher than the maximum voltage level interval range, the output signal corresponding to the maximum voltage level interval in the output trigger gate control value is valid, that is, the output is Y17 valid; at the moment, the main circuit performs corresponding voltage reduction compensation according to the condition that the input alternating current power supply voltage is in the maximum voltage grade interval. When the input alternating current power supply voltage is lower than the range of the minimum voltage class interval, the Y11 output is effective, and the main circuit performs corresponding voltage boosting compensation according to the fact that the input alternating current power supply voltage is in the minimum voltage class interval.

The fluctuation range of the input alternating current power supply voltage is set to be 220V +/-10%, and when the input alternating current power supply voltage is required to be stabilized within the range of 220V +/-4% for output, the number of voltage intervals can be reduced, and frequent adjustment is avoided. With the sampling comparison circuit embodiment 1 of fig. 4, the voltage input between 242V and 198V is divided into 3 voltage class intervals with the interval voltage size of 16V, i.e. M is equal to 3; the voltage of 1 voltage class interval is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of 1 voltage class interval is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage range of 16V is about 220V +/-3.64%, and the requirement that the output is controlled within 220V +/-4% is met; the fluctuation interval of the alternating current power supply voltage corresponding to 3 voltage class intervals of 16V is 244V to 196V, and the actual fluctuation range of the input voltage is covered. At this time, the compensation is performed by using TB2 of the compensation type main circuit embodiment 1 of fig. 2, and when the voltage on the field coil is ac 220V, the TB2 compensation voltage is 16V. And selecting the lowest interval judgment value Y11 and the outputs Y12-Y13 of the comparators FA2-FA3 to form the trigger gating control value P2. The selection of the threshold voltages UF2-UF3 is related to the ratio between the sampled values of the AC supply voltage U1 and the AC supply voltage; setting the proportion of the AC power supply voltage sampling value U1 to the AC power supply voltage to be 0.01, and setting the voltage sampling value range corresponding to the voltage between 242V and 198V to be 2.42V to 1.98V; when the alternating current power supply voltage is divided into 3 voltage class intervals with the interval voltage of 16V, 2 threshold voltages UF3-UF2 are 2.28V and 2.12V respectively, and are 2 middle separation voltage values of voltage sampling values corresponding to the alternating current power supply voltage values separating the 3 voltage class intervals; the resistance values of the upper limit threshold potentiometer RPH and the lower limit threshold potentiometer RPL are respectively adjusted, so that the 2 threshold voltages UF3-UF2 can be adjusted to required values. At this time, the comparators FA4-FA7 work simultaneously, but the threshold voltages of the FAs 4-FA7 are 2.44V, 2.60V, 2.76V and 2.92V respectively, and only when the input alternating current power supply voltage exceeds 244V, the comparators FA4-FA7 can output effective high level; since the input ac power supply voltage is between 242V and 198V, it is impossible to output an active high level in Y14 to Y17 among the outputs of the comparators FA4 to FA7, and the trigger gate control value P2 is composed of Y11 to Y13 included in the 7-bit comparison output value.

Since the compensation mode of the compensation type main circuit embodiment 1 automatically has the schmitt characteristic, the comparator FA2 to the comparator FA7 do not constitute a schmitt comparator. The trigger strobe control value output in FIG. 4 is active high; the output end of each of the comparators FA2-FA7 is added with a stage of inverter, and the NOR gate FH1 is changed into an OR gate, so that the output trigger gating control value is changed into low level and effective.

Embodiment 1 of fig. 4 may be performed for the compensated main circuit embodiment 2, and in this case, it is necessary to divide the voltage in the ac power supply voltage fluctuation interval range into more voltage class intervals. For example, when the voltage in the fluctuation interval of the ac power supply voltage is divided into 15 voltage class intervals, the circuit of fig. 4 should be extended to 14 comparators for comparison with 14 threshold voltages of different sizes; the output trigger strobe control value P2 would consist of 15 bits, e.g., Y11-Y115.

Fig. 5 shows a sample comparison circuit embodiment 2, where m is equal to 10, for performing compensation control on the compensated main circuit embodiment 2. In fig. 5, FD1 is a true effective value detection device LTC1966, and the LTC1966, a transformer TV1, a capacitor CV2, and a capacitor CV3 constitute an ac power supply voltage sampling circuit, and the ac power supply voltage input from a phase line LA1 and a neutral line N is measured to obtain an ac power supply voltage sampling value U2. UIN1 and UIN2 of LTC1966 are alternating voltage differential input terminals, USS is a negative power input terminal capable of being grounded, UDD is a positive power input terminal, GND is a ground terminal, EN is a low-level effective enable control input terminal, UOUT is a voltage output terminal, and COM is an output voltage return terminal.

In fig. 5, FD2, RD1, RD2 constitute a multi-interval voltage comparator circuit; FD2 is a 10-level comparison display driver LM3914, and the inside of the LM3914 includes 10 internal divider circuits with 1k Ω precision resistors connected in series, which form 10 comparison threshold voltages and are connected to the positive input terminals of the 10 comparators respectively, and divides the voltage in the fluctuation range of the ac power supply voltage into 10 voltage class intervals 1-10 at most. Pin 6 is the high end of the inner voltage divider circuit and is connected to the power supply + VCC1 through the upper threshold potentiometer RD 1; pin 4 is the low end of the internal voltage divider circuit and is connected to the ground through a lower threshold potentiometer RD 2; pin 8 is the low end of the internal standard power supply and is connected to the ground; pin 2 is a negative power supply end and is connected to the ground; pin 3 is a positive power supply terminal and is connected to a power supply + VCC 1; pin 5 is a signal input end, is connected to an alternating current power supply voltage sampling value U2 and is internally connected to the negative input ends of 10 comparators; signals Y110 to Y11 output by pins 10-18 and pin 1 are output results of 10 comparators, wherein Y110 has the highest comparison threshold voltage and is sequentially reduced, and Y11 has the lowest comparison threshold voltage; Y1-Y110 are all effective at low level to form a comparison output value with 10 effective at low level; the mode control end of the 9 pins is suspended to realize the dot output from Y11 to Y110, namely only a single low level output from Y11 to Y110 is effective; when the input alternating current power supply voltage is in a voltage grade interval 10, Y110 outputs a low level, and other outputs are high levels; when the input alternating current power supply voltage is in a voltage level interval 9, Y19 outputs low level, and other outputs are high level; when the input alternating current power supply voltage is in a voltage level interval 5, Y15 outputs low level, and other outputs are high level; when the input ac power supply voltage is in voltage class interval 1, Y11 outputs a low level, and the other outputs are high levels.

The input alternating current power supply voltage fluctuation range is set to be 220V + 10% to 220V-20%, and the output is required to be stabilized within the range of 220V +/-2%. With the sampling comparison circuit embodiment 2 of fig. 5, the voltage input between 242V and 176V is divided into 10 voltage class intervals with interval voltage of 7V, i.e., M is equal to 10, and the trigger strobe control value P2 is composed of Y11-Y110 included in the 10-bit comparison output value as a whole; the voltage of 3 voltage class intervals is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of the 6 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 7V is 220V +/-1.6%, the requirement that the output is controlled within 220V +/-2% is met, the alternating current power supply voltage fluctuation interval corresponding to 10 voltage class intervals of 7V is 244.5V to 174.5V, and the actual range of voltage fluctuation is covered. When the voltage on the exciting coil is 220V, the TB1 compensation voltage is 7V, the TB2 compensation voltage is 14V, and the TB3 compensation voltage is 28V, the compensation is performed by using the compensation type main circuit embodiment 2 of fig. 3. The selection of the threshold voltage is related to the ratio between the sampled value of the ac supply voltage U2 and the ac supply voltage; setting the proportion of the alternating current power supply voltage sampling value U2 to the alternating current power supply voltage to be 0.005, namely the alternating current power supply voltage sampling value U2 is 0.5% of the effective value of the alternating current power supply voltage, and the voltage sampling value range corresponding to the voltage input between 242V and 176V is 1.21V to 0.88V; when the alternating current power supply voltage is divided into 10 voltage grade intervals with the interval voltage of 7V, 10 threshold voltages are respectively 1.1875V, 1.1525V, 1.1175V, 1.0825V, 1.0475V, 1.0125V, 0.9775V, 0.9425V, 0.9075V and 0.8725V and respectively correspond to voltage sampling values for dividing the voltage range from 244.5V to 174.5V into 10 lower limit values of the voltage grade intervals; the voltage at the high end of the inner voltage divider circuit is connected to the positive input end of the highest comparator, so that the voltage at the 6 pin is 1.1875V. According to the magnitude of the internal standard power output VREF (1.2V or 1.25V) and the magnitude of the internal 10 precision resistors, 10 threshold voltages can be obtained by adjusting the resistance values of the upper threshold potentiometer RD1 and the lower threshold potentiometer RD 2. If the precision of voltage compensation is required to be improved or the fluctuation range of the input voltage is required to be larger, the sampling comparison circuit in embodiment 2 of fig. 5 is required to divide the voltage class into more voltage class intervals, for example, when the voltage in the fluctuation range of the ac power supply voltage needs to be divided into 15 voltage class intervals, 2 LM3914 slices can be adopted for implementation, and the inner voltage divider circuits in the 2 LM3914 slices are connected in series to form 20 comparison threshold voltages, so as to form a 20-stage comparator circuit; selecting 15 of the comparison outputs, the output trigger strobe control value P2 will consist of 15 bits, e.g., Y11-Y115.

In embodiment 2 of the sampling comparison circuit in fig. 5, when the input ac power voltage is higher than the range of the maximum voltage class interval, the output trigger strobe control value is valid for the output signal corresponding to the maximum voltage class interval, that is, the output is valid for Y110, and the main circuit performs corresponding voltage step-down compensation according to the ac power voltage in the maximum voltage class interval. When the input alternating current power supply voltage is lower than the range of the minimum voltage grade interval, all signals in the output trigger gating control value are invalid, and the main circuit does not perform voltage compensation at the moment.

In fig. 5, 10 comparators out of 10 comparators in LM3914 are used to divide the ac power supply voltage comparison into 10 voltage class intervals. Only 9 comparators in 10 comparators in LM3914 can be adopted to compare and divide the alternating current power supply voltage into 10 voltage grade intervals; the comparison threshold voltages of the 9 comparators are 9 middle separation voltage values of the voltage sampling values corresponding to the alternating current power supply voltage values separated by 10 voltage class intervals; for example, the comparison threshold voltage of each comparator is not changed, the output of pin 1 of LM3914 in FIG. 5 is not used as Y11, Y11 is selected and generated by Y12-Y110 control in the trigger gate control value, namely Y11 is enabled when all Y12-Y110 are disabled, otherwise Y11 is disabled; at the moment, when the input alternating current power supply voltage is in or is higher than the range of the maximum voltage grade interval, the output trigger gating control value is Y110 valid, and the main circuit performs corresponding voltage reduction compensation according to the situation that the alternating current power supply voltage is in the maximum voltage grade interval; when the input alternating current power supply voltage is in or lower than the range of the minimum voltage class interval, Y11 output is effective, and the main circuit performs corresponding voltage boosting compensation according to the fact that the input alternating current power supply voltage is in the range of the minimum voltage class interval.

The fluctuation range of the input alternating current power supply voltage is set to be 220V +/-15%, the alternating current power supply voltage is required to be stabilized within the range of 220V +/-3.5% for output, the requirement on voltage stabilization precision is lowered, the number of voltage intervals can be reduced at the moment, and frequent adjustment is avoided. With the sampling comparison circuit embodiment 2 of fig. 5, the voltage input between 253V and 187V is divided into 5 voltage class intervals with interval voltage size of 14V, i.e., M is equal to 5; the voltage of 2 voltage class intervals is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of 2 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 14V is less than 220V +/-3.2%, the requirement that the output is controlled within 220V +/-3.5% is met, the voltage fluctuation interval of the alternating current power supply corresponding to 5 voltage grade intervals of 14V is 255V-185V, and the actual range of voltage fluctuation is covered. The compensation is performed by using TB2 and TB3 in the compensation-type main circuit embodiment 2 of fig. 3, and when the voltage on the field coil is 220V, the TB2 compensation voltage is 14V and the TB3 compensation voltage is 28V. The sampled value U2 of the AC power supply voltage is 0.5% of the effective value of the AC power supply voltage, and the sampled value range of the voltage corresponding to the voltage input between 253V and 187V is 1.265V to 0.935V; when the alternating current power supply voltage is divided into 5 voltage grade intervals with the interval voltage of 14V, 5 threshold voltages are respectively 1.205V, 1.135V, 1.065V, 0.995V and 0.925V and are respectively voltage sampling values corresponding to the lower limit values of the alternating current power supply voltage values of the 5 voltage grade intervals; adjusting the resistance values of an upper limit threshold potentiometer RD1 and a lower limit threshold potentiometer RD2 to enable the threshold voltages of 5 comparators with lower threshold voltages in the LM3914 to be the 5 threshold voltages, and signals Y15-Y1 output by pins 15-18 and 1 are output results of the 5 comparators, wherein Y15 has the highest comparison threshold voltage and is sequentially reduced, and Y11 has the lowest comparison threshold voltage; the 10-bit comparison output values are all active low, and Y11-Y15 included in the 10-bit comparison output values form a trigger gating control value P2. At this time, the comparison threshold of the comparators outputting Y16 to Y110 is 1.275V or more, and the corresponding ac power supply voltage value is 255V, which is out of the actual input voltage range, and therefore, Y16 to Y110 in fig. 5 cannot output an effective low level.

The embodiment 2 of the sampling comparison circuit in fig. 5 can also perform compensation control on the compensation type main circuit embodiment 1, and at this time, only the voltage in the fluctuation interval range of the input ac power voltage needs to be divided into intervals of no more than 7 voltage classes, that is, the comparison output of no more than 7 classes is selected.

In addition to the sampling comparison circuit embodiment of fig. 4 or 5, when compensation control is performed for the compensation type main circuit embodiment 1 or embodiment 2, another ac power supply voltage sampling circuit and comparison circuit may be selected to realize a desired function. The ac power voltage sampling value U1 output by the ac power voltage sampling circuit of fig. 4 may be sent to the multi-interval voltage comparator circuit of fig. 5 for comparison, and a trigger gating control value is output; the sampled value U2 of the ac power voltage output by the ac power voltage sampling circuit of fig. 5 may be sent to the multi-interval voltage comparator circuit of fig. 4 for comparison, and a trigger gating control value is output.

FIG. 6 is a block diagram of an embodiment of a delay protection circuit, wherein a delay detection module YC1 respectively delays input signals Y11-Y1M including M-bit trigger strobe control values Y11-Y1M to obtain delayed signals Y21-Y2M, wherein Y21-Y2M form a delayed trigger strobe control value P3; the YC1 module simultaneously and respectively carries out edge detection on the input signals Y11-Y1m to obtain edge detection signals Y31-Y3 m; the triggerless area control signal generation module YC2 inputs the edge detection signals Y31-Y3M, and converts the edge variation in the M-bit trigger gate control value Y11-Y1M into a triggerless area control signal P4 for output. In the block diagram of the embodiment in fig. 6, when the input of the delay detection module YC1 is the trigger gating control value output by the sampling comparison circuit embodiment 1 in fig. 4, m is equal to 7; in the block diagram of the embodiment in fig. 6, when the input of the delay detection module YC1 is the trigger strobe control value output by the sampling comparison circuit embodiment 2 in fig. 5, m is equal to 10.

Fig. 7 shows an embodiment 1 of a delay detection circuit for the input signal Y11 in the delay detection module. The resistor RY0, the capacitor CY0 and the driving gate FY0 realize signal delay of Y11, and a delayed signal Y21 of Y11 is obtained. The resistor RY1, the capacitor CY1, the diode DY1 and the inverter FY1 form a rising edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is output in the output signal YP1 of the inverter FY 1. The resistor RY2, the capacitor CY2, the diode DY2, the inverters FY2 and FY3 constitute a falling edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the falling edge of Y11 is output in the output signal YP2 of the inverter FY 3. The nand gate FY4 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY4, that is, when the input signal Y11 changes, the nand gate FY4 outputs a single pulse in the form of a positive pulse. In fig. 7, the drive gate FY0, inverter FY1, inverter FY3 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; the drive gate FY0 may consist of 2 inverters with schmitt inputs.

Fig. 8 shows an embodiment 2 of the delay detection circuit for the input signal Y11 in the delay detection module. The inverter FY5, the resistor RY3 and the capacitor CY3 invert and delay the input signal Y11 to obtain a delayed inverted signal YP0 of Y11; the inverter FY6 inverts YP0 to obtain a delayed Y11 signal Y21. The signal input by the nand gate FY7 is a delayed inverted signal YP0 of Y11 and Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is generated in the output signal YP 1; the or gate FY8 receives the inverted signals YP0 of Y11 and Y11, and the output signal YP2 generates a single pulse in the form of a negative pulse corresponding to the falling edge of Y11. The nand gate FY9 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY9, that is, when the input signal Y11 changes, the nand gate FY9 outputs a single pulse in the form of a positive pulse. In fig. 8, inverter FY6, nand gate FY7, or gate FY8 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; nand gate select 74HC132, CD4093, etc.; or gate select 74HC7032 or 2 inverters with schmitt inputs and 1 nand gate to implement the or gate function.

Fig. 9 is a delay detection circuit embodiment 3 for the input signal Y11 in the delay detection module, wherein a rising edge detection circuit for the input signal Y11 is composed of the resistor RY1, the capacitor CY1, the diode DY1 and the inverter FY1, and a falling edge detection circuit for the input signal Y11 is composed of the resistor RY2, the capacitor CY2, the diode DY2, the inverter FY2 and the inverter FY3, and a circuit for outputting the edge detection signal Y31 by using the nand gate FY4 is the same as in embodiment 1 of fig. 7. In fig. 9, the signal delay of Y11 is realized by inverters FY11, FY12, FY13, and FY14, and a delayed signal Y21 of Y11 is obtained.

The delay detection circuits of the embodiments 1 to 3 in fig. 7, 8 and 9 are all delay detection circuits for the input signal Y11, and the delay detection circuits for the other signals Y12-Y1m have the same circuit structure and function as those of the corresponding embodiments for performing delay detection on the input signal Y11. The delay detection circuit may also adopt other circuits meeting the requirements to realize the functions thereof.

The function of the no-trigger area control signal generation module is to output a single pulse in the no-trigger area control signal when any one or more of the input edge detection signals for triggering the strobe control value generate a single pulse related to an edge. FIG. 10 is a non-trigger area control signal generating module embodiment, in which a circuit including m input NOR gates FY10, m pull-down resistors Rz1-Rzm, and m edge-detecting signal gate switches z1-zm is used to implement corresponding functions, m bit edge-detecting signals Y31-Y3m are respectively connected to m input terminals of the NOR gates FY10 via the edge-detecting signal gate switches z1-zm, and the pull-down resistors RZ1-RZm are used to pull down the corresponding input signals of the NOR gates FY10 to a low level when a certain one of the edge-detecting signal gate switches z1-zm is open; the nor gate FY10 outputs the no trigger area control signal P4. In the embodiment of fig. 10, the single pulse that does not trigger the output of the zone control signal is a negative pulse, i.e., the low level of the zone control signal is not active; when the nor gate FY10 is replaced by an or gate, the single pulse that does not trigger the zone control signal output is a positive pulse. If the single pulse associated with an edge generated in the input edge detection signals Y31-Y3M is a negative pulse, the nor gate FY10 in fig. 10 should be changed to a nand gate or an and gate to implement an or logic function under negative logic.

The m-bit comparison output values output by the sampling comparison unit are all sent to the m-bit input end of the delay protection unit; the M edge detection signal gating switches z1-zm are used for connecting M bit trigger gating control values in M bit comparison output values to the input end of the NOR gate FY10, and when M is smaller than M, redundant input signals are not connected to the input end of the NOR gate FY 10; for example, when M equals 7 and M also equals 7, the edge detection signal gate switches z1-z7 are all turned on; when M is equal to 7, and M is equal to 3, the edge detection signal gating switch z1-z3 is turned on, z4-z7 is turned off, and the pull-down resistor RZ4-RZ7 pulls down the signal at the input end of the NOR gate FY10 behind the switch z4-z7 to low level, and at the moment, the non-trigger area control signal is generated by edge change in Y11-Y13. In embodiments 1 and 2 of the sampling comparison unit, when M is smaller than M, other data in M-bit data except the M-bit trigger strobe control value does not change, for example, when M is equal to 3 in embodiment 1 of the sampling comparison unit, the remaining 4 bits output a constant low level, and no edge detection signal is generated; when M is equal to 5 in embodiment 2 of the sampling comparison unit, the output of the remaining 5 bits is a constant high level, and no edge detection signal is generated; therefore, when M is smaller than M, even if all of the M-bit edge detection signals Y31-Y3M are connected to the input terminal of the nor gate FY10, the signals other than the M-bit trigger gate control value in the M-bit comparison output value do not cause a single pulse to be output in the no-trigger area control signal; therefore, when the sampling comparison unit in embodiment 1 or embodiment 2 is used to output m-bit comparison output values, the m pull-down resistors Rz1-Rz m and the m edge detection signal gate switches z1-zm in fig. 10 may not be used, and the m-bit edge detection signals Y31-Y3m are directly and entirely connected to the input terminal of the nor gate FY 10.

All gates in the delay protection circuit are powered by a single power supply + VCC 1. Fig. 11 is a diagram illustrating a part of related waveforms in the delay protection circuit. From the principle and requirements of the sampling comparison circuit, when the output trigger strobe control value is changed normally, 2 bits are changed every time. In fig. 11, Y11 in the trigger strobe control values has a rising edge change and a falling edge change respectively, and Y21 is the trigger strobe control value of Y11 delayed by T1 time; in embodiment 1 of the delay detection circuit in fig. 7, T1 is determined by the magnitude of the product of the resistor RY0 and the capacitor CY0 (i.e., the magnitude of the time constant); in embodiment 2 of the delay detection circuit in fig. 8, T1 is determined by the product of the resistor RY3 and the capacitor CY 3; in the embodiment 3 of the delay detection circuit in fig. 9, T1 is determined by the gate delay time of the inverters FY11, FY12, FY13 and FY 14. In fig. 11, the negative pulse width of the signal YP1 due to the rising edge of Y11 is T2; in the delay detection circuit embodiment 1 of fig. 7 and the delay detection circuit embodiment 3 of fig. 9, T2 is determined by the magnitude of the product of the resistor RY1 and the capacitor CY 1; in embodiment 2 of the delay detection circuit in fig. 8, T2 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 11, the negative pulse width generated by the falling edge of Y11 in the signal YP2 is T3; in the delay detection circuit embodiment 1 of fig. 7 and the delay detection circuit embodiment 3 of fig. 9, T3 is determined by the magnitude of the product of the resistor RY2 and the capacitor CY 2; in embodiment 2 of the delay detection circuit in fig. 8, T3 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 11, 2 positive pulses in the edge detection signal Y31 correspond to a negative pulse due to a rising edge of Y11 in the signal YP1 and a negative pulse due to a falling edge of Y11 in the signal YP2, respectively. When Y11 in the trigger gate control value in fig. 11 changes in rising edge, Y12 in the trigger gate control value changes in falling edge, and the corresponding edge detection signal Y32 generates a positive pulse correspondingly; when Y11 is changed by a falling edge, Y12 in the trigger gate control value is changed by a rising edge at the same time, and a positive pulse is correspondingly generated in the corresponding edge detection signal Y32; during this period, the comparison output value signals including the trigger strobe control value signals other than Y11 and Y12 are unchanged, and the corresponding edge detection signals are all at low level, which is not shown in fig. 11. According to the logical or function of the non-trigger area control signal generation module, the width of the single pulse output by the non-trigger area control signal generation module is the same as the widest pulse width of the input pulses in the input edge detection signals, and the width difference is caused by the difference between the resistance and capacitance values of T2 and T3 determined in the different delay detection circuits. In fig. 11, the 1 st positive pulse in Y31 is wider than the 1 st positive pulse in Y32, the 2 nd positive pulse in Y31 is narrower than the 2 nd positive pulse in Y32, the 1 st negative pulse width in the no-trigger-region control signal P4 coincides with the 1 st positive pulse width in the edge detection signal Y31, and the 2 nd negative pulse width in the no-trigger-region control signal P4 coincides with the 2 nd positive pulse width in the edge detection signal Y32.

In the embodiment 1 of the delay detection circuit of the delay protection circuit in fig. 7, the delay time for the trigger gate control value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY1 and FY4 and FY10 in fig. 10, or the sum of the delay times of the gates FY3 and FY4 and FY10 in fig. 10; the selection range of the signal delay time T1 of the trigger gate control value determined by the product of the resistor RY0 and the capacitor CY0 is ms order of magnitude, obviously, is greater than the delay time of the trigger gate control value changing to the leading edge of the corresponding single pulse of the no-trigger area control signal, that is, the time of the delay change of the trigger gate control value signal is later than the leading edge time of the single pulse output after the trigger gate control value changes. Strictly speaking, T1 actually includes the sum of the delay time caused by resistor RY0 and capacitor CY0, and the delay time of gate FY 0. In embodiment 1 of fig. 7, when selecting parameters, the value of T2 and the value of T3 are both greater than the value of T1, so that the time of delayed change of the trigger gate control value signal meets the requirement of earlier time of the trailing edge of a single pulse of the control signal of the non-trigger area output after the change of the trigger gate control value.

In the embodiment 2 of the delay detection circuit in the delay protection circuit of fig. 8, the delay time for the trigger gate control value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY7 and FY9 and FY10 in fig. 10, or the sum of the delay times of the gates FY8 and FY9 and FY10 in fig. 10; t1 is a value of ms magnitude, and it is obvious that the signal delay time T1 of the trigger gate control value determined by the product of the resistor RY3 and the capacitor CY3 is longer than the delay time of the trigger gate control value changing to the leading edge of the corresponding single pulse of the non-trigger area control signal, i.e. the time of the trigger gate control value signal delay changing is later than the leading edge of the single pulse output after the trigger gate control value changing. In the embodiment 2 of the delay detection circuit in fig. 8, both the time when the trigger gate control value signal changes in delay and the time when the trailing edge of the output single pulse after the trigger gate control value changes are affected by the change of the signal YP 0; the time when the delay of the trigger gating control value signal changes is the delay of the gate circuit FY6 after the signal YP0 changes; the trailing edge time of the single pulse output after the trigger gating control value is the sum of the delay time of the gate circuits FY7 and FY9 after the signal YP0 is changed and FY10 in the graph 10, or the sum of the delay time of the gate circuits FY8 and FY9 after the signal YP0 is changed and FY10 in the graph 10; obviously, the time of the delayed change of the trigger gating control value signal is less than the time of the back edge of the output single pulse after the change of the trigger gating control value by 2 gate circuits, and the requirement that the time of the delayed change of the trigger gating control value signal is earlier than the time of the back edge of the output single pulse after the change of the trigger gating control value is met.

Fig. 12 is a circuit embodiment of a trigger circuit for triggering the compensation type main circuit 1 in fig. 2 or triggering the triac SR1 in the compensation type main circuit 2 in fig. 3, and the circuit embodiment includes an ac trigger optocoupler UG1, a resistor RG1, and a resistor RG2, and the trigger control signal P51 is active at a low level. The alternating current trigger optocoupler UG1 can be selected from phase-shifting bidirectional thyristor output optocouplers such as MOC3022, MOC3023, MOC3052 and MOC 3053. Power supply + VCCK is the controlled power supply controlled by the protected drive circuit. The circuit structure of the trigger circuit for triggering the triacs SR2-SR6 in the compensated main circuit embodiment 1 in FIG. 2 or the triacs SR2-SR8 in the compensated main circuit embodiment 2 in FIG. 3 is the same as that of the triac SR 1. The trigger pulses output by the alternating current trigger optocoupler UG1 in fig. 12 from G11 and G12 and the trigger pulses output by other alternating current trigger optocouplers in the trigger circuit jointly form a trigger signal P6.

Fig. 13 is an embodiment 1 of a thyristor-triggered gating configuration circuit, which is used to implement a triggered gating configuration when the trigger gating control value is active high and M is equal to 7, i.e., M does not exceed 7, the trigger control signal is active low and N is equal to 6. In fig. 13, 42 diodes D11-D76, 42 configuration switches K11-K76, 7 trigger control row lines Y21-Y27, and 6 trigger drive column lines VK1-VK6 form a diode trigger configuration matrix, resistors RS1-RS6 and triodes VS1-VS6 form a drive circuit of trigger control signals P51-P56, and at most, P51-P56 form a trigger control signal P5 to control 6 thyristors. At the crossing positions of 7 trigger control row lines Y21-Y27 and 6 trigger drive column lines VK1-VK6, configuration branches composed of diodes and configuration switches in series are arranged, the anode sides of the diodes of the configuration branches are connected to the trigger control row lines, and the cathode sides of the diodes of the configuration branches are connected to the trigger drive column lines.

Using the thyristor-triggered-gate configuration circuit embodiment 1 of fig. 13 for compensation control for the compensated main circuit embodiment 1 of fig. 2; setting the fluctuation range of the alternating current power supply voltage as 220V +/-10%, and requiring the alternating current power supply voltage to be stabilized within the range of 220V +/-2% for output; at this time, the trigger strobe control value is Y21-Y27 of 7 bits, and all of the 7 trigger control row lines Y21-Y27 in FIG. 13 are selected as trigger strobe control row lines. Table 1 is a trigger gating configuration table of the thyristor trigger gating configuration circuit, and lists the configuration states of the configuration switches in the diode trigger configuration matrix when the 7-bit trigger gating control values Y21-Y27 are respectively valid and the corresponding valid trigger control signals are configured. The trigger gating control values Y21-Y27 are respectively corresponding to the voltage level intervals 1-7, and the thyristor trigger gating configuration circuit controls the on-off state of the bidirectional thyristor in the compensation type main circuit embodiment 1 to perform corresponding voltage compensation according to the trigger gating control values through trigger control signals. In table 1, the listed configuration switches need to be configured in the on state, and the unlisted configuration switches need to be configured in the off state; a total of 21 configuration switches in table 1 need to be configured in the on state. When a certain trigger gating control row line is effective, the configuration switch between the trigger driving row lines of the bidirectional thyristor which needs to be conducted in the corresponding on-off combination state when the certain trigger gating control row line is effective is configured to be in a conducting state, and the configuration switch is connected through the diode, so that the trigger driving row line of the bidirectional thyristor which needs to be conducted is effective. For example, when the input voltage is at the lowest voltage level 1, that is, Y21 is at a high level, K11, K14 and K16 in the diode trigger configuration matrix are turned on to turn on diodes D11, D14 and D16, and trigger drive row lines VK1, VK4 and VK6 are at a high level to control transistors VS1, VS4 and VS6 to be turned on to make P51, P54 and P56 effectively turn on triacs SR1, SR4 and SR6, and other diodes in the diode trigger configuration matrix are turned off to control and turn off triacs SR2, SR3 and SR5 to make TB1 and TB2 perform forward compensation; when the input voltage is in a voltage class 2, namely Y22 is effectively in a high level, K21, K23 and K26 in the diode trigger configuration matrix are conducted, diodes D21, D23 and D26 are conducted, transistors VS1, VS3 and VS6 are respectively controlled to be conducted to trigger and drive row lines VK1, VK3 and VK6 to be in a high level, so that P51, P53 and P56 effectively turn on the bidirectional thyristors SR1, SR3 and SR6, other diodes in the diode trigger configuration matrix are turned off, the bidirectional thyristors SR2, SR4 and SR5 are controlled to be turned off, and only TB2 is subjected to forward compensation; when the input voltage is in a voltage level 4, namely Y24 is effectively in a high level, K41, K43 and K45 in the diode trigger configuration matrix are conducted, diodes D41, D43 and D45 are conducted, trigger driving row lines VK1, VK3 and VK5 are in a high level to respectively control triodes VS1, VS3 and VS5 to be conducted, so that P51, P53 and P55 effectively turn on bidirectional thyristors SR1, SR3 and SR5, other diodes in the diode trigger configuration matrix are turned off, and control turning off the bidirectional thyristors SR2, SR4 and SR6 to realize 0-voltage compensation, namely TB1 and TB2 are not compensated; when the input voltage is at voltage level 5, that is, Y25 is at high level, K52, K53 and K56 in the diode trigger configuration matrix are turned on to turn on diodes D52, D53 and D56, trigger and drive row lines VK2, VK3 and VK6 to be at high level to control triodes VS2, VS3 and VS6 to be turned on respectively to make P52, P53 and P56 effectively turn on bidirectional thyristors SR2, SR3 and SR6, and other diodes in the diode trigger configuration matrix are turned off to control and turn off bidirectional thyristors SR1, SR4 and SR5 to make TB1 perform reverse compensation only; when the input voltage is in a voltage level of 7, namely Y27 is effectively in a high level, K72, K73 and K75 in the diode trigger configuration matrix are conducted, diodes D72, D73 and D75 are conducted, trigger driving row lines VK2, VK3 and VK5 are in a high level to respectively control triodes VS2, VS3 and VS5 to be conducted so that P52, P53 and P55 can effectively turn on bidirectional thyristors SR2, SR3 and SR5, other diodes in the diode trigger configuration matrix are cut off, and reverse compensation is carried out on bidirectional thyristors SR1, SR4, SR6, TB1 and TB 2; and so on.

TABLE 1

The thyristor-triggered gating configuration circuit embodiment 1 of fig. 13 is used for compensation control of the compensation-type main circuit embodiment 1 of fig. 2, the fluctuation range of the alternating-current power supply voltage is 220V ± 10%, and the alternating-current power supply voltage is required to be stabilized within a range of 220V ± 4% for output; at this time, the trigger strobe control value is Y21-Y23 with 3 bits, and 3 trigger control row lines Y21-Y23 in FIG. 13 are selected as the trigger strobe control row lines. Table 2 is a trigger gating configuration table of the thyristor trigger gating configuration circuit at this time, and lists the configuration states of the configuration switches in the diode trigger configuration matrix when the corresponding valid trigger control signals are configured when the 3-bit trigger gating control values Y21-Y23 are valid respectively. The trigger strobe control values Y21-Y23 effectively correspond to voltage level intervals 1-3, respectively.

In table 2, the listed configuration switches need to be configured in the on state, and the unlisted configuration switches need to be configured in the off state; in table 2, a total of 9 configuration switches need to be configured in the on state. For example, when the input voltage is at the lowest voltage level 1, that is, Y21 is at the high level, K11, K13 and K16 in the diode trigger configuration matrix are turned on to turn on diodes D11, D13 and D16, and trigger drive row lines VK1, VK3 and VK6 are at the high level to control transistors VS1, VS3 and VS6 to turn on transistors P51, P53 and P56 to effectively turn on triacs SR1, SR3 and SR6, and other diodes in the diode trigger configuration matrix are turned off to control and turn off triacs SR2, SR4 and SR5 to perform forward compensation on TB 2; when the input voltage is in a voltage class 2, namely Y22 is effectively in a high level, K21, K23 and K25 in the diode trigger configuration matrix are conducted, diodes D21, D23 and D25 are conducted, trigger driving row lines VK1, VK3 and VK5 are in a high level to respectively control triodes VS1, VS3 and VS5 to be conducted, so that P51, P53 and P55 effectively turn on bidirectional thyristors SR1, SR3 and SR5, other diodes in the diode trigger configuration matrix are turned off, and control turning off the bidirectional thyristors SR2, SR4 and SR6 to realize 0-voltage compensation; when the input voltage is in the voltage class 3, that is, Y23 is at a high level, K32, K34 and K35 in the diode trigger configuration matrix are turned on to turn on diodes D32, D34 and D35, trigger driving row lines VK2, VK4 and VK5 to be at a high level to control transistors VS2, VS4 and VS5 to be turned on respectively to make P52, P54 and P55 effectively turn on bidirectional thyristors SR2, SR4 and SR5, and other diodes in the diode trigger configuration matrix are turned off to control bidirectional thyristors SR1, SR3 and SR6 to perform reverse compensation on TB 2.

TABLE 2

Fig. 14 shows an embodiment 2 of the thyristor-triggered gating configuration circuit, which is used to implement the triggered gating configuration when the trigger gating control value is active low and M is equal to 10, i.e., M does not exceed 10, and the trigger control signal is active low and 8, i.e., N is equal to 8. In fig. 14, 80 diodes D01-D98, 80 configuration switches K01-K98, 10 trigger control row lines Y21-Y210, and 8 trigger driving column lines VK1-VK8 form a diode trigger configuration matrix, and 8 trigger driving column lines VK1-VK8 in the diode trigger configuration matrix directly output low-level active trigger control signals P51-P58. At the crossing positions of 10 trigger control row lines Y21-Y210 and 8 trigger driving column lines VK1-VK8, configuration branches composed of diodes and configuration switches connected in series are arranged, the cathode sides of the diodes of the configuration branches are connected to the trigger control row lines, and the anode sides of the diodes of the configuration branches are connected to the trigger driving column lines. The main difference between the thyristor-triggered gating configuration circuit embodiment 2 of fig. 14 and the thyristor-triggered gating configuration circuit embodiment 1 of fig. 13 is that the trigger gating control value is active low, and the diodes that are turned on by the active low of the trigger gating control value are configured to directly serve as the driving source of the light emitting diodes at the input ends of the plurality of ac-triggered optocouplers, without the trigger control signal driving circuit.

Using the thyristor-triggered-gate configuration circuit embodiment 2 of fig. 14 for compensation control for the compensated main circuit embodiment 2 of fig. 3; setting the fluctuation range of the alternating current power supply voltage to be 220V + 10% to 220V-20%, and requiring the alternating current power supply voltage to be stabilized within the range of 220V +/-2% for output; at this time, the trigger strobe control value is Y21-Y210 with 10 bits, and all of the 10 trigger control row lines Y21-Y210 in FIG. 14 are selected as trigger strobe control row lines. Table 3 is a trigger gating configuration table of the thyristor trigger gating configuration circuit at this time, and lists the configuration states of the configuration switches in the diode trigger configuration matrix when the corresponding valid trigger control signals are configured when the trigger gating control values Y21-Y210 of 10 bits are valid respectively. The trigger gating control values Y21-Y210 effectively correspond to the voltage class intervals 1-10, and the thyristor trigger gating configuration circuit controls the on-off state of the bidirectional thyristor in the compensation type main circuit embodiment 2 to perform corresponding voltage compensation according to the trigger gating control values through the trigger control signals. In table 3, the listed configuration switches need to be configured in the on state, and the unlisted configuration switches need to be configured in the off state; a total of 40 configuration switches in table 3 need to be configured in the on state. When a certain trigger gating control row line is effective, the configuration switch between the trigger driving row lines of the bidirectional thyristor which needs to be conducted in the corresponding on-off combination state when the certain trigger gating control row line is effective is configured to be in a conducting state, and the configuration switch is connected through the diode, so that the trigger driving row line of the bidirectional thyristor which needs to be conducted is effective. For example, when the input voltage is at voltage level 7, that is, Y27 is active at low level, K71, K73, K75, and K77 in the diode-triggered configuration matrix are turned on, so that diodes D71, D73, D75, and D77 are turned on, row lines VK1, VK3, VK5, and VK7 are triggered to be at low level to turn on triacs SR1, SR3, SR5, and SR7, and other diodes in the diode-triggered configuration matrix are turned off, so that triacs SR2, SR4, SR6, and SR8 are turned off, and 0-voltage compensation is realized, that is, none of TB1, TB2, and TB3 is compensated; when the input voltage is in a voltage level 8, namely Y28 is effectively in a low level, K82, K83, K86 and K88 in the diode trigger configuration matrix are switched on, diodes D82, D83, D86 and D88 are switched on, row lines VK2, VK3, VK6 and VK8 are triggered and driven to be in a low level to switch on the bidirectional thyristors SR2, SR3, SR6 and SR8, other diodes in the diode trigger configuration matrix are switched off, the bidirectional thyristors SR1, SR4, SR5 and SR7 are switched off, and TB1 is reversely compensated; when the input voltage is in a voltage class 9, namely Y29 is effectively in a low level, K92, K94, K95 and K98 in the diode trigger configuration matrix are switched on, diodes D92, D94, D95 and D98 are switched on, row lines VK2, VK4, VK5 and VK8 are triggered and driven to be in a low level to switch on the bidirectional thyristors SR2, SR4, SR5 and SR8, other diodes in the diode trigger configuration matrix are switched off, the bidirectional thyristors SR1, SR3, SR6 and SR7 are switched off, and TB2 is reversely compensated; when the input voltage is in a voltage level of 10, namely Y210 is effectively in a low level, K02, K03, K05 and K08 in the diode trigger configuration matrix are switched on, diodes D02, D03, D05 and D08 are switched on, row lines VK2, VK3, VK5 and VK8 are triggered and driven to be in a low level to switch on the bidirectional thyristors SR2, SR3, SR5 and SR8, other diodes in the diode trigger configuration matrix are switched off, the bidirectional thyristors SR1, SR4, SR6 and SR7 are switched off, and TB1 and TB2 are simultaneously subjected to reverse compensation; when the input voltage is at voltage level 6, namely Y26 is effectively at low level, K61, K64, K65 and K67 in the diode trigger configuration matrix are switched on, diodes D61, D64, D65 and D67 are switched on, row lines VK1, VK4, VK5 and VK7 are triggered and driven to be at low level to switch on the bidirectional thyristors SR1, SR4, SR5 and SR7, other diodes in the diode trigger configuration matrix are switched off, the bidirectional thyristors SR2, SR3, SR6 and SR8 are switched off, and TB1 is enabled to carry out forward compensation; when the input voltage is in a voltage level 4, namely Y24 is effectively in a low level, K41, K44, K46 and K47 in the diode trigger configuration matrix are switched on, diodes D41, D44, D46 and D47 are switched on, row lines VK1, VK4, VK6 and VK7 are triggered and driven to be in a low level to switch on the bidirectional thyristors SR1, SR4, SR6 and SR7, other diodes in the diode trigger configuration matrix are switched off, the bidirectional thyristors SR2, SR3, SR5 and SR8 are switched off, and the forward compensation is carried out on the TBs 1 and the TB2 at the same time; when the input voltage is in a voltage level 1, namely Y21 is effectively in a low level, K11, K13, K16 and K18 in the diode trigger configuration matrix are switched on, diodes D11, D13, D16 and D18 are switched on, row lines VK1, VK3, VK6 and VK8 are triggered and driven to be in a low level to switch on the bidirectional thyristors SR1, SR3, SR6 and SR8, other diodes in the diode trigger configuration matrix are switched off, the bidirectional thyristors SR2, SR4, SR5 and SR7 are switched off, and the forward compensation is carried out on the TBs 2 and the TB3 at the same time; and so on.

TABLE 3

Using the thyristor-triggered-gate configuration circuit embodiment 2 of fig. 14 for compensation control for the compensated main circuit embodiment 2 of fig. 3; setting the fluctuation range of the alternating current power supply voltage as 220V +/-15%, and requiring the alternating current power supply voltage to be stabilized within the range of 220V +/-3.5% for output; at this time, the trigger strobe control value is Y21-Y25 with 5 bits, and 5 trigger control row lines Y21-Y25 in FIG. 14 are selected as the trigger strobe control row lines. Table 4 is a trigger gating configuration table of the thyristor trigger gating configuration circuit at this time, and lists the configuration states of the configuration switches in the diode trigger configuration matrix when the corresponding valid trigger control signals are configured when the trigger gating control values Y21-Y25 of 5 bits are valid respectively. The trigger gating control values Y21-Y25 are respectively corresponding to the voltage level intervals 1-5, and the thyristor trigger gating configuration circuit controls the on-off state of the bidirectional thyristor in the compensation type main circuit embodiment 2 to perform corresponding voltage compensation according to the trigger gating control values through trigger control signals. In table 4, the listed configuration switches need to be configured in the on state, and the unlisted configuration switches need to be configured in the off state; a total of 20 configuration switches in table 4 need to be configured in the on state. For example, when the input voltage is at voltage level 3, that is, Y23 is active at low level, K31, K33, K35 and K37 in the diode-triggered configuration matrix are turned on to turn on diodes D31, D33, D35 and D37, trigger and drive row lines VK1, VK3, VK5 and VK7 to low level to turn on triacs SR1, SR3, SR5 and SR7, and switch off other diodes in the diode-triggered configuration matrix to turn off triacs SR2, SR4, SR6 and SR8, thereby realizing 0-voltage compensation; when the input voltage is in a voltage class 2, namely Y22 is effectively in a low level, K21, K23, K26 and K27 in the diode trigger configuration matrix are switched on, diodes D21, D23, D26 and D27 are switched on, row lines VK1, VK3, VK6 and VK7 are triggered and driven to be in a low level to switch on the bidirectional thyristors SR1, SR3, SR6 and SR7, other diodes in the diode trigger configuration matrix are switched off, the bidirectional thyristors SR2, SR4, SR5 and SR8 are switched off, and TB2 is enabled to carry out forward compensation; when the input voltage is in a voltage level 1, namely Y21 is effectively in a low level, K11, K13, K15 and K18 in the diode trigger configuration matrix are switched on, diodes D11, D13, D15 and D18 are switched on, row lines VK1, VK3, VK5 and VK8 are triggered and driven to be in a low level to switch on the bidirectional thyristors SR1, SR3, SR5 and SR8, other diodes in the diode trigger configuration matrix are switched off, the bidirectional thyristors SR2, SR4, SR6 and SR7 are switched off, and TB3 is enabled to carry out forward compensation; when the input voltage is at voltage level 5, that is, Y25 is at a low level, K52, K54, K56 and K57 in the diode trigger configuration matrix are turned on to turn on diodes D52, D54, D56 and D57, and to trigger and drive row lines VK2, VK4, VK6 and VK7 to turn on triacs SR2, SR4, SR6 and SR7 at a low level, and other diodes in the diode trigger configuration matrix are turned off to turn off triacs SR1, SR3, SR5 and SR8 to perform reverse compensation on TB 2; and so on.

TABLE 4

When the embodiment 2 of the thyristor-triggered gating configuration circuit in fig. 14 is used for performing compensation control on the embodiment 2 of the compensation-type main circuit in fig. 3, a low level in a trigger gating control value needs to directly drive the light-emitting diodes at the input ends of the four ac trigger optocouplers to emit light; when the alternating current trigger optocoupler selects MOC3022, MOC3052 and the like, a driving current of 40mA is needed; when the alternating current trigger optocoupler selects MOC3023, MOC3053 and the like, a driving current of 20mA is required. The embodiment 2 of the thyristor-triggered gating configuration circuit of fig. 14 may also be used to perform compensation control with respect to the embodiment 1 of the compensation-type main circuit of fig. 2, where a low level in the trigger gating control value needs to directly drive the input end light emitting diodes of the three ac trigger optocouplers to emit light; when the alternating current trigger optocoupler selects MOC3022, MOC3052 and the like, a driving current of 30mA is needed; when the alternating current trigger optocoupler selects MOC3023, MOC3053 and the like, 15mA of driving current is needed.

The embodiment 1 of the thyristor-triggered gating configuration circuit of fig. 13 can also be used for compensation control with respect to the embodiment 2 of the self-coupled compensated main circuit of fig. 3, where an increase in the number of trigger control row lines and the number of trigger drive column lines is required. When fig. 13 and fig. 14 are expanded, the diode triggering configuration matrix needs to be provided with configuration branches formed by connecting diodes and configuration switches in series at all intersections of triggering control row lines and triggering driving column lines.

The function of the error detection judging circuit is to enable the output trigger gating control value judging signal P7 to be effective when judging that only one of M bits of the trigger gating control value is effective, or to enable the output trigger gating control value judging signal P7 to be ineffective; that is, when not only one of the M bits of the trigger strobe control value is valid, or when no one of the M bits of the trigger strobe control value is valid, the output trigger strobe control value determination signal P7 is invalidated.

FIG. 15 shows an error detection and determination circuit in embodiment 1, with inputs Y21-Y27, for determining the trigger strobe control value P3, which is active high and m is 7, i.e., at most 7 bits; the output trigger gating control value judges whether the signal P7 is effective at high level or ineffective at low level; that is, the output P7 is 1, indicating that the trigger strobe control value is valid; the output P7 is 0 indicating that the trigger strobe control value is invalid. In fig. 15, FD3 is a ROM memory having a 10-bit address input and a 1-bit data output, 7-bit trigger strobe control values Y21-Y27 are connected to 7-bit address inputs a0-a6 via strobe switches k1-k7, respectively, and a trigger strobe control value decision signal P7 is output from a data output terminal D0; pull-down resistors RX1-RX7 are used to pull down the corresponding ROM memory input signal to a low level when the gate switches are open. Table 5 is a logical truth table of the error detection and discrimination circuit in embodiment 1, and is also a table of contents of memory cells in the ROM memory in fig. 15.

The contents of the ROM memory storage unit in fig. 15 are written in accordance with the data of table 5. If the input trigger strobe control value P3 is 7 bits, i.e., M equals 7, then the strobe switches k1-k7 in FIG. 15 are all closed and the 7-bit trigger strobe control values Y21-Y27 are all actually input to the 7-bit address inputs A0-A6 of the ROM memory. In table 5, only one of the 7 bits Y21-Y27 of the trigger strobe control value is valid 1, the output trigger strobe control value decision signal P7 is made valid 1, otherwise the output trigger strobe control value decision signal P7 is made invalid 0, which satisfies the functional requirements of the error detection decision circuit.

In FIG. 15, if the input trigger gate control value P3 is 3 bits, i.e. M equals to 3, then the gate switches k1-k3 in FIG. 15 are closed and k4-k7 are opened; the 3-bit trigger strobe control value Y21-Y23 is actually input to the 3-bit address input A0-A2 of the ROM memory, and the other 4-bit address input A3-A6 of the ROM memory is pulled down to 0 by a pull-down resistor; at this time, the input conditions of the 4 th to 7 th rows in table 5 cannot be generated, and only one of the 3 bits Y21-Y23 of the trigger strobe control value is valid 1, the output trigger strobe control value determination signal P7 is made to be valid 1, otherwise the output trigger strobe control value determination signal P7 is made to be invalid 0, so as to satisfy the functional requirements of the error detection determination circuit.

TABLE 5

In fig. 15, if the trigger strobe control value determination signal P7 to be output is active at low and inactive at high, all the contents of the last 1 column data in table 5 need to be changed from 0 to 1 and from 1 to 0.

FIG. 16 shows an error detection and determination circuit of embodiment 2, with inputs Y21-Y210, for determining the trigger strobe control value P3, which is active at low level and m is 10, i.e., 10 bits at most; the output trigger gating control value judges whether the signal P7 is effective at high level or ineffective at low level; that is, the output P7 is 1, indicating that the trigger strobe control value is valid; the output P7 is 0 indicating that the trigger strobe control value is invalid. In fig. 16, FD4 is a ROM memory having a 10-bit address input and a 1-bit data output, 10-bit trigger strobe control values Y21-Y210 are connected to the 10-bit address input a0-a9 via strobe switches j1-j10, respectively, and a trigger strobe control value decision signal P7 is output from a data output terminal D0; pull-up resistors RJ1-RJ10 are used to pull up the corresponding ROM memory input signal to a high level when the gating switches are open. Table 6 is a logical truth table of the error detection and discrimination circuit in embodiment 2, and is also a table of the cell contents data of the ROM memory in fig. 16.

The contents of the ROM memory storage unit in fig. 16 are written in accordance with the data of table 6. If the input trigger strobe control value P3 is 10 bits, i.e., M equals 10, then the strobe switches j1-j10 in FIG. 16 are all closed and the 10-bit trigger strobe control values Y21-Y210 are all actually input to the 10-bit address inputs A0-A9 of the ROM memory. In table 6, only one of the 10 bits Y21-Y210 of the trigger strobe control value is a valid 1, the output trigger strobe control value determination signal P7 is a valid 1, otherwise, the output trigger strobe control value determination signal P7 is an invalid 0, so as to satisfy the functional requirements of the error detection determination circuit.

In FIG. 16, if the input trigger gate control value P3 is 9 bits, i.e., M equals 9, then the gate switches k1-k9 in FIG. 16 are closed and k10 is opened; the 9-bit trigger strobe control value Y21-Y29 is actually input to 9-bit address inputs A0-A8 of the ROM memory, and the other 1-bit address input A9 of the ROM memory is pulled up to 1 by a pull-up resistor; at this time, the input condition of the 10 th row in table 6 cannot be generated, and only one valid 0 out of the 9 bits Y21-Y29 of the trigger strobe control value makes the output trigger strobe control value decision signal P7 be a valid 1, otherwise makes the output trigger strobe control value decision signal P7 be a invalid 0, so as to satisfy the functional requirement of the error detection decision circuit.

In FIG. 16, if the input trigger strobe control value P3 is 7 bits, i.e., M equals 7, then the strobe switches j1-j7 in FIG. 15 are closed and j8-j10 are opened; the 7-bit trigger strobe control value Y21-Y27 is actually input to the 7-bit address input A0-A6 of the ROM memory, and the other 3-bit address input A7-A9 of the ROM memory is pulled up to 0 by a pull-up resistor; at this time, the input conditions of the 8 th to 10 th rows in table 6 cannot be generated, and only one valid 0 out of the 7 bits Y21 to Y27 of the trigger strobe control value makes the output trigger strobe control value decision signal P7 be a valid 1, otherwise makes the output trigger strobe control value decision signal P7 be a invalid 0, so as to satisfy the functional requirements of the error detection decision circuit.

In fig. 16, if the trigger strobe control value determination signal P7 to be output is active at a low level and inactive at a high level, all the contents of the data in the last 1 column in table 6 need to be changed from 0 to 1, and from 1 to 0.

TABLE 6

In

embodiments

1 and 2 of the sampling comparison unit, when M is smaller than M, except for the M-bit trigger gating control value, the state of other comparison output values of M-M bits and the state after delay of the signals sent to the delay protection unit by the sampling comparison unit are the same as the state of an invalid bit in the M-bit trigger gating control value, and the judgment on whether the M-bit trigger gating control value is valid or not is not influenced; thus, at this time, the gate switches k1-k7 and the pull-down resistors RX1-RX7 in FIG. 15 may be eliminated, and the 7-bit comparison output values Y21-Y27 are directly connected to the 7-bit address inputs A0-A6 of the ROM memory; the gating switches j1-j10 and pull-up resistors RJ1-RJ10 in FIG. 16 may be eliminated, and the 10-bit comparison output values Y21-Y210 may be directly connected to the 10-bit address inputs A0-A9 of the ROM memory.

The logic function of the error detection and discrimination circuit can also be realized in other ways, for example, tables 5 and 6 are logic truth tables, and the function can be realized by combining with or not logic gate. The ROM memory in the error detection judging circuit or the logic gate is adopted to realize the function, and the single power supply + VCC1 is adopted to supply power.

FIG. 17 shows an embodiment of a protection driving circuit, wherein the high level of the input trigger gate control value determining signal P7 is asserted, i.e. P7 is 1, which indicates that the trigger gate control value is asserted; the P7 is inactive low, i.e., P7 is 0, indicating that the trigger strobe control value is inactive. The low level of an input control signal P4 of the non-trigger area is effective, namely when P4 is equal to 0, the fact that the alternating current power supply voltage fluctuates indicates that the trigger gating control value changes needs to be switched on and off states of a bidirectional thyristor in a thyristor bridge, and a compensation mode is changed; in the switching process, in order to avoid the power supply short circuit caused by the factor of delayed turn-off of the bidirectional thyristor when the upper and lower bridge arms in the thyristor bridge are switched, all the bidirectional thyristors in the thyristor bridge are turned off during the period when the control signal of the trigger zone is not valid, i.e., when P4 in the embodiment is equal to 0.

In fig. 17, a transistor VT, a relay coil KA, a freewheeling diode VD, and a resistor RK1 form a protection control circuit, a transistor VK1, a transistor VK2, a resistor RK2, a resistor RK3, and an and gate FY21 form a controlled power control circuit of a trigger circuit, and the and gate FY21 is powered by a single power supply + VCC 1. + VCC2 is the power supply for the relay coil and the source supply for the controlled power supply + VCCK in the trigger circuit. When the input trigger gating control value judging signal P7 is at a low level, namely the trigger gating control value is invalid, the AND gate FY21 outputs a low level, the triodes VK1 and VK2 are cut off, the controlled power supply + VCCK loses power, the trigger circuit does not have a power supply, does not work, and does not send out trigger pulses for triggering the bidirectional thyristor; p7 is a low level and simultaneously controls the cutoff of the triode VT, the relay coil KA loses power, so that the normally open switches KA-1, KA-2 and KA-3 of the relay in the embodiment 1 of the compensation type main circuit in the figure 2 are disconnected, or the normally open switches KA-1, KA-2, KA-3 and KA-4 of the relay in the embodiment 2 of the compensation type main circuit in the figure 3 are disconnected, and the open circuit protection of the thyristor bridge is realized; the control is performed such that the normally closed relay switches KA-5 and KA-6 in the compensation main circuit example 1 of fig. 2 are closed to set the voltage applied to the exciting coil TB1 and TB2 to 0, or the control is performed such that the normally closed relay switches KA-5, KA-6 and KA-7 in the compensation main circuit example 2 of fig. 3 are closed to set the voltage applied to the exciting coil TB1, TB2 and TB3 to 0. When the sampling comparison circuit fails to work to cause the trigger gating control value to be invalid, or the input alternating current power supply voltage is lower than the range of the minimum voltage level interval to cause the output trigger gating control value to be invalid, the protection driving circuit cuts off the power supply of the trigger circuit no matter whether the input non-trigger area control signal P4 is valid or not, stops sending out trigger pulses of all bidirectional thyristors, and simultaneously controls to cut off all bridge arms of the thyristor bridge to realize open-circuit protection of the thyristor bridge. When the input trigger gating control value judging signal P7 is at a high level, that is, the trigger gating control value is valid, the control triode VT is turned on, and the relay coil KA is powered on, so that the normally open switches KA-1, KA-2, KA-3 of the relay in the compensation main circuit embodiment 1 in fig. 2 are closed, and the normally closed switches KA-5, KA-6 of the relay are opened, or the normally open switches KA-1, KA-2, KA-3, KA-4 of the relay in the compensation main circuit embodiment 2 in fig. 3 are closed, and the normally closed switches KA-5, KA-6, KA-7 of the relay are opened, and the thyristor bridge is in a compensation working state. When the trigger gating control value is valid, namely P7 is 1, and the control signal of the non-trigger area is valid, namely P4 is equal to 0, the AND gate FY21 outputs low level, the triodes VK1 and VK2 are cut off, the controlled power supply + VCCK loses power, the trigger circuit does not work, namely trigger pulse for triggering the bidirectional thyristor is not sent out, all the bidirectional thyristors in the thyristor bridge are cut off, the alternating current power supply voltage is fluctuated at the moment, the trigger gating control value is changed, the electronic switch needs to be switched, and the compensation mode is changed. When the trigger gating control value is valid, namely P7 is 1, and the control signal of the non-trigger area is invalid, namely P4 is equal to 1, the AND gate FY21 outputs high level, the triodes VK1 and VK2 are both conducted, the controlled power supply + VCCK is electrified, the trigger circuit works normally, the thyristor trigger gating configuration circuit selects the corresponding trigger control signal to be valid according to the valid trigger gating control value corresponding to a certain voltage grade interval, the trigger circuit sends out trigger pulse to control the on-off state of the bidirectional thyristor in the thyristor bridge, and the main circuit is in the compensation working state corresponding to the voltage grade interval.

When the error detection judging circuit judges that the input trigger gating control value is invalid, the protection driving circuit sends a protection control signal to the main circuit, so that the thyristor bridge is in an open circuit protection state, the alternating current voltage stabilizer does not compensate the input voltage, and the voltage output by the voltage stabilizer is the input alternating current power supply voltage. When the thyristor bridge is in the open-circuit protection state, if the error detection judging circuit judges that the input trigger gating control value is recovered to be an effective signal, the protection driving circuit automatically stops the open-circuit protection state of the thyristor bridge, and the thyristor bridge is in the compensation working state again.

As can be known from the above embodiments and the working process thereof, when the input is an effective trigger gating control value, the thyristor trigger gating configuration circuit ensures that the bidirectional thyristors of the upper and lower bridge arms of the same full-bridge circuit are not simultaneously conducted, that is, the interlocking control of the bidirectional thyristors of the upper and lower bridge arms of the same full-bridge circuit is realized; when the trigger gating control value is invalid, the protection driving circuit simultaneously disconnects all bridge arms of the thyristor bridge on the basis of rapidly cutting off a power supply of the trigger circuit and avoiding short circuit caused by error conduction of the bidirectional thyristor, so that the thyristor bridge is in an open-circuit protection state. When the thyristor bridge is in the open-circuit protection state, if the error detection judging circuit judges that the alternating-current voltage stabilizer enters the normal logic control state again, namely the error detection judging circuit judges that the input trigger gating control value is recovered to be an effective signal, the protection driving circuit can automatically stop the open-circuit protection state of the thyristor bridge and enable the thyristor bridge to be in the compensation working state again. The function effectively strengthens the protection force of the AC voltage stabilizer against the abnormity of the working process, and the work of the partition compensation AC voltage stabilizer is more reliable.

Other techniques of the present invention than the technical features described in the specification are conventional techniques which are known to those skilled in the art.

Claims

1. A thyristor triggering gating configuration method is used for controlling the on-off combined state of thyristors in a thyristor bridge and is characterized in that: controlling the output trigger control signal through a diode trigger configuration matrix according to the input trigger gating control value to realize the control of the on-off combination state of the thyristor in the thyristor bridge; triggering a gating control value to be an M-bit binary value; configuring the diode trigger configuration matrix, and changing the on-off combination state of the thyristors in the thyristor bridge corresponding to each trigger gating control value; one and only one of the M binary values triggering the gating control value is valid; m is an integer greater than or equal to 2;

the thyristor bridge is provided with N thyristors; the diode trigger configuration matrix comprises m trigger control row lines and N trigger drive column lines; the N triggering driving column lines correspond to the N thyristors one by one, and the signal of one triggering driving column line effectively corresponds to the triggering control signal of one thyristor; a configuration branch circuit formed by connecting a diode and a configuration switch in series is arranged at the crossing position of each trigger control row line and each trigger driving column line; when the trigger control row line signal is active at a low level, the cathode side of the diode of the configuration branch is connected to the trigger control row line, and the anode side of the diode of the configuration branch is connected to the trigger driving column line; when the trigger control row line signal is high level and effective, the anode side of the diode of the configuration branch is connected to the trigger control row line, and the cathode side of the diode is connected to the trigger drive column line; m is greater than or equal to 3, and M is less than or equal to M; the N is more than or equal to 4;

when one and only one of the M binary values of the trigger gating control value is valid, the trigger gating control value is valid; otherwise, triggering the gating control value to be invalid;

the configuration method of the configuration switch in the configuration branch circuit is that M of M trigger control row lines are selected as trigger gating control row lines; m triggering gating control row lines correspond to M effective triggering gating control values one by one, and one effective triggering gating control value correspondingly enables a signal of one triggering gating control row line to be effective; when one trigger gating control row line signal is effective, the on-off combination state of a thyristor in a corresponding thyristor bridge is corresponded; configuring a configuration switch in a configuration branch between each trigger gating control row line and a trigger driving row line which is in a corresponding on-off combination state and needs to control the conduction of a thyristor when a signal of the row line is effective into an on state; configuring a configuration switch in a configuration branch between each trigger gating control row line and a trigger driving row line which is in a corresponding on-off combination state and needs to control the turn-off of the thyristor when the row line signal is effective into an off state;

the thyristor triggering gating configuration method is realized by a thyristor triggering gating configuration circuit and is used for on-off combination control of a thyristor bridge in the partition compensation alternating current voltage stabilizer;

and adjusting the voltage in the alternating current power supply voltage fluctuation interval range into M voltage grade intervals, wherein the M voltage grade intervals correspond to the M effective trigger gating control values one by one.

2. The thyristor-triggered-gating configuration method of claim 1, wherein: the method for enabling the trigger control signal of one thyristor to be effective by enabling one trigger driving column line signal to be effective is that N trigger driving column line signals are directly used as the trigger control signals of N thyristors.

3. The thyristor-triggered-gating configuration method of claim 1, wherein: the method for enabling the trigger control signal of a thyristor to be effective by enabling a trigger driving column line signal to be effective correspondingly is realized by a trigger control signal driving circuit; the input of the trigger control signal driving circuit is signals of N trigger driving column lines, and the output is trigger control signals of N thyristors.

4. A thyristor triggered gating configuration method according to any one of claims 1-3, characterized in that: the partition compensation alternating current voltage stabilizer comprises a compensation type main circuit, a sampling comparison circuit, a delay protection circuit, a thyristor trigger gating configuration circuit, a trigger circuit, an error detection judgment circuit and a protection driving circuit;

the compensation type main circuit comprises a compensation transformer bank, a thyristor bridge and a relay protection switch.

5. The thyristor-triggered-gating configuration method of claim 4, wherein: the sampling comparison circuit adjusts the voltage in the alternating current power supply voltage fluctuation interval range into M voltage grade intervals and outputs M-bit trigger gating control values; each voltage grade interval corresponds to a voltage compensation state, and different voltage compensation states are controlled by different on-off combination states of thyristors in the thyristor bridge.

6. The thyristor-triggered-gating configuration method of claim 5, wherein: the delay protection circuit inputs a trigger gating control value and outputs a delayed trigger gating control value and a non-trigger area control signal; the control signal of the non-trigger area outputs a single pulse after the trigger gating control value is changed; the no-trigger area control signal is active during the output of a single pulse and inactive during the non-output of a single pulse.

7. The thyristor-triggered-gating configuration method of claim 6, wherein: the error detection judging circuit judges whether the input trigger gating control value is effective or not.

8. The thyristor-triggered-gating configuration method of claim 6, wherein: the specific method for stopping/starting the open-circuit protection of the thyristor bridge by the protection driving circuit according to whether the trigger gating control value is effective is that when the trigger gating control value is ineffective, all upper bridge arms of the thyristor bridge are controlled to be disconnected to enable the thyristor bridge to be in an open-circuit protection state, or all lower bridge arms of the thyristor bridge are controlled to be disconnected to enable the thyristor bridge to be in the open-circuit protection state; the protection driving circuit controls the power supply of the trigger circuit according to whether the trigger gating control value is effective or not and whether the control signal of the non-trigger area is effective or not.